1 //===-- ARMInstrNEON.td - NEON support for ARM -------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVI32NegAsmOperand : AsmOperandClass { let Name = "NEONi32vmovNeg"; }
43 def nImmVMOVI32Neg : Operand<i32> {
44 let PrintMethod = "printNEONModImmOperand";
45 let ParserMatchClass = nImmVMOVI32NegAsmOperand;
47 def nImmVMOVF32 : Operand<i32> {
48 let PrintMethod = "printFPImmOperand";
49 let ParserMatchClass = FPImmOperand;
51 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
52 def nImmSplatI64 : Operand<i32> {
53 let PrintMethod = "printNEONModImmOperand";
54 let ParserMatchClass = nImmSplatI64AsmOperand;
57 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
58 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
59 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
60 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
61 return ((uint64_t)Imm) < 8;
63 let ParserMatchClass = VectorIndex8Operand;
64 let PrintMethod = "printVectorIndex";
65 let MIOperandInfo = (ops i32imm);
67 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
68 return ((uint64_t)Imm) < 4;
70 let ParserMatchClass = VectorIndex16Operand;
71 let PrintMethod = "printVectorIndex";
72 let MIOperandInfo = (ops i32imm);
74 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
75 return ((uint64_t)Imm) < 2;
77 let ParserMatchClass = VectorIndex32Operand;
78 let PrintMethod = "printVectorIndex";
79 let MIOperandInfo = (ops i32imm);
82 // Register list of one D register.
83 def VecListOneDAsmOperand : AsmOperandClass {
84 let Name = "VecListOneD";
85 let ParserMethod = "parseVectorList";
86 let RenderMethod = "addVecListOperands";
88 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
89 let ParserMatchClass = VecListOneDAsmOperand;
91 // Register list of two sequential D registers.
92 def VecListDPairAsmOperand : AsmOperandClass {
93 let Name = "VecListDPair";
94 let ParserMethod = "parseVectorList";
95 let RenderMethod = "addVecListOperands";
97 def VecListDPair : RegisterOperand<DPair, "printVectorListTwo"> {
98 let ParserMatchClass = VecListDPairAsmOperand;
100 // Register list of three sequential D registers.
101 def VecListThreeDAsmOperand : AsmOperandClass {
102 let Name = "VecListThreeD";
103 let ParserMethod = "parseVectorList";
104 let RenderMethod = "addVecListOperands";
106 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
107 let ParserMatchClass = VecListThreeDAsmOperand;
109 // Register list of four sequential D registers.
110 def VecListFourDAsmOperand : AsmOperandClass {
111 let Name = "VecListFourD";
112 let ParserMethod = "parseVectorList";
113 let RenderMethod = "addVecListOperands";
115 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
116 let ParserMatchClass = VecListFourDAsmOperand;
118 // Register list of two D registers spaced by 2 (two sequential Q registers).
119 def VecListDPairSpacedAsmOperand : AsmOperandClass {
120 let Name = "VecListDPairSpaced";
121 let ParserMethod = "parseVectorList";
122 let RenderMethod = "addVecListOperands";
124 def VecListDPairSpaced : RegisterOperand<DPair, "printVectorListTwoSpaced"> {
125 let ParserMatchClass = VecListDPairSpacedAsmOperand;
127 // Register list of three D registers spaced by 2 (three Q registers).
128 def VecListThreeQAsmOperand : AsmOperandClass {
129 let Name = "VecListThreeQ";
130 let ParserMethod = "parseVectorList";
131 let RenderMethod = "addVecListOperands";
133 def VecListThreeQ : RegisterOperand<DPR, "printVectorListThreeSpaced"> {
134 let ParserMatchClass = VecListThreeQAsmOperand;
136 // Register list of three D registers spaced by 2 (three Q registers).
137 def VecListFourQAsmOperand : AsmOperandClass {
138 let Name = "VecListFourQ";
139 let ParserMethod = "parseVectorList";
140 let RenderMethod = "addVecListOperands";
142 def VecListFourQ : RegisterOperand<DPR, "printVectorListFourSpaced"> {
143 let ParserMatchClass = VecListFourQAsmOperand;
146 // Register list of one D register, with "all lanes" subscripting.
147 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
148 let Name = "VecListOneDAllLanes";
149 let ParserMethod = "parseVectorList";
150 let RenderMethod = "addVecListOperands";
152 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
153 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
155 // Register list of two D registers, with "all lanes" subscripting.
156 def VecListDPairAllLanesAsmOperand : AsmOperandClass {
157 let Name = "VecListDPairAllLanes";
158 let ParserMethod = "parseVectorList";
159 let RenderMethod = "addVecListOperands";
161 def VecListDPairAllLanes : RegisterOperand<DPair,
162 "printVectorListTwoAllLanes"> {
163 let ParserMatchClass = VecListDPairAllLanesAsmOperand;
165 // Register list of two D registers spaced by 2 (two sequential Q registers).
166 def VecListDPairSpacedAllLanesAsmOperand : AsmOperandClass {
167 let Name = "VecListDPairSpacedAllLanes";
168 let ParserMethod = "parseVectorList";
169 let RenderMethod = "addVecListOperands";
171 def VecListDPairSpacedAllLanes : RegisterOperand<DPair,
172 "printVectorListTwoSpacedAllLanes"> {
173 let ParserMatchClass = VecListDPairSpacedAllLanesAsmOperand;
175 // Register list of three D registers, with "all lanes" subscripting.
176 def VecListThreeDAllLanesAsmOperand : AsmOperandClass {
177 let Name = "VecListThreeDAllLanes";
178 let ParserMethod = "parseVectorList";
179 let RenderMethod = "addVecListOperands";
181 def VecListThreeDAllLanes : RegisterOperand<DPR,
182 "printVectorListThreeAllLanes"> {
183 let ParserMatchClass = VecListThreeDAllLanesAsmOperand;
185 // Register list of three D registers spaced by 2 (three sequential Q regs).
186 def VecListThreeQAllLanesAsmOperand : AsmOperandClass {
187 let Name = "VecListThreeQAllLanes";
188 let ParserMethod = "parseVectorList";
189 let RenderMethod = "addVecListOperands";
191 def VecListThreeQAllLanes : RegisterOperand<DPR,
192 "printVectorListThreeSpacedAllLanes"> {
193 let ParserMatchClass = VecListThreeQAllLanesAsmOperand;
195 // Register list of four D registers, with "all lanes" subscripting.
196 def VecListFourDAllLanesAsmOperand : AsmOperandClass {
197 let Name = "VecListFourDAllLanes";
198 let ParserMethod = "parseVectorList";
199 let RenderMethod = "addVecListOperands";
201 def VecListFourDAllLanes : RegisterOperand<DPR, "printVectorListFourAllLanes"> {
202 let ParserMatchClass = VecListFourDAllLanesAsmOperand;
204 // Register list of four D registers spaced by 2 (four sequential Q regs).
205 def VecListFourQAllLanesAsmOperand : AsmOperandClass {
206 let Name = "VecListFourQAllLanes";
207 let ParserMethod = "parseVectorList";
208 let RenderMethod = "addVecListOperands";
210 def VecListFourQAllLanes : RegisterOperand<DPR,
211 "printVectorListFourSpacedAllLanes"> {
212 let ParserMatchClass = VecListFourQAllLanesAsmOperand;
216 // Register list of one D register, with byte lane subscripting.
217 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
218 let Name = "VecListOneDByteIndexed";
219 let ParserMethod = "parseVectorList";
220 let RenderMethod = "addVecListIndexedOperands";
222 def VecListOneDByteIndexed : Operand<i32> {
223 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
224 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
226 // ...with half-word lane subscripting.
227 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
228 let Name = "VecListOneDHWordIndexed";
229 let ParserMethod = "parseVectorList";
230 let RenderMethod = "addVecListIndexedOperands";
232 def VecListOneDHWordIndexed : Operand<i32> {
233 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
234 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
236 // ...with word lane subscripting.
237 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
238 let Name = "VecListOneDWordIndexed";
239 let ParserMethod = "parseVectorList";
240 let RenderMethod = "addVecListIndexedOperands";
242 def VecListOneDWordIndexed : Operand<i32> {
243 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
244 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
247 // Register list of two D registers with byte lane subscripting.
248 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
249 let Name = "VecListTwoDByteIndexed";
250 let ParserMethod = "parseVectorList";
251 let RenderMethod = "addVecListIndexedOperands";
253 def VecListTwoDByteIndexed : Operand<i32> {
254 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
255 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
257 // ...with half-word lane subscripting.
258 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
259 let Name = "VecListTwoDHWordIndexed";
260 let ParserMethod = "parseVectorList";
261 let RenderMethod = "addVecListIndexedOperands";
263 def VecListTwoDHWordIndexed : Operand<i32> {
264 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
265 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
267 // ...with word lane subscripting.
268 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
269 let Name = "VecListTwoDWordIndexed";
270 let ParserMethod = "parseVectorList";
271 let RenderMethod = "addVecListIndexedOperands";
273 def VecListTwoDWordIndexed : Operand<i32> {
274 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
277 // Register list of two Q registers with half-word lane subscripting.
278 def VecListTwoQHWordIndexAsmOperand : AsmOperandClass {
279 let Name = "VecListTwoQHWordIndexed";
280 let ParserMethod = "parseVectorList";
281 let RenderMethod = "addVecListIndexedOperands";
283 def VecListTwoQHWordIndexed : Operand<i32> {
284 let ParserMatchClass = VecListTwoQHWordIndexAsmOperand;
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
287 // ...with word lane subscripting.
288 def VecListTwoQWordIndexAsmOperand : AsmOperandClass {
289 let Name = "VecListTwoQWordIndexed";
290 let ParserMethod = "parseVectorList";
291 let RenderMethod = "addVecListIndexedOperands";
293 def VecListTwoQWordIndexed : Operand<i32> {
294 let ParserMatchClass = VecListTwoQWordIndexAsmOperand;
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
299 // Register list of three D registers with byte lane subscripting.
300 def VecListThreeDByteIndexAsmOperand : AsmOperandClass {
301 let Name = "VecListThreeDByteIndexed";
302 let ParserMethod = "parseVectorList";
303 let RenderMethod = "addVecListIndexedOperands";
305 def VecListThreeDByteIndexed : Operand<i32> {
306 let ParserMatchClass = VecListThreeDByteIndexAsmOperand;
307 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
309 // ...with half-word lane subscripting.
310 def VecListThreeDHWordIndexAsmOperand : AsmOperandClass {
311 let Name = "VecListThreeDHWordIndexed";
312 let ParserMethod = "parseVectorList";
313 let RenderMethod = "addVecListIndexedOperands";
315 def VecListThreeDHWordIndexed : Operand<i32> {
316 let ParserMatchClass = VecListThreeDHWordIndexAsmOperand;
317 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
319 // ...with word lane subscripting.
320 def VecListThreeDWordIndexAsmOperand : AsmOperandClass {
321 let Name = "VecListThreeDWordIndexed";
322 let ParserMethod = "parseVectorList";
323 let RenderMethod = "addVecListIndexedOperands";
325 def VecListThreeDWordIndexed : Operand<i32> {
326 let ParserMatchClass = VecListThreeDWordIndexAsmOperand;
327 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
329 // Register list of three Q registers with half-word lane subscripting.
330 def VecListThreeQHWordIndexAsmOperand : AsmOperandClass {
331 let Name = "VecListThreeQHWordIndexed";
332 let ParserMethod = "parseVectorList";
333 let RenderMethod = "addVecListIndexedOperands";
335 def VecListThreeQHWordIndexed : Operand<i32> {
336 let ParserMatchClass = VecListThreeQHWordIndexAsmOperand;
337 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
339 // ...with word lane subscripting.
340 def VecListThreeQWordIndexAsmOperand : AsmOperandClass {
341 let Name = "VecListThreeQWordIndexed";
342 let ParserMethod = "parseVectorList";
343 let RenderMethod = "addVecListIndexedOperands";
345 def VecListThreeQWordIndexed : Operand<i32> {
346 let ParserMatchClass = VecListThreeQWordIndexAsmOperand;
347 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
350 // Register list of four D registers with byte lane subscripting.
351 def VecListFourDByteIndexAsmOperand : AsmOperandClass {
352 let Name = "VecListFourDByteIndexed";
353 let ParserMethod = "parseVectorList";
354 let RenderMethod = "addVecListIndexedOperands";
356 def VecListFourDByteIndexed : Operand<i32> {
357 let ParserMatchClass = VecListFourDByteIndexAsmOperand;
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
360 // ...with half-word lane subscripting.
361 def VecListFourDHWordIndexAsmOperand : AsmOperandClass {
362 let Name = "VecListFourDHWordIndexed";
363 let ParserMethod = "parseVectorList";
364 let RenderMethod = "addVecListIndexedOperands";
366 def VecListFourDHWordIndexed : Operand<i32> {
367 let ParserMatchClass = VecListFourDHWordIndexAsmOperand;
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
370 // ...with word lane subscripting.
371 def VecListFourDWordIndexAsmOperand : AsmOperandClass {
372 let Name = "VecListFourDWordIndexed";
373 let ParserMethod = "parseVectorList";
374 let RenderMethod = "addVecListIndexedOperands";
376 def VecListFourDWordIndexed : Operand<i32> {
377 let ParserMatchClass = VecListFourDWordIndexAsmOperand;
378 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
380 // Register list of four Q registers with half-word lane subscripting.
381 def VecListFourQHWordIndexAsmOperand : AsmOperandClass {
382 let Name = "VecListFourQHWordIndexed";
383 let ParserMethod = "parseVectorList";
384 let RenderMethod = "addVecListIndexedOperands";
386 def VecListFourQHWordIndexed : Operand<i32> {
387 let ParserMatchClass = VecListFourQHWordIndexAsmOperand;
388 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
390 // ...with word lane subscripting.
391 def VecListFourQWordIndexAsmOperand : AsmOperandClass {
392 let Name = "VecListFourQWordIndexed";
393 let ParserMethod = "parseVectorList";
394 let RenderMethod = "addVecListIndexedOperands";
396 def VecListFourQWordIndexed : Operand<i32> {
397 let ParserMatchClass = VecListFourQWordIndexAsmOperand;
398 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
401 def dword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
402 return cast<LoadSDNode>(N)->getAlignment() >= 8;
404 def dword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
405 (store node:$val, node:$ptr), [{
406 return cast<StoreSDNode>(N)->getAlignment() >= 8;
408 def word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
409 return cast<LoadSDNode>(N)->getAlignment() == 4;
411 def word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
412 (store node:$val, node:$ptr), [{
413 return cast<StoreSDNode>(N)->getAlignment() == 4;
415 def hword_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
416 return cast<LoadSDNode>(N)->getAlignment() == 2;
418 def hword_alignedstore : PatFrag<(ops node:$val, node:$ptr),
419 (store node:$val, node:$ptr), [{
420 return cast<StoreSDNode>(N)->getAlignment() == 2;
422 def byte_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
423 return cast<LoadSDNode>(N)->getAlignment() == 1;
425 def byte_alignedstore : PatFrag<(ops node:$val, node:$ptr),
426 (store node:$val, node:$ptr), [{
427 return cast<StoreSDNode>(N)->getAlignment() == 1;
429 def non_word_alignedload : PatFrag<(ops node:$ptr), (load node:$ptr), [{
430 return cast<LoadSDNode>(N)->getAlignment() < 4;
432 def non_word_alignedstore : PatFrag<(ops node:$val, node:$ptr),
433 (store node:$val, node:$ptr), [{
434 return cast<StoreSDNode>(N)->getAlignment() < 4;
437 //===----------------------------------------------------------------------===//
438 // NEON-specific DAG Nodes.
439 //===----------------------------------------------------------------------===//
441 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
442 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
444 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
445 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
446 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
447 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
448 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
449 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
450 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
451 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
452 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
453 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
454 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
456 // Types for vector shift by immediates. The "SHX" version is for long and
457 // narrow operations where the source and destination vectors have different
458 // types. The "SHINS" version is for shift and insert operations.
459 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
461 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
463 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
464 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
466 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
467 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
468 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
469 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
471 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
472 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
473 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
475 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
476 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
477 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
478 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
479 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
480 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
482 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
483 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
484 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
486 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
487 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
489 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
491 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
492 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
494 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
495 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
496 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
497 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
499 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
501 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
502 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
504 def NEONvbsl : SDNode<"ARMISD::VBSL",
505 SDTypeProfile<1, 3, [SDTCisVec<0>,
508 SDTCisSameAs<0, 3>]>>;
510 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
512 // VDUPLANE can produce a quad-register result from a double-register source,
513 // so the result is not constrained to match the source.
514 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
515 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
518 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
519 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
520 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
522 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
523 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
524 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
525 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
527 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
529 SDTCisSameAs<0, 3>]>;
530 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
531 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
532 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
534 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
535 SDTCisSameAs<1, 2>]>;
536 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
537 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
539 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
540 SDTCisSameAs<0, 2>]>;
541 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
542 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
544 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
545 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
546 unsigned EltBits = 0;
547 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
548 return (EltBits == 32 && EltVal == 0);
551 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
552 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
553 unsigned EltBits = 0;
554 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
555 return (EltBits == 8 && EltVal == 0xff);
558 //===----------------------------------------------------------------------===//
559 // NEON load / store instructions
560 //===----------------------------------------------------------------------===//
562 // Use VLDM to load a Q register as a D register pair.
563 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
565 : PseudoVFPLdStM<(outs DPair:$dst), (ins GPR:$Rn),
567 [(set DPair:$dst, (v2f64 (load GPR:$Rn)))]>;
569 // Use VSTM to store a Q register as a D register pair.
570 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
572 : PseudoVFPLdStM<(outs), (ins DPair:$src, GPR:$Rn),
574 [(store (v2f64 DPair:$src), GPR:$Rn)]>;
576 // Classes for VLD* pseudo-instructions with multi-register operands.
577 // These are expanded to real instructions after register allocation.
578 class VLDQPseudo<InstrItinClass itin>
579 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
580 class VLDQWBPseudo<InstrItinClass itin>
581 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
582 (ins addrmode6:$addr, am6offset:$offset), itin,
584 class VLDQWBfixedPseudo<InstrItinClass itin>
585 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
586 (ins addrmode6:$addr), itin,
588 class VLDQWBregisterPseudo<InstrItinClass itin>
589 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
590 (ins addrmode6:$addr, rGPR:$offset), itin,
593 class VLDQQPseudo<InstrItinClass itin>
594 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
595 class VLDQQWBPseudo<InstrItinClass itin>
596 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
597 (ins addrmode6:$addr, am6offset:$offset), itin,
599 class VLDQQWBfixedPseudo<InstrItinClass itin>
600 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
601 (ins addrmode6:$addr), itin,
603 class VLDQQWBregisterPseudo<InstrItinClass itin>
604 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
605 (ins addrmode6:$addr, rGPR:$offset), itin,
609 class VLDQQQQPseudo<InstrItinClass itin>
610 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
612 class VLDQQQQWBPseudo<InstrItinClass itin>
613 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
614 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
615 "$addr.addr = $wb, $src = $dst">;
617 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
619 // VLD1 : Vector Load (multiple single elements)
620 class VLD1D<bits<4> op7_4, string Dt, Operand AddrMode>
621 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
622 (ins AddrMode:$Rn), IIC_VLD1,
623 "vld1", Dt, "$Vd, $Rn", "", []> {
626 let DecoderMethod = "DecodeVLDST1Instruction";
628 class VLD1Q<bits<4> op7_4, string Dt, Operand AddrMode>
629 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd),
630 (ins AddrMode:$Rn), IIC_VLD1x2,
631 "vld1", Dt, "$Vd, $Rn", "", []> {
633 let Inst{5-4} = Rn{5-4};
634 let DecoderMethod = "DecodeVLDST1Instruction";
637 def VLD1d8 : VLD1D<{0,0,0,?}, "8", addrmode6align64>;
638 def VLD1d16 : VLD1D<{0,1,0,?}, "16", addrmode6align64>;
639 def VLD1d32 : VLD1D<{1,0,0,?}, "32", addrmode6align64>;
640 def VLD1d64 : VLD1D<{1,1,0,?}, "64", addrmode6align64>;
642 def VLD1q8 : VLD1Q<{0,0,?,?}, "8", addrmode6align64or128>;
643 def VLD1q16 : VLD1Q<{0,1,?,?}, "16", addrmode6align64or128>;
644 def VLD1q32 : VLD1Q<{1,0,?,?}, "32", addrmode6align64or128>;
645 def VLD1q64 : VLD1Q<{1,1,?,?}, "64", addrmode6align64or128>;
647 // ...with address register writeback:
648 multiclass VLD1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
649 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
650 (ins AddrMode:$Rn), IIC_VLD1u,
651 "vld1", Dt, "$Vd, $Rn!",
652 "$Rn.addr = $wb", []> {
653 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
655 let DecoderMethod = "DecodeVLDST1Instruction";
657 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
658 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1u,
659 "vld1", Dt, "$Vd, $Rn, $Rm",
660 "$Rn.addr = $wb", []> {
662 let DecoderMethod = "DecodeVLDST1Instruction";
665 multiclass VLD1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
666 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
667 (ins AddrMode:$Rn), IIC_VLD1x2u,
668 "vld1", Dt, "$Vd, $Rn!",
669 "$Rn.addr = $wb", []> {
670 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
671 let Inst{5-4} = Rn{5-4};
672 let DecoderMethod = "DecodeVLDST1Instruction";
674 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListDPair:$Vd, GPR:$wb),
675 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
676 "vld1", Dt, "$Vd, $Rn, $Rm",
677 "$Rn.addr = $wb", []> {
678 let Inst{5-4} = Rn{5-4};
679 let DecoderMethod = "DecodeVLDST1Instruction";
683 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8", addrmode6align64>;
684 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16", addrmode6align64>;
685 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32", addrmode6align64>;
686 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64", addrmode6align64>;
687 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
688 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
689 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
690 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
692 // ...with 3 registers
693 class VLD1D3<bits<4> op7_4, string Dt, Operand AddrMode>
694 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
695 (ins AddrMode:$Rn), IIC_VLD1x3, "vld1", Dt,
696 "$Vd, $Rn", "", []> {
699 let DecoderMethod = "DecodeVLDST1Instruction";
701 multiclass VLD1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
702 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
703 (ins AddrMode:$Rn), IIC_VLD1x2u,
704 "vld1", Dt, "$Vd, $Rn!",
705 "$Rn.addr = $wb", []> {
706 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
708 let DecoderMethod = "DecodeVLDST1Instruction";
710 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
711 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
712 "vld1", Dt, "$Vd, $Rn, $Rm",
713 "$Rn.addr = $wb", []> {
715 let DecoderMethod = "DecodeVLDST1Instruction";
719 def VLD1d8T : VLD1D3<{0,0,0,?}, "8", addrmode6align64>;
720 def VLD1d16T : VLD1D3<{0,1,0,?}, "16", addrmode6align64>;
721 def VLD1d32T : VLD1D3<{1,0,0,?}, "32", addrmode6align64>;
722 def VLD1d64T : VLD1D3<{1,1,0,?}, "64", addrmode6align64>;
724 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8", addrmode6align64>;
725 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16", addrmode6align64>;
726 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32", addrmode6align64>;
727 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64", addrmode6align64>;
729 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
730 def VLD1d64TPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x3>;
731 def VLD1d64TPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x3>;
733 // ...with 4 registers
734 class VLD1D4<bits<4> op7_4, string Dt, Operand AddrMode>
735 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
736 (ins AddrMode:$Rn), IIC_VLD1x4, "vld1", Dt,
737 "$Vd, $Rn", "", []> {
739 let Inst{5-4} = Rn{5-4};
740 let DecoderMethod = "DecodeVLDST1Instruction";
742 multiclass VLD1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
743 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
744 (ins AddrMode:$Rn), IIC_VLD1x2u,
745 "vld1", Dt, "$Vd, $Rn!",
746 "$Rn.addr = $wb", []> {
747 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
748 let Inst{5-4} = Rn{5-4};
749 let DecoderMethod = "DecodeVLDST1Instruction";
751 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
752 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1x2u,
753 "vld1", Dt, "$Vd, $Rn, $Rm",
754 "$Rn.addr = $wb", []> {
755 let Inst{5-4} = Rn{5-4};
756 let DecoderMethod = "DecodeVLDST1Instruction";
760 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
761 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
762 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
763 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
765 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
766 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
767 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
768 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
770 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
771 def VLD1d64QPseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD1x4>;
772 def VLD1d64QPseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD1x4>;
774 // VLD2 : Vector Load (multiple 2-element structures)
775 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
776 InstrItinClass itin, Operand AddrMode>
777 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
778 (ins AddrMode:$Rn), itin,
779 "vld2", Dt, "$Vd, $Rn", "", []> {
781 let Inst{5-4} = Rn{5-4};
782 let DecoderMethod = "DecodeVLDST2Instruction";
785 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2,
786 addrmode6align64or128>;
787 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2,
788 addrmode6align64or128>;
789 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2,
790 addrmode6align64or128>;
792 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
793 addrmode6align64or128or256>;
794 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
795 addrmode6align64or128or256>;
796 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
797 addrmode6align64or128or256>;
799 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
800 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
801 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
803 // ...with address register writeback:
804 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
805 RegisterOperand VdTy, InstrItinClass itin, Operand AddrMode> {
806 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
807 (ins AddrMode:$Rn), itin,
808 "vld2", Dt, "$Vd, $Rn!",
809 "$Rn.addr = $wb", []> {
810 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
811 let Inst{5-4} = Rn{5-4};
812 let DecoderMethod = "DecodeVLDST2Instruction";
814 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
815 (ins AddrMode:$Rn, rGPR:$Rm), itin,
816 "vld2", Dt, "$Vd, $Rn, $Rm",
817 "$Rn.addr = $wb", []> {
818 let Inst{5-4} = Rn{5-4};
819 let DecoderMethod = "DecodeVLDST2Instruction";
823 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VLD2u,
824 addrmode6align64or128>;
825 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VLD2u,
826 addrmode6align64or128>;
827 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VLD2u,
828 addrmode6align64or128>;
830 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
831 addrmode6align64or128or256>;
832 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
833 addrmode6align64or128or256>;
834 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
835 addrmode6align64or128or256>;
837 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
838 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
839 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
840 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
841 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
842 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
844 // ...with double-spaced registers
845 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2,
846 addrmode6align64or128>;
847 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2,
848 addrmode6align64or128>;
849 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2,
850 addrmode6align64or128>;
851 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VLD2u,
852 addrmode6align64or128>;
853 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VLD2u,
854 addrmode6align64or128>;
855 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VLD2u,
856 addrmode6align64or128>;
858 // VLD3 : Vector Load (multiple 3-element structures)
859 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
860 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
861 (ins addrmode6:$Rn), IIC_VLD3,
862 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
865 let DecoderMethod = "DecodeVLDST3Instruction";
868 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
869 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
870 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
872 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
873 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
874 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
876 // ...with address register writeback:
877 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
878 : NLdSt<0, 0b10, op11_8, op7_4,
879 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
880 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
881 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
882 "$Rn.addr = $wb", []> {
884 let DecoderMethod = "DecodeVLDST3Instruction";
887 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
888 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
889 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
891 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
892 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
893 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
895 // ...with double-spaced registers:
896 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
897 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
898 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
899 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
900 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
901 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
903 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
904 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
905 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
907 // ...alternate versions to be allocated odd register numbers:
908 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
909 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
910 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
912 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
913 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
914 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
916 // VLD4 : Vector Load (multiple 4-element structures)
917 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
918 : NLdSt<0, 0b10, op11_8, op7_4,
919 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
920 (ins addrmode6:$Rn), IIC_VLD4,
921 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
923 let Inst{5-4} = Rn{5-4};
924 let DecoderMethod = "DecodeVLDST4Instruction";
927 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
928 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
929 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
931 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
932 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
933 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
935 // ...with address register writeback:
936 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
937 : NLdSt<0, 0b10, op11_8, op7_4,
938 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
939 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
940 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
941 "$Rn.addr = $wb", []> {
942 let Inst{5-4} = Rn{5-4};
943 let DecoderMethod = "DecodeVLDST4Instruction";
946 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
947 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
948 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
950 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
951 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
952 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
954 // ...with double-spaced registers:
955 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
956 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
957 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
958 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
959 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
960 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
962 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
963 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
964 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
966 // ...alternate versions to be allocated odd register numbers:
967 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
968 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
969 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
971 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
972 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
973 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
975 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
977 // Classes for VLD*LN pseudo-instructions with multi-register operands.
978 // These are expanded to real instructions after register allocation.
979 class VLDQLNPseudo<InstrItinClass itin>
980 : PseudoNLdSt<(outs QPR:$dst),
981 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
982 itin, "$src = $dst">;
983 class VLDQLNWBPseudo<InstrItinClass itin>
984 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
985 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
986 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
987 class VLDQQLNPseudo<InstrItinClass itin>
988 : PseudoNLdSt<(outs QQPR:$dst),
989 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
990 itin, "$src = $dst">;
991 class VLDQQLNWBPseudo<InstrItinClass itin>
992 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
993 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
994 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
995 class VLDQQQQLNPseudo<InstrItinClass itin>
996 : PseudoNLdSt<(outs QQQQPR:$dst),
997 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
998 itin, "$src = $dst">;
999 class VLDQQQQLNWBPseudo<InstrItinClass itin>
1000 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
1001 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1002 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
1004 // VLD1LN : Vector Load (single element to one lane)
1005 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1007 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1008 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
1009 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1011 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1012 (i32 (LoadOp addrmode6:$Rn)),
1015 let DecoderMethod = "DecodeVLD1LN";
1017 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1019 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
1020 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
1021 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
1023 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
1024 (i32 (LoadOp addrmode6oneL32:$Rn)),
1027 let DecoderMethod = "DecodeVLD1LN";
1029 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
1030 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
1031 (i32 (LoadOp addrmode6:$addr)),
1035 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
1036 let Inst{7-5} = lane{2-0};
1038 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
1039 let Inst{7-6} = lane{1-0};
1040 let Inst{5-4} = Rn{5-4};
1042 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
1043 let Inst{7} = lane{0};
1044 let Inst{5-4} = Rn{5-4};
1047 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
1048 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
1049 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
1051 def : Pat<(vector_insert (v2f32 DPR:$src),
1052 (f32 (load addrmode6:$addr)), imm:$lane),
1053 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1054 def : Pat<(vector_insert (v4f32 QPR:$src),
1055 (f32 (load addrmode6:$addr)), imm:$lane),
1056 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1058 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1060 // ...with address register writeback:
1061 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1062 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
1063 (ins addrmode6:$Rn, am6offset:$Rm,
1064 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
1065 "\\{$Vd[$lane]\\}, $Rn$Rm",
1066 "$src = $Vd, $Rn.addr = $wb", []> {
1067 let DecoderMethod = "DecodeVLD1LN";
1070 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
1071 let Inst{7-5} = lane{2-0};
1073 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
1074 let Inst{7-6} = lane{1-0};
1075 let Inst{4} = Rn{4};
1077 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
1078 let Inst{7} = lane{0};
1079 let Inst{5} = Rn{4};
1080 let Inst{4} = Rn{4};
1083 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1084 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1085 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
1087 // VLD2LN : Vector Load (single 2-element structure to one lane)
1088 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1089 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
1090 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
1091 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
1092 "$src1 = $Vd, $src2 = $dst2", []> {
1094 let Inst{4} = Rn{4};
1095 let DecoderMethod = "DecodeVLD2LN";
1098 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
1099 let Inst{7-5} = lane{2-0};
1101 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
1102 let Inst{7-6} = lane{1-0};
1104 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
1105 let Inst{7} = lane{0};
1108 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1109 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1110 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
1112 // ...with double-spaced registers:
1113 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
1114 let Inst{7-6} = lane{1-0};
1116 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
1117 let Inst{7} = lane{0};
1120 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1121 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
1123 // ...with address register writeback:
1124 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1125 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1126 (ins addrmode6:$Rn, am6offset:$Rm,
1127 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
1128 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
1129 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
1130 let Inst{4} = Rn{4};
1131 let DecoderMethod = "DecodeVLD2LN";
1134 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
1135 let Inst{7-5} = lane{2-0};
1137 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
1138 let Inst{7-6} = lane{1-0};
1140 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
1141 let Inst{7} = lane{0};
1144 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1145 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1146 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
1148 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
1149 let Inst{7-6} = lane{1-0};
1151 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
1152 let Inst{7} = lane{0};
1155 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1156 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
1158 // VLD3LN : Vector Load (single 3-element structure to one lane)
1159 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1160 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1161 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
1162 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
1163 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
1164 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
1166 let DecoderMethod = "DecodeVLD3LN";
1169 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
1170 let Inst{7-5} = lane{2-0};
1172 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
1173 let Inst{7-6} = lane{1-0};
1175 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
1176 let Inst{7} = lane{0};
1179 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1180 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1181 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
1183 // ...with double-spaced registers:
1184 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
1185 let Inst{7-6} = lane{1-0};
1187 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
1188 let Inst{7} = lane{0};
1191 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1192 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
1194 // ...with address register writeback:
1195 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1196 : NLdStLn<1, 0b10, op11_8, op7_4,
1197 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1198 (ins addrmode6:$Rn, am6offset:$Rm,
1199 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1200 IIC_VLD3lnu, "vld3", Dt,
1201 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
1202 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
1204 let DecoderMethod = "DecodeVLD3LN";
1207 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
1208 let Inst{7-5} = lane{2-0};
1210 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
1211 let Inst{7-6} = lane{1-0};
1213 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
1214 let Inst{7} = lane{0};
1217 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1218 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1219 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1221 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1222 let Inst{7-6} = lane{1-0};
1224 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1225 let Inst{7} = lane{0};
1228 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1229 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1231 // VLD4LN : Vector Load (single 4-element structure to one lane)
1232 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1233 : NLdStLn<1, 0b10, op11_8, op7_4,
1234 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1235 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1236 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1237 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1238 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1240 let Inst{4} = Rn{4};
1241 let DecoderMethod = "DecodeVLD4LN";
1244 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1245 let Inst{7-5} = lane{2-0};
1247 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1248 let Inst{7-6} = lane{1-0};
1250 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1251 let Inst{7} = lane{0};
1252 let Inst{5} = Rn{5};
1255 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1256 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1257 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1259 // ...with double-spaced registers:
1260 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1261 let Inst{7-6} = lane{1-0};
1263 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1264 let Inst{7} = lane{0};
1265 let Inst{5} = Rn{5};
1268 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1269 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1271 // ...with address register writeback:
1272 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1273 : NLdStLn<1, 0b10, op11_8, op7_4,
1274 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1275 (ins addrmode6:$Rn, am6offset:$Rm,
1276 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1277 IIC_VLD4lnu, "vld4", Dt,
1278 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1279 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1281 let Inst{4} = Rn{4};
1282 let DecoderMethod = "DecodeVLD4LN" ;
1285 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1286 let Inst{7-5} = lane{2-0};
1288 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1289 let Inst{7-6} = lane{1-0};
1291 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1292 let Inst{7} = lane{0};
1293 let Inst{5} = Rn{5};
1296 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1297 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1298 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1300 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1301 let Inst{7-6} = lane{1-0};
1303 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1304 let Inst{7} = lane{0};
1305 let Inst{5} = Rn{5};
1308 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1309 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1311 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1313 // VLD1DUP : Vector Load (single element to all lanes)
1314 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1316 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1318 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1319 [(set VecListOneDAllLanes:$Vd,
1320 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1322 let Inst{4} = Rn{4};
1323 let DecoderMethod = "DecodeVLD1DupInstruction";
1325 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8,
1326 addrmode6dupalignNone>;
1327 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16,
1328 addrmode6dupalign16>;
1329 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load,
1330 addrmode6dupalign32>;
1332 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1333 (VLD1DUPd32 addrmode6:$addr)>;
1335 class VLD1QDUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp,
1337 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListDPairAllLanes:$Vd),
1338 (ins AddrMode:$Rn), IIC_VLD1dup,
1339 "vld1", Dt, "$Vd, $Rn", "",
1340 [(set VecListDPairAllLanes:$Vd,
1341 (Ty (NEONvdup (i32 (LoadOp AddrMode:$Rn)))))]> {
1343 let Inst{4} = Rn{4};
1344 let DecoderMethod = "DecodeVLD1DupInstruction";
1347 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8", v16i8, extloadi8,
1348 addrmode6dupalignNone>;
1349 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16", v8i16, extloadi16,
1350 addrmode6dupalign16>;
1351 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32", v4i32, load,
1352 addrmode6dupalign32>;
1354 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1355 (VLD1DUPq32 addrmode6:$addr)>;
1357 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1358 // ...with address register writeback:
1359 multiclass VLD1DUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1360 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1361 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1362 (ins AddrMode:$Rn), IIC_VLD1dupu,
1363 "vld1", Dt, "$Vd, $Rn!",
1364 "$Rn.addr = $wb", []> {
1365 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1366 let Inst{4} = Rn{4};
1367 let DecoderMethod = "DecodeVLD1DupInstruction";
1369 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1370 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1371 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1372 "vld1", Dt, "$Vd, $Rn, $Rm",
1373 "$Rn.addr = $wb", []> {
1374 let Inst{4} = Rn{4};
1375 let DecoderMethod = "DecodeVLD1DupInstruction";
1378 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1379 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1380 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1381 (ins AddrMode:$Rn), IIC_VLD1dupu,
1382 "vld1", Dt, "$Vd, $Rn!",
1383 "$Rn.addr = $wb", []> {
1384 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1385 let Inst{4} = Rn{4};
1386 let DecoderMethod = "DecodeVLD1DupInstruction";
1388 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1389 (outs VecListDPairAllLanes:$Vd, GPR:$wb),
1390 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1391 "vld1", Dt, "$Vd, $Rn, $Rm",
1392 "$Rn.addr = $wb", []> {
1393 let Inst{4} = Rn{4};
1394 let DecoderMethod = "DecodeVLD1DupInstruction";
1398 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8", addrmode6dupalignNone>;
1399 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16", addrmode6dupalign16>;
1400 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32", addrmode6dupalign32>;
1402 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8", addrmode6dupalignNone>;
1403 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16", addrmode6dupalign16>;
1404 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32", addrmode6dupalign32>;
1406 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1407 class VLD2DUP<bits<4> op7_4, string Dt, RegisterOperand VdTy, Operand AddrMode>
1408 : NLdSt<1, 0b10, 0b1101, op7_4, (outs VdTy:$Vd),
1409 (ins AddrMode:$Rn), IIC_VLD2dup,
1410 "vld2", Dt, "$Vd, $Rn", "", []> {
1412 let Inst{4} = Rn{4};
1413 let DecoderMethod = "DecodeVLD2DupInstruction";
1416 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8", VecListDPairAllLanes,
1417 addrmode6dupalign16>;
1418 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16", VecListDPairAllLanes,
1419 addrmode6dupalign32>;
1420 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32", VecListDPairAllLanes,
1421 addrmode6dupalign64>;
1423 // HACK this one, VLD2DUPd8x2 must be changed at the same time with VLD2b8 or
1424 // "vld2.8 {d0[], d2[]}, [r4:32]" will become "vld2.8 {d0, d2}, [r4:32]".
1425 // ...with double-spaced registers
1426 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8", VecListDPairSpacedAllLanes,
1427 addrmode6dupalign16>;
1428 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1429 addrmode6dupalign32>;
1430 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1431 addrmode6dupalign64>;
1433 // ...with address register writeback:
1434 multiclass VLD2DUPWB<bits<4> op7_4, string Dt, RegisterOperand VdTy,
1436 def _fixed : NLdSt<1, 0b10, 0b1101, op7_4,
1437 (outs VdTy:$Vd, GPR:$wb),
1438 (ins AddrMode:$Rn), IIC_VLD2dupu,
1439 "vld2", Dt, "$Vd, $Rn!",
1440 "$Rn.addr = $wb", []> {
1441 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1442 let Inst{4} = Rn{4};
1443 let DecoderMethod = "DecodeVLD2DupInstruction";
1445 def _register : NLdSt<1, 0b10, 0b1101, op7_4,
1446 (outs VdTy:$Vd, GPR:$wb),
1447 (ins AddrMode:$Rn, rGPR:$Rm), IIC_VLD2dupu,
1448 "vld2", Dt, "$Vd, $Rn, $Rm",
1449 "$Rn.addr = $wb", []> {
1450 let Inst{4} = Rn{4};
1451 let DecoderMethod = "DecodeVLD2DupInstruction";
1455 defm VLD2DUPd8wb : VLD2DUPWB<{0,0,0,0}, "8", VecListDPairAllLanes,
1456 addrmode6dupalign16>;
1457 defm VLD2DUPd16wb : VLD2DUPWB<{0,1,0,?}, "16", VecListDPairAllLanes,
1458 addrmode6dupalign32>;
1459 defm VLD2DUPd32wb : VLD2DUPWB<{1,0,0,?}, "32", VecListDPairAllLanes,
1460 addrmode6dupalign64>;
1462 defm VLD2DUPd8x2wb : VLD2DUPWB<{0,0,1,0}, "8", VecListDPairSpacedAllLanes,
1463 addrmode6dupalign16>;
1464 defm VLD2DUPd16x2wb : VLD2DUPWB<{0,1,1,?}, "16", VecListDPairSpacedAllLanes,
1465 addrmode6dupalign32>;
1466 defm VLD2DUPd32x2wb : VLD2DUPWB<{1,0,1,?}, "32", VecListDPairSpacedAllLanes,
1467 addrmode6dupalign64>;
1469 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1470 class VLD3DUP<bits<4> op7_4, string Dt>
1471 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1472 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1473 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1476 let DecoderMethod = "DecodeVLD3DupInstruction";
1479 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1480 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1481 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1483 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1484 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1485 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1487 // ...with double-spaced registers (not used for codegen):
1488 def VLD3DUPq8 : VLD3DUP<{0,0,1,?}, "8">;
1489 def VLD3DUPq16 : VLD3DUP<{0,1,1,?}, "16">;
1490 def VLD3DUPq32 : VLD3DUP<{1,0,1,?}, "32">;
1492 // ...with address register writeback:
1493 class VLD3DUPWB<bits<4> op7_4, string Dt, Operand AddrMode>
1494 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1495 (ins AddrMode:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1496 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1497 "$Rn.addr = $wb", []> {
1499 let DecoderMethod = "DecodeVLD3DupInstruction";
1502 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8", addrmode6dupalign64>;
1503 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16", addrmode6dupalign64>;
1504 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32", addrmode6dupalign64>;
1506 def VLD3DUPq8_UPD : VLD3DUPWB<{0,0,1,0}, "8", addrmode6dupalign64>;
1507 def VLD3DUPq16_UPD : VLD3DUPWB<{0,1,1,?}, "16", addrmode6dupalign64>;
1508 def VLD3DUPq32_UPD : VLD3DUPWB<{1,0,1,?}, "32", addrmode6dupalign64>;
1510 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1511 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1512 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1514 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1515 class VLD4DUP<bits<4> op7_4, string Dt>
1516 : NLdSt<1, 0b10, 0b1111, op7_4,
1517 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1518 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1519 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1521 let Inst{4} = Rn{4};
1522 let DecoderMethod = "DecodeVLD4DupInstruction";
1525 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1526 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1527 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1529 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1530 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1531 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1533 // ...with double-spaced registers (not used for codegen):
1534 def VLD4DUPq8 : VLD4DUP<{0,0,1,?}, "8">;
1535 def VLD4DUPq16 : VLD4DUP<{0,1,1,?}, "16">;
1536 def VLD4DUPq32 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1538 // ...with address register writeback:
1539 class VLD4DUPWB<bits<4> op7_4, string Dt>
1540 : NLdSt<1, 0b10, 0b1111, op7_4,
1541 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1542 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1543 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1544 "$Rn.addr = $wb", []> {
1545 let Inst{4} = Rn{4};
1546 let DecoderMethod = "DecodeVLD4DupInstruction";
1549 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1550 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1551 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1553 def VLD4DUPq8_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1554 def VLD4DUPq16_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1555 def VLD4DUPq32_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1557 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1558 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1559 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1561 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1563 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1565 // Classes for VST* pseudo-instructions with multi-register operands.
1566 // These are expanded to real instructions after register allocation.
1567 class VSTQPseudo<InstrItinClass itin>
1568 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1569 class VSTQWBPseudo<InstrItinClass itin>
1570 : PseudoNLdSt<(outs GPR:$wb),
1571 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1572 "$addr.addr = $wb">;
1573 class VSTQWBfixedPseudo<InstrItinClass itin>
1574 : PseudoNLdSt<(outs GPR:$wb),
1575 (ins addrmode6:$addr, QPR:$src), itin,
1576 "$addr.addr = $wb">;
1577 class VSTQWBregisterPseudo<InstrItinClass itin>
1578 : PseudoNLdSt<(outs GPR:$wb),
1579 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1580 "$addr.addr = $wb">;
1581 class VSTQQPseudo<InstrItinClass itin>
1582 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1583 class VSTQQWBPseudo<InstrItinClass itin>
1584 : PseudoNLdSt<(outs GPR:$wb),
1585 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1586 "$addr.addr = $wb">;
1587 class VSTQQWBfixedPseudo<InstrItinClass itin>
1588 : PseudoNLdSt<(outs GPR:$wb),
1589 (ins addrmode6:$addr, QQPR:$src), itin,
1590 "$addr.addr = $wb">;
1591 class VSTQQWBregisterPseudo<InstrItinClass itin>
1592 : PseudoNLdSt<(outs GPR:$wb),
1593 (ins addrmode6:$addr, rGPR:$offset, QQPR:$src), itin,
1594 "$addr.addr = $wb">;
1596 class VSTQQQQPseudo<InstrItinClass itin>
1597 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1598 class VSTQQQQWBPseudo<InstrItinClass itin>
1599 : PseudoNLdSt<(outs GPR:$wb),
1600 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1601 "$addr.addr = $wb">;
1603 // VST1 : Vector Store (multiple single elements)
1604 class VST1D<bits<4> op7_4, string Dt, Operand AddrMode>
1605 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins AddrMode:$Rn, VecListOneD:$Vd),
1606 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1608 let Inst{4} = Rn{4};
1609 let DecoderMethod = "DecodeVLDST1Instruction";
1611 class VST1Q<bits<4> op7_4, string Dt, Operand AddrMode>
1612 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins AddrMode:$Rn, VecListDPair:$Vd),
1613 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1615 let Inst{5-4} = Rn{5-4};
1616 let DecoderMethod = "DecodeVLDST1Instruction";
1619 def VST1d8 : VST1D<{0,0,0,?}, "8", addrmode6align64>;
1620 def VST1d16 : VST1D<{0,1,0,?}, "16", addrmode6align64>;
1621 def VST1d32 : VST1D<{1,0,0,?}, "32", addrmode6align64>;
1622 def VST1d64 : VST1D<{1,1,0,?}, "64", addrmode6align64>;
1624 def VST1q8 : VST1Q<{0,0,?,?}, "8", addrmode6align64or128>;
1625 def VST1q16 : VST1Q<{0,1,?,?}, "16", addrmode6align64or128>;
1626 def VST1q32 : VST1Q<{1,0,?,?}, "32", addrmode6align64or128>;
1627 def VST1q64 : VST1Q<{1,1,?,?}, "64", addrmode6align64or128>;
1629 // ...with address register writeback:
1630 multiclass VST1DWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1631 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1632 (ins AddrMode:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1633 "vst1", Dt, "$Vd, $Rn!",
1634 "$Rn.addr = $wb", []> {
1635 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1636 let Inst{4} = Rn{4};
1637 let DecoderMethod = "DecodeVLDST1Instruction";
1639 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1640 (ins AddrMode:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1642 "vst1", Dt, "$Vd, $Rn, $Rm",
1643 "$Rn.addr = $wb", []> {
1644 let Inst{4} = Rn{4};
1645 let DecoderMethod = "DecodeVLDST1Instruction";
1648 multiclass VST1QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1649 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1650 (ins AddrMode:$Rn, VecListDPair:$Vd), IIC_VLD1x2u,
1651 "vst1", Dt, "$Vd, $Rn!",
1652 "$Rn.addr = $wb", []> {
1653 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1654 let Inst{5-4} = Rn{5-4};
1655 let DecoderMethod = "DecodeVLDST1Instruction";
1657 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1658 (ins AddrMode:$Rn, rGPR:$Rm, VecListDPair:$Vd),
1660 "vst1", Dt, "$Vd, $Rn, $Rm",
1661 "$Rn.addr = $wb", []> {
1662 let Inst{5-4} = Rn{5-4};
1663 let DecoderMethod = "DecodeVLDST1Instruction";
1667 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8", addrmode6align64>;
1668 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16", addrmode6align64>;
1669 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32", addrmode6align64>;
1670 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64", addrmode6align64>;
1672 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8", addrmode6align64or128>;
1673 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16", addrmode6align64or128>;
1674 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32", addrmode6align64or128>;
1675 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64", addrmode6align64or128>;
1677 // ...with 3 registers
1678 class VST1D3<bits<4> op7_4, string Dt, Operand AddrMode>
1679 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1680 (ins AddrMode:$Rn, VecListThreeD:$Vd),
1681 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1683 let Inst{4} = Rn{4};
1684 let DecoderMethod = "DecodeVLDST1Instruction";
1686 multiclass VST1D3WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1687 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1688 (ins AddrMode:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1689 "vst1", Dt, "$Vd, $Rn!",
1690 "$Rn.addr = $wb", []> {
1691 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1692 let Inst{5-4} = Rn{5-4};
1693 let DecoderMethod = "DecodeVLDST1Instruction";
1695 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1696 (ins AddrMode:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1698 "vst1", Dt, "$Vd, $Rn, $Rm",
1699 "$Rn.addr = $wb", []> {
1700 let Inst{5-4} = Rn{5-4};
1701 let DecoderMethod = "DecodeVLDST1Instruction";
1705 def VST1d8T : VST1D3<{0,0,0,?}, "8", addrmode6align64>;
1706 def VST1d16T : VST1D3<{0,1,0,?}, "16", addrmode6align64>;
1707 def VST1d32T : VST1D3<{1,0,0,?}, "32", addrmode6align64>;
1708 def VST1d64T : VST1D3<{1,1,0,?}, "64", addrmode6align64>;
1710 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8", addrmode6align64>;
1711 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16", addrmode6align64>;
1712 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32", addrmode6align64>;
1713 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64", addrmode6align64>;
1715 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1716 def VST1d64TPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x3u>;
1717 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1719 // ...with 4 registers
1720 class VST1D4<bits<4> op7_4, string Dt, Operand AddrMode>
1721 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1722 (ins AddrMode:$Rn, VecListFourD:$Vd),
1723 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1726 let Inst{5-4} = Rn{5-4};
1727 let DecoderMethod = "DecodeVLDST1Instruction";
1729 multiclass VST1D4WB<bits<4> op7_4, string Dt, Operand AddrMode> {
1730 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1731 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1732 "vst1", Dt, "$Vd, $Rn!",
1733 "$Rn.addr = $wb", []> {
1734 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1735 let Inst{5-4} = Rn{5-4};
1736 let DecoderMethod = "DecodeVLDST1Instruction";
1738 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1739 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1741 "vst1", Dt, "$Vd, $Rn, $Rm",
1742 "$Rn.addr = $wb", []> {
1743 let Inst{5-4} = Rn{5-4};
1744 let DecoderMethod = "DecodeVLDST1Instruction";
1748 def VST1d8Q : VST1D4<{0,0,?,?}, "8", addrmode6align64or128or256>;
1749 def VST1d16Q : VST1D4<{0,1,?,?}, "16", addrmode6align64or128or256>;
1750 def VST1d32Q : VST1D4<{1,0,?,?}, "32", addrmode6align64or128or256>;
1751 def VST1d64Q : VST1D4<{1,1,?,?}, "64", addrmode6align64or128or256>;
1753 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1754 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1755 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1756 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64", addrmode6align64or128or256>;
1758 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1759 def VST1d64QPseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST1x4u>;
1760 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1762 // VST2 : Vector Store (multiple 2-element structures)
1763 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1764 InstrItinClass itin, Operand AddrMode>
1765 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins AddrMode:$Rn, VdTy:$Vd),
1766 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1768 let Inst{5-4} = Rn{5-4};
1769 let DecoderMethod = "DecodeVLDST2Instruction";
1772 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListDPair, IIC_VST2,
1773 addrmode6align64or128>;
1774 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListDPair, IIC_VST2,
1775 addrmode6align64or128>;
1776 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListDPair, IIC_VST2,
1777 addrmode6align64or128>;
1779 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1780 addrmode6align64or128or256>;
1781 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
1782 addrmode6align64or128or256>;
1783 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2,
1784 addrmode6align64or128or256>;
1786 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1787 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1788 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1790 // ...with address register writeback:
1791 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1792 RegisterOperand VdTy, Operand AddrMode> {
1793 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1794 (ins AddrMode:$Rn, VdTy:$Vd), IIC_VLD1u,
1795 "vst2", Dt, "$Vd, $Rn!",
1796 "$Rn.addr = $wb", []> {
1797 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1798 let Inst{5-4} = Rn{5-4};
1799 let DecoderMethod = "DecodeVLDST2Instruction";
1801 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1802 (ins AddrMode:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1803 "vst2", Dt, "$Vd, $Rn, $Rm",
1804 "$Rn.addr = $wb", []> {
1805 let Inst{5-4} = Rn{5-4};
1806 let DecoderMethod = "DecodeVLDST2Instruction";
1809 multiclass VST2QWB<bits<4> op7_4, string Dt, Operand AddrMode> {
1810 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1811 (ins AddrMode:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1812 "vst2", Dt, "$Vd, $Rn!",
1813 "$Rn.addr = $wb", []> {
1814 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1815 let Inst{5-4} = Rn{5-4};
1816 let DecoderMethod = "DecodeVLDST2Instruction";
1818 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1819 (ins AddrMode:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1821 "vst2", Dt, "$Vd, $Rn, $Rm",
1822 "$Rn.addr = $wb", []> {
1823 let Inst{5-4} = Rn{5-4};
1824 let DecoderMethod = "DecodeVLDST2Instruction";
1828 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListDPair,
1829 addrmode6align64or128>;
1830 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListDPair,
1831 addrmode6align64or128>;
1832 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListDPair,
1833 addrmode6align64or128>;
1835 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8", addrmode6align64or128or256>;
1836 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16", addrmode6align64or128or256>;
1837 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32", addrmode6align64or128or256>;
1839 def VST2q8PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1840 def VST2q16PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1841 def VST2q32PseudoWB_fixed : VSTQQWBfixedPseudo<IIC_VST2x2u>;
1842 def VST2q8PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1843 def VST2q16PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1844 def VST2q32PseudoWB_register : VSTQQWBregisterPseudo<IIC_VST2x2u>;
1846 // ...with double-spaced registers
1847 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListDPairSpaced, IIC_VST2,
1848 addrmode6align64or128>;
1849 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListDPairSpaced, IIC_VST2,
1850 addrmode6align64or128>;
1851 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListDPairSpaced, IIC_VST2,
1852 addrmode6align64or128>;
1853 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListDPairSpaced,
1854 addrmode6align64or128>;
1855 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListDPairSpaced,
1856 addrmode6align64or128>;
1857 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListDPairSpaced,
1858 addrmode6align64or128>;
1860 // VST3 : Vector Store (multiple 3-element structures)
1861 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1862 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1863 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1864 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1866 let Inst{4} = Rn{4};
1867 let DecoderMethod = "DecodeVLDST3Instruction";
1870 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1871 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1872 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1874 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1875 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1876 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1878 // ...with address register writeback:
1879 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1880 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1881 (ins addrmode6:$Rn, am6offset:$Rm,
1882 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1883 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1884 "$Rn.addr = $wb", []> {
1885 let Inst{4} = Rn{4};
1886 let DecoderMethod = "DecodeVLDST3Instruction";
1889 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1890 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1891 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1893 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1894 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1895 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1897 // ...with double-spaced registers:
1898 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1899 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1900 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1901 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1902 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1903 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1905 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1906 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1907 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1909 // ...alternate versions to be allocated odd register numbers:
1910 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1911 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1912 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1914 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1915 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1916 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1918 // VST4 : Vector Store (multiple 4-element structures)
1919 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1920 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1921 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1922 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1925 let Inst{5-4} = Rn{5-4};
1926 let DecoderMethod = "DecodeVLDST4Instruction";
1929 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1930 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1931 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1933 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1934 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1935 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1937 // ...with address register writeback:
1938 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1939 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1940 (ins addrmode6:$Rn, am6offset:$Rm,
1941 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1942 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1943 "$Rn.addr = $wb", []> {
1944 let Inst{5-4} = Rn{5-4};
1945 let DecoderMethod = "DecodeVLDST4Instruction";
1948 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1949 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1950 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1952 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1953 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1954 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1956 // ...with double-spaced registers:
1957 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1958 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1959 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1960 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1961 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1962 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1964 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1965 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1966 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1968 // ...alternate versions to be allocated odd register numbers:
1969 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1970 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1971 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1973 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1974 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1975 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1977 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1979 // Classes for VST*LN pseudo-instructions with multi-register operands.
1980 // These are expanded to real instructions after register allocation.
1981 class VSTQLNPseudo<InstrItinClass itin>
1982 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1984 class VSTQLNWBPseudo<InstrItinClass itin>
1985 : PseudoNLdSt<(outs GPR:$wb),
1986 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1987 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1988 class VSTQQLNPseudo<InstrItinClass itin>
1989 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1991 class VSTQQLNWBPseudo<InstrItinClass itin>
1992 : PseudoNLdSt<(outs GPR:$wb),
1993 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1994 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1995 class VSTQQQQLNPseudo<InstrItinClass itin>
1996 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1998 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1999 : PseudoNLdSt<(outs GPR:$wb),
2000 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
2001 nohash_imm:$lane), itin, "$addr.addr = $wb">;
2003 // VST1LN : Vector Store (single element from one lane)
2004 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2005 PatFrag StoreOp, SDNode ExtractOp, Operand AddrMode>
2006 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2007 (ins AddrMode:$Rn, DPR:$Vd, nohash_imm:$lane),
2008 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
2009 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), AddrMode:$Rn)]> {
2011 let DecoderMethod = "DecodeVST1LN";
2013 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2014 : VSTQLNPseudo<IIC_VST1ln> {
2015 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2019 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
2020 NEONvgetlaneu, addrmode6> {
2021 let Inst{7-5} = lane{2-0};
2023 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
2024 NEONvgetlaneu, addrmode6> {
2025 let Inst{7-6} = lane{1-0};
2026 let Inst{4} = Rn{4};
2029 def VST1LNd32 : VST1LN<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt,
2031 let Inst{7} = lane{0};
2032 let Inst{5-4} = Rn{5-4};
2035 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
2036 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
2037 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
2039 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
2040 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
2041 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
2042 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
2044 // ...with address register writeback:
2045 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
2046 PatFrag StoreOp, SDNode ExtractOp, Operand AdrMode>
2047 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2048 (ins AdrMode:$Rn, am6offset:$Rm,
2049 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
2050 "\\{$Vd[$lane]\\}, $Rn$Rm",
2052 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
2053 AdrMode:$Rn, am6offset:$Rm))]> {
2054 let DecoderMethod = "DecodeVST1LN";
2056 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
2057 : VSTQLNWBPseudo<IIC_VST1lnu> {
2058 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
2059 addrmode6:$addr, am6offset:$offset))];
2062 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
2063 NEONvgetlaneu, addrmode6> {
2064 let Inst{7-5} = lane{2-0};
2066 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
2067 NEONvgetlaneu, addrmode6> {
2068 let Inst{7-6} = lane{1-0};
2069 let Inst{4} = Rn{4};
2071 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
2072 extractelt, addrmode6oneL32> {
2073 let Inst{7} = lane{0};
2074 let Inst{5-4} = Rn{5-4};
2077 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
2078 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
2079 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
2081 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
2083 // VST2LN : Vector Store (single 2-element structure from one lane)
2084 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2085 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2086 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
2087 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
2090 let Inst{4} = Rn{4};
2091 let DecoderMethod = "DecodeVST2LN";
2094 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
2095 let Inst{7-5} = lane{2-0};
2097 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
2098 let Inst{7-6} = lane{1-0};
2100 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
2101 let Inst{7} = lane{0};
2104 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2105 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2106 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
2108 // ...with double-spaced registers:
2109 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
2110 let Inst{7-6} = lane{1-0};
2111 let Inst{4} = Rn{4};
2113 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
2114 let Inst{7} = lane{0};
2115 let Inst{4} = Rn{4};
2118 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2119 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
2121 // ...with address register writeback:
2122 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2123 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2124 (ins addrmode6:$Rn, am6offset:$Rm,
2125 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
2126 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
2127 "$Rn.addr = $wb", []> {
2128 let Inst{4} = Rn{4};
2129 let DecoderMethod = "DecodeVST2LN";
2132 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
2133 let Inst{7-5} = lane{2-0};
2135 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
2136 let Inst{7-6} = lane{1-0};
2138 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
2139 let Inst{7} = lane{0};
2142 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2143 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2144 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
2146 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
2147 let Inst{7-6} = lane{1-0};
2149 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
2150 let Inst{7} = lane{0};
2153 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2154 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
2156 // VST3LN : Vector Store (single 3-element structure from one lane)
2157 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2158 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2159 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
2160 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
2161 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
2163 let DecoderMethod = "DecodeVST3LN";
2166 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
2167 let Inst{7-5} = lane{2-0};
2169 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
2170 let Inst{7-6} = lane{1-0};
2172 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
2173 let Inst{7} = lane{0};
2176 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2177 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2178 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
2180 // ...with double-spaced registers:
2181 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
2182 let Inst{7-6} = lane{1-0};
2184 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
2185 let Inst{7} = lane{0};
2188 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2189 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
2191 // ...with address register writeback:
2192 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2193 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2194 (ins addrmode6:$Rn, am6offset:$Rm,
2195 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
2196 IIC_VST3lnu, "vst3", Dt,
2197 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
2198 "$Rn.addr = $wb", []> {
2199 let DecoderMethod = "DecodeVST3LN";
2202 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
2203 let Inst{7-5} = lane{2-0};
2205 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2206 let Inst{7-6} = lane{1-0};
2208 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2209 let Inst{7} = lane{0};
2212 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2213 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2214 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2216 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2217 let Inst{7-6} = lane{1-0};
2219 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2220 let Inst{7} = lane{0};
2223 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2224 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2226 // VST4LN : Vector Store (single 4-element structure from one lane)
2227 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2228 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2229 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2230 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2231 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2234 let Inst{4} = Rn{4};
2235 let DecoderMethod = "DecodeVST4LN";
2238 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2239 let Inst{7-5} = lane{2-0};
2241 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2242 let Inst{7-6} = lane{1-0};
2244 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2245 let Inst{7} = lane{0};
2246 let Inst{5} = Rn{5};
2249 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2250 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2251 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2253 // ...with double-spaced registers:
2254 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2255 let Inst{7-6} = lane{1-0};
2257 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2258 let Inst{7} = lane{0};
2259 let Inst{5} = Rn{5};
2262 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2263 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2265 // ...with address register writeback:
2266 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2267 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2268 (ins addrmode6:$Rn, am6offset:$Rm,
2269 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2270 IIC_VST4lnu, "vst4", Dt,
2271 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2272 "$Rn.addr = $wb", []> {
2273 let Inst{4} = Rn{4};
2274 let DecoderMethod = "DecodeVST4LN";
2277 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2278 let Inst{7-5} = lane{2-0};
2280 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2281 let Inst{7-6} = lane{1-0};
2283 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2284 let Inst{7} = lane{0};
2285 let Inst{5} = Rn{5};
2288 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2289 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2290 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2292 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2293 let Inst{7-6} = lane{1-0};
2295 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2296 let Inst{7} = lane{0};
2297 let Inst{5} = Rn{5};
2300 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2301 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2303 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2305 // Use vld1/vst1 for unaligned f64 load / store
2306 def : Pat<(f64 (hword_alignedload addrmode6:$addr)),
2307 (VLD1d16 addrmode6:$addr)>, Requires<[IsLE]>;
2308 def : Pat<(hword_alignedstore (f64 DPR:$value), addrmode6:$addr),
2309 (VST1d16 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2310 def : Pat<(f64 (byte_alignedload addrmode6:$addr)),
2311 (VLD1d8 addrmode6:$addr)>, Requires<[IsLE]>;
2312 def : Pat<(byte_alignedstore (f64 DPR:$value), addrmode6:$addr),
2313 (VST1d8 addrmode6:$addr, DPR:$value)>, Requires<[IsLE]>;
2314 def : Pat<(f64 (non_word_alignedload addrmode6:$addr)),
2315 (VLD1d64 addrmode6:$addr)>, Requires<[IsBE]>;
2316 def : Pat<(non_word_alignedstore (f64 DPR:$value), addrmode6:$addr),
2317 (VST1d64 addrmode6:$addr, DPR:$value)>, Requires<[IsBE]>;
2319 // Use vld1/vst1 for Q and QQ. Also use them for unaligned v2f64
2320 // load / store if it's legal.
2321 def : Pat<(v2f64 (dword_alignedload addrmode6:$addr)),
2322 (VLD1q64 addrmode6:$addr)>;
2323 def : Pat<(dword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2324 (VST1q64 addrmode6:$addr, QPR:$value)>;
2325 def : Pat<(v2f64 (word_alignedload addrmode6:$addr)),
2326 (VLD1q32 addrmode6:$addr)>;
2327 def : Pat<(word_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2328 (VST1q32 addrmode6:$addr, QPR:$value)>;
2329 def : Pat<(v2f64 (hword_alignedload addrmode6:$addr)),
2330 (VLD1q16 addrmode6:$addr)>, Requires<[IsLE]>;
2331 def : Pat<(hword_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2332 (VST1q16 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2333 def : Pat<(v2f64 (byte_alignedload addrmode6:$addr)),
2334 (VLD1q8 addrmode6:$addr)>, Requires<[IsLE]>;
2335 def : Pat<(byte_alignedstore (v2f64 QPR:$value), addrmode6:$addr),
2336 (VST1q8 addrmode6:$addr, QPR:$value)>, Requires<[IsLE]>;
2338 //===----------------------------------------------------------------------===//
2339 // NEON pattern fragments
2340 //===----------------------------------------------------------------------===//
2342 // Extract D sub-registers of Q registers.
2343 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2344 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2345 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2347 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2348 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2349 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2351 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2352 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2353 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2355 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2356 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2357 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2360 // Extract S sub-registers of Q/D registers.
2361 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2362 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2363 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2366 // Translate lane numbers from Q registers to D subregs.
2367 def SubReg_i8_lane : SDNodeXForm<imm, [{
2368 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2370 def SubReg_i16_lane : SDNodeXForm<imm, [{
2371 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2373 def SubReg_i32_lane : SDNodeXForm<imm, [{
2374 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2377 //===----------------------------------------------------------------------===//
2378 // Instruction Classes
2379 //===----------------------------------------------------------------------===//
2381 // Basic 2-register operations: double- and quad-register.
2382 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2383 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2384 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2385 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2386 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2387 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2388 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2389 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2390 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2391 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2392 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2393 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2395 // Basic 2-register intrinsics, both double- and quad-register.
2396 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2397 bits<2> op17_16, bits<5> op11_7, bit op4,
2398 InstrItinClass itin, string OpcodeStr, string Dt,
2399 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2400 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2401 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2402 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2403 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2404 bits<2> op17_16, bits<5> op11_7, bit op4,
2405 InstrItinClass itin, string OpcodeStr, string Dt,
2406 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2407 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2408 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2409 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2411 // Same as above, but not predicated.
2412 class N2VDIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2413 InstrItinClass itin, string OpcodeStr, string Dt,
2414 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2415 : N2Vnp<0b10, op17_16, op10_8, op7, 0, (outs DPR:$Vd), (ins DPR:$Vm),
2416 itin, OpcodeStr, Dt, ResTy, OpTy,
2417 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2419 class N2VQIntnp<bits<2> op17_16, bits<3> op10_8, bit op7,
2420 InstrItinClass itin, string OpcodeStr, string Dt,
2421 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2422 : N2Vnp<0b10, op17_16, op10_8, op7, 1, (outs QPR:$Vd), (ins QPR:$Vm),
2423 itin, OpcodeStr, Dt, ResTy, OpTy,
2424 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2426 // Similar to NV2VQIntnp with some more encoding bits exposed (crypto).
2427 class N2VQIntXnp<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2428 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2429 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2430 : N2Vnp<op19_18, op17_16, op10_8, op7, op6, (outs QPR:$Vd), (ins QPR:$Vm),
2431 itin, OpcodeStr, Dt, ResTy, OpTy,
2432 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2434 // Same as N2VQIntXnp but with Vd as a src register.
2435 class N2VQIntX2np<bits<2> op19_18, bits<2> op17_16, bits<3> op10_8, bit op6,
2436 bit op7, InstrItinClass itin, string OpcodeStr, string Dt,
2437 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2438 : N2Vnp<op19_18, op17_16, op10_8, op7, op6,
2439 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vm),
2440 itin, OpcodeStr, Dt, ResTy, OpTy,
2441 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vm))))]> {
2442 let Constraints = "$src = $Vd";
2445 // Narrow 2-register operations.
2446 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2447 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2448 InstrItinClass itin, string OpcodeStr, string Dt,
2449 ValueType TyD, ValueType TyQ, SDNode OpNode>
2450 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2451 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2452 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2454 // Narrow 2-register intrinsics.
2455 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2456 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2457 InstrItinClass itin, string OpcodeStr, string Dt,
2458 ValueType TyD, ValueType TyQ, SDPatternOperator IntOp>
2459 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2460 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2461 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2463 // Long 2-register operations (currently only used for VMOVL).
2464 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2465 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2466 InstrItinClass itin, string OpcodeStr, string Dt,
2467 ValueType TyQ, ValueType TyD, SDNode OpNode>
2468 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2469 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2470 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2472 // Long 2-register intrinsics.
2473 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2474 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2475 InstrItinClass itin, string OpcodeStr, string Dt,
2476 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2477 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2478 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2479 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2481 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2482 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2483 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2484 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2485 OpcodeStr, Dt, "$Vd, $Vm",
2486 "$src1 = $Vd, $src2 = $Vm", []>;
2487 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2488 InstrItinClass itin, string OpcodeStr, string Dt>
2489 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2490 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2491 "$src1 = $Vd, $src2 = $Vm", []>;
2493 // Basic 3-register operations: double- and quad-register.
2494 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2495 InstrItinClass itin, string OpcodeStr, string Dt,
2496 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2497 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2498 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2499 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2500 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2501 // All of these have a two-operand InstAlias.
2502 let TwoOperandAliasConstraint = "$Vn = $Vd";
2503 let isCommutable = Commutable;
2505 // Same as N3VD but no data type.
2506 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2507 InstrItinClass itin, string OpcodeStr,
2508 ValueType ResTy, ValueType OpTy,
2509 SDNode OpNode, bit Commutable>
2510 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2511 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2512 OpcodeStr, "$Vd, $Vn, $Vm", "",
2513 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2514 // All of these have a two-operand InstAlias.
2515 let TwoOperandAliasConstraint = "$Vn = $Vd";
2516 let isCommutable = Commutable;
2519 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2520 InstrItinClass itin, string OpcodeStr, string Dt,
2521 ValueType Ty, SDNode ShOp>
2522 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2523 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2524 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2526 (Ty (ShOp (Ty DPR:$Vn),
2527 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2528 // All of these have a two-operand InstAlias.
2529 let TwoOperandAliasConstraint = "$Vn = $Vd";
2530 let isCommutable = 0;
2532 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2533 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2534 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2535 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2536 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2538 (Ty (ShOp (Ty DPR:$Vn),
2539 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2540 // All of these have a two-operand InstAlias.
2541 let TwoOperandAliasConstraint = "$Vn = $Vd";
2542 let isCommutable = 0;
2545 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2546 InstrItinClass itin, string OpcodeStr, string Dt,
2547 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2548 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2549 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2550 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2551 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2552 // All of these have a two-operand InstAlias.
2553 let TwoOperandAliasConstraint = "$Vn = $Vd";
2554 let isCommutable = Commutable;
2556 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2557 InstrItinClass itin, string OpcodeStr,
2558 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2559 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2560 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2561 OpcodeStr, "$Vd, $Vn, $Vm", "",
2562 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2563 // All of these have a two-operand InstAlias.
2564 let TwoOperandAliasConstraint = "$Vn = $Vd";
2565 let isCommutable = Commutable;
2567 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2568 InstrItinClass itin, string OpcodeStr, string Dt,
2569 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2570 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2571 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2572 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2573 [(set (ResTy QPR:$Vd),
2574 (ResTy (ShOp (ResTy QPR:$Vn),
2575 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2577 // All of these have a two-operand InstAlias.
2578 let TwoOperandAliasConstraint = "$Vn = $Vd";
2579 let isCommutable = 0;
2581 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2582 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2583 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2584 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2585 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2586 [(set (ResTy QPR:$Vd),
2587 (ResTy (ShOp (ResTy QPR:$Vn),
2588 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2590 // All of these have a two-operand InstAlias.
2591 let TwoOperandAliasConstraint = "$Vn = $Vd";
2592 let isCommutable = 0;
2595 // Basic 3-register intrinsics, both double- and quad-register.
2596 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2597 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2598 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2599 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2600 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2601 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2602 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2603 // All of these have a two-operand InstAlias.
2604 let TwoOperandAliasConstraint = "$Vn = $Vd";
2605 let isCommutable = Commutable;
2608 class N3VDIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2609 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2610 string Dt, ValueType ResTy, ValueType OpTy,
2611 SDPatternOperator IntOp, bit Commutable>
2612 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2613 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2614 ResTy, OpTy, IntOp, Commutable,
2615 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2617 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2618 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2619 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2620 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2621 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2623 (Ty (IntOp (Ty DPR:$Vn),
2624 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2626 let isCommutable = 0;
2629 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2630 string OpcodeStr, string Dt, ValueType Ty, SDPatternOperator IntOp>
2631 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2632 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2633 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2635 (Ty (IntOp (Ty DPR:$Vn),
2636 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2637 let isCommutable = 0;
2639 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2640 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2641 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2642 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2643 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2644 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2645 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2646 let TwoOperandAliasConstraint = "$Vm = $Vd";
2647 let isCommutable = 0;
2650 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2651 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2652 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp, bit Commutable>
2653 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2654 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2655 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2656 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2657 // All of these have a two-operand InstAlias.
2658 let TwoOperandAliasConstraint = "$Vn = $Vd";
2659 let isCommutable = Commutable;
2662 class N3VQIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2663 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2664 string Dt, ValueType ResTy, ValueType OpTy,
2665 SDPatternOperator IntOp, bit Commutable>
2666 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2667 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr, Dt,
2668 ResTy, OpTy, IntOp, Commutable,
2669 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2671 // Same as N3VQIntnp but with Vd as a src register.
2672 class N3VQInt3np<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2673 bit op4, Format f, InstrItinClass itin, string OpcodeStr,
2674 string Dt, ValueType ResTy, ValueType OpTy,
2675 SDPatternOperator IntOp, bit Commutable>
2676 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2677 (outs QPR:$Vd), (ins QPR:$src, QPR:$Vn, QPR:$Vm), f, itin, OpcodeStr,
2678 Dt, ResTy, OpTy, IntOp, Commutable,
2679 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src), (OpTy QPR:$Vn),
2680 (OpTy QPR:$Vm))))]> {
2681 let Constraints = "$src = $Vd";
2684 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2685 string OpcodeStr, string Dt,
2686 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2687 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2688 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2689 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2690 [(set (ResTy QPR:$Vd),
2691 (ResTy (IntOp (ResTy QPR:$Vn),
2692 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2694 let isCommutable = 0;
2696 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2697 string OpcodeStr, string Dt,
2698 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2699 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2700 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2701 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2702 [(set (ResTy QPR:$Vd),
2703 (ResTy (IntOp (ResTy QPR:$Vn),
2704 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2706 let isCommutable = 0;
2708 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2709 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2710 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2711 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2712 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2713 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2714 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2715 let TwoOperandAliasConstraint = "$Vm = $Vd";
2716 let isCommutable = 0;
2719 // Multiply-Add/Sub operations: double- and quad-register.
2720 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2721 InstrItinClass itin, string OpcodeStr, string Dt,
2722 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2723 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2724 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2725 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2726 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2727 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2729 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2730 string OpcodeStr, string Dt,
2731 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2732 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2734 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2736 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2738 (Ty (ShOp (Ty DPR:$src1),
2740 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2742 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2743 string OpcodeStr, string Dt,
2744 ValueType Ty, SDNode MulOp, SDNode ShOp>
2745 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2747 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2749 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2751 (Ty (ShOp (Ty DPR:$src1),
2753 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2756 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2757 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2758 SDPatternOperator MulOp, SDPatternOperator OpNode>
2759 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2760 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2761 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2762 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2763 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2764 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2765 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2766 SDPatternOperator MulOp, SDPatternOperator ShOp>
2767 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2769 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2771 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2772 [(set (ResTy QPR:$Vd),
2773 (ResTy (ShOp (ResTy QPR:$src1),
2774 (ResTy (MulOp QPR:$Vn,
2775 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2777 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2778 string OpcodeStr, string Dt,
2779 ValueType ResTy, ValueType OpTy,
2780 SDNode MulOp, SDNode ShOp>
2781 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2783 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2785 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2786 [(set (ResTy QPR:$Vd),
2787 (ResTy (ShOp (ResTy QPR:$src1),
2788 (ResTy (MulOp QPR:$Vn,
2789 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2792 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2793 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2794 InstrItinClass itin, string OpcodeStr, string Dt,
2795 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2796 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2797 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2798 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2799 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2800 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2801 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2802 InstrItinClass itin, string OpcodeStr, string Dt,
2803 ValueType Ty, SDPatternOperator IntOp, SDNode OpNode>
2804 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2805 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2806 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2807 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2808 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2810 // Neon 3-argument intrinsics, both double- and quad-register.
2811 // The destination register is also used as the first source operand register.
2812 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2813 InstrItinClass itin, string OpcodeStr, string Dt,
2814 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2815 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2816 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2817 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2818 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2819 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2820 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2821 InstrItinClass itin, string OpcodeStr, string Dt,
2822 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2823 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2824 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2825 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2826 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2827 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2829 // Long Multiply-Add/Sub operations.
2830 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2831 InstrItinClass itin, string OpcodeStr, string Dt,
2832 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2833 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2834 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2835 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2836 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2837 (TyQ (MulOp (TyD DPR:$Vn),
2838 (TyD DPR:$Vm)))))]>;
2839 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2840 InstrItinClass itin, string OpcodeStr, string Dt,
2841 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2842 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2843 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2845 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2847 (OpNode (TyQ QPR:$src1),
2848 (TyQ (MulOp (TyD DPR:$Vn),
2849 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2851 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2852 InstrItinClass itin, string OpcodeStr, string Dt,
2853 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2854 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2855 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2857 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2859 (OpNode (TyQ QPR:$src1),
2860 (TyQ (MulOp (TyD DPR:$Vn),
2861 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2864 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2865 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2866 InstrItinClass itin, string OpcodeStr, string Dt,
2867 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2869 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2870 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2871 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2872 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2873 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2874 (TyD DPR:$Vm)))))))]>;
2876 // Neon Long 3-argument intrinsic. The destination register is
2877 // a quad-register and is also used as the first source operand register.
2878 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2879 InstrItinClass itin, string OpcodeStr, string Dt,
2880 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp>
2881 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2882 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2883 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2885 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2886 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2887 string OpcodeStr, string Dt,
2888 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2889 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2891 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2893 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2894 [(set (ResTy QPR:$Vd),
2895 (ResTy (IntOp (ResTy QPR:$src1),
2897 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2899 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2900 InstrItinClass itin, string OpcodeStr, string Dt,
2901 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
2902 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2904 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2906 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2907 [(set (ResTy QPR:$Vd),
2908 (ResTy (IntOp (ResTy QPR:$src1),
2910 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2913 // Narrowing 3-register intrinsics.
2914 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2915 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2916 SDPatternOperator IntOp, bit Commutable>
2917 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2918 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2919 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2920 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2921 let isCommutable = Commutable;
2924 // Long 3-register operations.
2925 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2926 InstrItinClass itin, string OpcodeStr, string Dt,
2927 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2928 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2929 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2930 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2931 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2932 let isCommutable = Commutable;
2935 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2936 InstrItinClass itin, string OpcodeStr, string Dt,
2937 ValueType TyQ, ValueType TyD, SDNode OpNode>
2938 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2939 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2940 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2942 (TyQ (OpNode (TyD DPR:$Vn),
2943 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2944 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2945 InstrItinClass itin, string OpcodeStr, string Dt,
2946 ValueType TyQ, ValueType TyD, SDNode OpNode>
2947 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2948 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2949 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2951 (TyQ (OpNode (TyD DPR:$Vn),
2952 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2954 // Long 3-register operations with explicitly extended operands.
2955 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2956 InstrItinClass itin, string OpcodeStr, string Dt,
2957 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2959 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2960 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2961 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2962 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2963 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2964 let isCommutable = Commutable;
2967 // Long 3-register intrinsics with explicit extend (VABDL).
2968 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2969 InstrItinClass itin, string OpcodeStr, string Dt,
2970 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, SDNode ExtOp,
2972 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2973 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2974 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2975 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2976 (TyD DPR:$Vm))))))]> {
2977 let isCommutable = Commutable;
2980 // Long 3-register intrinsics.
2981 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2982 InstrItinClass itin, string OpcodeStr, string Dt,
2983 ValueType TyQ, ValueType TyD, SDPatternOperator IntOp, bit Commutable>
2984 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2985 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2986 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2987 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2988 let isCommutable = Commutable;
2991 // Same as above, but not predicated.
2992 class N3VLIntnp<bits<5> op27_23, bits<2> op21_20, bits<4> op11_8, bit op6,
2993 bit op4, InstrItinClass itin, string OpcodeStr,
2994 string Dt, ValueType ResTy, ValueType OpTy,
2995 SDPatternOperator IntOp, bit Commutable>
2996 : N3Vnp<op27_23, op21_20, op11_8, op6, op4,
2997 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin, OpcodeStr, Dt,
2998 ResTy, OpTy, IntOp, Commutable,
2999 [(set QPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
3001 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
3002 string OpcodeStr, string Dt,
3003 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3004 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
3005 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
3006 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3007 [(set (ResTy QPR:$Vd),
3008 (ResTy (IntOp (OpTy DPR:$Vn),
3009 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
3011 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
3012 InstrItinClass itin, string OpcodeStr, string Dt,
3013 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3014 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
3015 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
3016 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
3017 [(set (ResTy QPR:$Vd),
3018 (ResTy (IntOp (OpTy DPR:$Vn),
3019 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
3022 // Wide 3-register operations.
3023 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
3024 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
3025 SDNode OpNode, SDNode ExtOp, bit Commutable>
3026 : N3V<op24, op23, op21_20, op11_8, 0, op4,
3027 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
3028 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
3029 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
3030 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
3031 // All of these have a two-operand InstAlias.
3032 let TwoOperandAliasConstraint = "$Vn = $Vd";
3033 let isCommutable = Commutable;
3036 // Pairwise long 2-register intrinsics, both double- and quad-register.
3037 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3038 bits<2> op17_16, bits<5> op11_7, bit op4,
3039 string OpcodeStr, string Dt,
3040 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3041 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
3042 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3043 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
3044 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3045 bits<2> op17_16, bits<5> op11_7, bit op4,
3046 string OpcodeStr, string Dt,
3047 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3048 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
3049 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
3050 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
3052 // Pairwise long 2-register accumulate intrinsics,
3053 // both double- and quad-register.
3054 // The destination register is also used as the first source operand register.
3055 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3056 bits<2> op17_16, bits<5> op11_7, bit op4,
3057 string OpcodeStr, string Dt,
3058 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3059 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
3060 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
3061 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3062 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
3063 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
3064 bits<2> op17_16, bits<5> op11_7, bit op4,
3065 string OpcodeStr, string Dt,
3066 ValueType ResTy, ValueType OpTy, SDPatternOperator IntOp>
3067 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
3068 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
3069 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
3070 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
3072 // Shift by immediate,
3073 // both double- and quad-register.
3074 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3075 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3076 Format f, InstrItinClass itin, Operand ImmTy,
3077 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3078 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3079 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
3080 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3081 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
3082 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3083 Format f, InstrItinClass itin, Operand ImmTy,
3084 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
3085 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3086 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
3087 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3088 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
3091 // Long shift by immediate.
3092 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3093 string OpcodeStr, string Dt,
3094 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3095 SDPatternOperator OpNode>
3096 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3097 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
3098 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3099 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm), ImmTy:$SIMM)))]>;
3101 // Narrow shift by immediate.
3102 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
3103 InstrItinClass itin, string OpcodeStr, string Dt,
3104 ValueType ResTy, ValueType OpTy, Operand ImmTy,
3105 SDPatternOperator OpNode>
3106 : N2VImm<op24, op23, op11_8, op7, op6, op4,
3107 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
3108 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3109 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
3110 (i32 ImmTy:$SIMM))))]>;
3112 // Shift right by immediate and accumulate,
3113 // both double- and quad-register.
3114 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3115 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3116 Operand ImmTy, string OpcodeStr, string Dt,
3117 ValueType Ty, SDNode ShOp>
3118 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3119 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3120 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3121 [(set DPR:$Vd, (Ty (add DPR:$src1,
3122 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
3123 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3124 Operand ImmTy, string OpcodeStr, string Dt,
3125 ValueType Ty, SDNode ShOp>
3126 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3127 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
3128 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3129 [(set QPR:$Vd, (Ty (add QPR:$src1,
3130 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
3133 // Shift by immediate and insert,
3134 // both double- and quad-register.
3135 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
3136 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3137 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3138 ValueType Ty,SDNode ShOp>
3139 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
3140 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
3141 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3142 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
3143 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3144 Operand ImmTy, Format f, string OpcodeStr, string Dt,
3145 ValueType Ty,SDNode ShOp>
3146 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
3147 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
3148 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
3149 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
3152 // Convert, with fractional bits immediate,
3153 // both double- and quad-register.
3154 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3155 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3156 SDPatternOperator IntOp>
3157 : N2VImm<op24, op23, op11_8, op7, 0, op4,
3158 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3159 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3160 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
3161 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
3162 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
3163 SDPatternOperator IntOp>
3164 : N2VImm<op24, op23, op11_8, op7, 1, op4,
3165 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
3166 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
3167 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
3169 //===----------------------------------------------------------------------===//
3171 //===----------------------------------------------------------------------===//
3173 // Abbreviations used in multiclass suffixes:
3174 // Q = quarter int (8 bit) elements
3175 // H = half int (16 bit) elements
3176 // S = single int (32 bit) elements
3177 // D = double int (64 bit) elements
3179 // Neon 2-register vector operations and intrinsics.
3181 // Neon 2-register comparisons.
3182 // source operand element sizes of 8, 16 and 32 bits:
3183 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3184 bits<5> op11_7, bit op4, string opc, string Dt,
3185 string asm, SDNode OpNode> {
3186 // 64-bit vector types.
3187 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
3188 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3189 opc, !strconcat(Dt, "8"), asm, "",
3190 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
3191 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
3192 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3193 opc, !strconcat(Dt, "16"), asm, "",
3194 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
3195 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3196 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3197 opc, !strconcat(Dt, "32"), asm, "",
3198 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
3199 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
3200 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
3201 opc, "f32", asm, "",
3202 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
3203 let Inst{10} = 1; // overwrite F = 1
3206 // 128-bit vector types.
3207 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
3208 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3209 opc, !strconcat(Dt, "8"), asm, "",
3210 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
3211 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
3212 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3213 opc, !strconcat(Dt, "16"), asm, "",
3214 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
3215 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3216 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3217 opc, !strconcat(Dt, "32"), asm, "",
3218 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
3219 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
3220 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
3221 opc, "f32", asm, "",
3222 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
3223 let Inst{10} = 1; // overwrite F = 1
3228 // Neon 2-register vector intrinsics,
3229 // element sizes of 8, 16 and 32 bits:
3230 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3231 bits<5> op11_7, bit op4,
3232 InstrItinClass itinD, InstrItinClass itinQ,
3233 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3234 // 64-bit vector types.
3235 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3236 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3237 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3238 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
3239 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3240 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
3242 // 128-bit vector types.
3243 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3244 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
3245 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3246 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
3247 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3248 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
3252 // Neon Narrowing 2-register vector operations,
3253 // source operand element sizes of 16, 32 and 64 bits:
3254 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3255 bits<5> op11_7, bit op6, bit op4,
3256 InstrItinClass itin, string OpcodeStr, string Dt,
3258 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3259 itin, OpcodeStr, !strconcat(Dt, "16"),
3260 v8i8, v8i16, OpNode>;
3261 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3262 itin, OpcodeStr, !strconcat(Dt, "32"),
3263 v4i16, v4i32, OpNode>;
3264 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3265 itin, OpcodeStr, !strconcat(Dt, "64"),
3266 v2i32, v2i64, OpNode>;
3269 // Neon Narrowing 2-register vector intrinsics,
3270 // source operand element sizes of 16, 32 and 64 bits:
3271 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3272 bits<5> op11_7, bit op6, bit op4,
3273 InstrItinClass itin, string OpcodeStr, string Dt,
3274 SDPatternOperator IntOp> {
3275 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
3276 itin, OpcodeStr, !strconcat(Dt, "16"),
3277 v8i8, v8i16, IntOp>;
3278 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
3279 itin, OpcodeStr, !strconcat(Dt, "32"),
3280 v4i16, v4i32, IntOp>;
3281 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
3282 itin, OpcodeStr, !strconcat(Dt, "64"),
3283 v2i32, v2i64, IntOp>;
3287 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
3288 // source operand element sizes of 16, 32 and 64 bits:
3289 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
3290 string OpcodeStr, string Dt, SDNode OpNode> {
3291 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3292 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
3293 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3294 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3295 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
3296 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3300 // Neon 3-register vector operations.
3302 // First with only element sizes of 8, 16 and 32 bits:
3303 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3304 InstrItinClass itinD16, InstrItinClass itinD32,
3305 InstrItinClass itinQ16, InstrItinClass itinQ32,
3306 string OpcodeStr, string Dt,
3307 SDNode OpNode, bit Commutable = 0> {
3308 // 64-bit vector types.
3309 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
3310 OpcodeStr, !strconcat(Dt, "8"),
3311 v8i8, v8i8, OpNode, Commutable>;
3312 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
3313 OpcodeStr, !strconcat(Dt, "16"),
3314 v4i16, v4i16, OpNode, Commutable>;
3315 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
3316 OpcodeStr, !strconcat(Dt, "32"),
3317 v2i32, v2i32, OpNode, Commutable>;
3319 // 128-bit vector types.
3320 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
3321 OpcodeStr, !strconcat(Dt, "8"),
3322 v16i8, v16i8, OpNode, Commutable>;
3323 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
3324 OpcodeStr, !strconcat(Dt, "16"),
3325 v8i16, v8i16, OpNode, Commutable>;
3326 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
3327 OpcodeStr, !strconcat(Dt, "32"),
3328 v4i32, v4i32, OpNode, Commutable>;
3331 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
3332 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
3333 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
3334 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
3335 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
3336 v4i32, v2i32, ShOp>;
3339 // ....then also with element size 64 bits:
3340 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3341 InstrItinClass itinD, InstrItinClass itinQ,
3342 string OpcodeStr, string Dt,
3343 SDNode OpNode, bit Commutable = 0>
3344 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
3345 OpcodeStr, Dt, OpNode, Commutable> {
3346 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
3347 OpcodeStr, !strconcat(Dt, "64"),
3348 v1i64, v1i64, OpNode, Commutable>;
3349 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3350 OpcodeStr, !strconcat(Dt, "64"),
3351 v2i64, v2i64, OpNode, Commutable>;
3355 // Neon 3-register vector intrinsics.
3357 // First with only element sizes of 16 and 32 bits:
3358 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3359 InstrItinClass itinD16, InstrItinClass itinD32,
3360 InstrItinClass itinQ16, InstrItinClass itinQ32,
3361 string OpcodeStr, string Dt,
3362 SDPatternOperator IntOp, bit Commutable = 0> {
3363 // 64-bit vector types.
3364 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3365 OpcodeStr, !strconcat(Dt, "16"),
3366 v4i16, v4i16, IntOp, Commutable>;
3367 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3368 OpcodeStr, !strconcat(Dt, "32"),
3369 v2i32, v2i32, IntOp, Commutable>;
3371 // 128-bit vector types.
3372 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3373 OpcodeStr, !strconcat(Dt, "16"),
3374 v8i16, v8i16, IntOp, Commutable>;
3375 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3376 OpcodeStr, !strconcat(Dt, "32"),
3377 v4i32, v4i32, IntOp, Commutable>;
3379 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3380 InstrItinClass itinD16, InstrItinClass itinD32,
3381 InstrItinClass itinQ16, InstrItinClass itinQ32,
3382 string OpcodeStr, string Dt,
3383 SDPatternOperator IntOp> {
3384 // 64-bit vector types.
3385 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3386 OpcodeStr, !strconcat(Dt, "16"),
3387 v4i16, v4i16, IntOp>;
3388 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3389 OpcodeStr, !strconcat(Dt, "32"),
3390 v2i32, v2i32, IntOp>;
3392 // 128-bit vector types.
3393 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3394 OpcodeStr, !strconcat(Dt, "16"),
3395 v8i16, v8i16, IntOp>;
3396 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3397 OpcodeStr, !strconcat(Dt, "32"),
3398 v4i32, v4i32, IntOp>;
3401 multiclass N3VIntSL_HS<bits<4> op11_8,
3402 InstrItinClass itinD16, InstrItinClass itinD32,
3403 InstrItinClass itinQ16, InstrItinClass itinQ32,
3404 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3405 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3406 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3407 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3408 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3409 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3410 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3411 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3412 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3415 // ....then also with element size of 8 bits:
3416 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3417 InstrItinClass itinD16, InstrItinClass itinD32,
3418 InstrItinClass itinQ16, InstrItinClass itinQ32,
3419 string OpcodeStr, string Dt,
3420 SDPatternOperator IntOp, bit Commutable = 0>
3421 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3422 OpcodeStr, Dt, IntOp, Commutable> {
3423 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3424 OpcodeStr, !strconcat(Dt, "8"),
3425 v8i8, v8i8, IntOp, Commutable>;
3426 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3427 OpcodeStr, !strconcat(Dt, "8"),
3428 v16i8, v16i8, IntOp, Commutable>;
3430 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3431 InstrItinClass itinD16, InstrItinClass itinD32,
3432 InstrItinClass itinQ16, InstrItinClass itinQ32,
3433 string OpcodeStr, string Dt,
3434 SDPatternOperator IntOp>
3435 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3436 OpcodeStr, Dt, IntOp> {
3437 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3438 OpcodeStr, !strconcat(Dt, "8"),
3440 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3441 OpcodeStr, !strconcat(Dt, "8"),
3442 v16i8, v16i8, IntOp>;
3446 // ....then also with element size of 64 bits:
3447 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3448 InstrItinClass itinD16, InstrItinClass itinD32,
3449 InstrItinClass itinQ16, InstrItinClass itinQ32,
3450 string OpcodeStr, string Dt,
3451 SDPatternOperator IntOp, bit Commutable = 0>
3452 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3453 OpcodeStr, Dt, IntOp, Commutable> {
3454 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3455 OpcodeStr, !strconcat(Dt, "64"),
3456 v1i64, v1i64, IntOp, Commutable>;
3457 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3458 OpcodeStr, !strconcat(Dt, "64"),
3459 v2i64, v2i64, IntOp, Commutable>;
3461 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3462 InstrItinClass itinD16, InstrItinClass itinD32,
3463 InstrItinClass itinQ16, InstrItinClass itinQ32,
3464 string OpcodeStr, string Dt,
3465 SDPatternOperator IntOp>
3466 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3467 OpcodeStr, Dt, IntOp> {
3468 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3469 OpcodeStr, !strconcat(Dt, "64"),
3470 v1i64, v1i64, IntOp>;
3471 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3472 OpcodeStr, !strconcat(Dt, "64"),
3473 v2i64, v2i64, IntOp>;
3476 // Neon Narrowing 3-register vector intrinsics,
3477 // source operand element sizes of 16, 32 and 64 bits:
3478 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3479 string OpcodeStr, string Dt,
3480 SDPatternOperator IntOp, bit Commutable = 0> {
3481 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3482 OpcodeStr, !strconcat(Dt, "16"),
3483 v8i8, v8i16, IntOp, Commutable>;
3484 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3485 OpcodeStr, !strconcat(Dt, "32"),
3486 v4i16, v4i32, IntOp, Commutable>;
3487 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3488 OpcodeStr, !strconcat(Dt, "64"),
3489 v2i32, v2i64, IntOp, Commutable>;
3493 // Neon Long 3-register vector operations.
3495 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3496 InstrItinClass itin16, InstrItinClass itin32,
3497 string OpcodeStr, string Dt,
3498 SDNode OpNode, bit Commutable = 0> {
3499 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3500 OpcodeStr, !strconcat(Dt, "8"),
3501 v8i16, v8i8, OpNode, Commutable>;
3502 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3503 OpcodeStr, !strconcat(Dt, "16"),
3504 v4i32, v4i16, OpNode, Commutable>;
3505 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3506 OpcodeStr, !strconcat(Dt, "32"),
3507 v2i64, v2i32, OpNode, Commutable>;
3510 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3511 InstrItinClass itin, string OpcodeStr, string Dt,
3513 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3514 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3515 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3516 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3519 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3520 InstrItinClass itin16, InstrItinClass itin32,
3521 string OpcodeStr, string Dt,
3522 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3523 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3524 OpcodeStr, !strconcat(Dt, "8"),
3525 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3526 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3527 OpcodeStr, !strconcat(Dt, "16"),
3528 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3529 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3530 OpcodeStr, !strconcat(Dt, "32"),
3531 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3534 // Neon Long 3-register vector intrinsics.
3536 // First with only element sizes of 16 and 32 bits:
3537 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3538 InstrItinClass itin16, InstrItinClass itin32,
3539 string OpcodeStr, string Dt,
3540 SDPatternOperator IntOp, bit Commutable = 0> {
3541 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3542 OpcodeStr, !strconcat(Dt, "16"),
3543 v4i32, v4i16, IntOp, Commutable>;
3544 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3545 OpcodeStr, !strconcat(Dt, "32"),
3546 v2i64, v2i32, IntOp, Commutable>;
3549 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3550 InstrItinClass itin, string OpcodeStr, string Dt,
3551 SDPatternOperator IntOp> {
3552 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3553 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3554 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3555 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3558 // ....then also with element size of 8 bits:
3559 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3560 InstrItinClass itin16, InstrItinClass itin32,
3561 string OpcodeStr, string Dt,
3562 SDPatternOperator IntOp, bit Commutable = 0>
3563 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3564 IntOp, Commutable> {
3565 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3566 OpcodeStr, !strconcat(Dt, "8"),
3567 v8i16, v8i8, IntOp, Commutable>;
3570 // ....with explicit extend (VABDL).
3571 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3572 InstrItinClass itin, string OpcodeStr, string Dt,
3573 SDPatternOperator IntOp, SDNode ExtOp, bit Commutable = 0> {
3574 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3575 OpcodeStr, !strconcat(Dt, "8"),
3576 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3577 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3578 OpcodeStr, !strconcat(Dt, "16"),
3579 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3580 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3581 OpcodeStr, !strconcat(Dt, "32"),
3582 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3586 // Neon Wide 3-register vector intrinsics,
3587 // source operand element sizes of 8, 16 and 32 bits:
3588 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3589 string OpcodeStr, string Dt,
3590 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3591 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3592 OpcodeStr, !strconcat(Dt, "8"),
3593 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3594 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3595 OpcodeStr, !strconcat(Dt, "16"),
3596 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3597 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3598 OpcodeStr, !strconcat(Dt, "32"),
3599 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3603 // Neon Multiply-Op vector operations,
3604 // element sizes of 8, 16 and 32 bits:
3605 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3606 InstrItinClass itinD16, InstrItinClass itinD32,
3607 InstrItinClass itinQ16, InstrItinClass itinQ32,
3608 string OpcodeStr, string Dt, SDNode OpNode> {
3609 // 64-bit vector types.
3610 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3611 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3612 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3613 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3614 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3615 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3617 // 128-bit vector types.
3618 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3619 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3620 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3621 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3622 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3623 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3626 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3627 InstrItinClass itinD16, InstrItinClass itinD32,
3628 InstrItinClass itinQ16, InstrItinClass itinQ32,
3629 string OpcodeStr, string Dt, SDNode ShOp> {
3630 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3631 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3632 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3633 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3634 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3635 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3637 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3638 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3642 // Neon Intrinsic-Op vector operations,
3643 // element sizes of 8, 16 and 32 bits:
3644 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3645 InstrItinClass itinD, InstrItinClass itinQ,
3646 string OpcodeStr, string Dt, SDPatternOperator IntOp,
3648 // 64-bit vector types.
3649 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3650 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3651 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3652 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3653 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3654 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3656 // 128-bit vector types.
3657 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3658 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3659 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3660 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3661 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3662 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3665 // Neon 3-argument intrinsics,
3666 // element sizes of 8, 16 and 32 bits:
3667 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3668 InstrItinClass itinD, InstrItinClass itinQ,
3669 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3670 // 64-bit vector types.
3671 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3672 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3673 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3674 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3675 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3676 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3678 // 128-bit vector types.
3679 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3680 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3681 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3682 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3683 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3684 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3688 // Neon Long Multiply-Op vector operations,
3689 // element sizes of 8, 16 and 32 bits:
3690 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3691 InstrItinClass itin16, InstrItinClass itin32,
3692 string OpcodeStr, string Dt, SDNode MulOp,
3694 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3695 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3696 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3697 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3698 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3699 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3702 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3703 string Dt, SDNode MulOp, SDNode OpNode> {
3704 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3705 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3706 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3707 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3711 // Neon Long 3-argument intrinsics.
3713 // First with only element sizes of 16 and 32 bits:
3714 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3715 InstrItinClass itin16, InstrItinClass itin32,
3716 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3717 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3718 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3719 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3720 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3723 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3724 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3725 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3726 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3727 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3728 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3731 // ....then also with element size of 8 bits:
3732 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3733 InstrItinClass itin16, InstrItinClass itin32,
3734 string OpcodeStr, string Dt, SDPatternOperator IntOp>
3735 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3736 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3737 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3740 // ....with explicit extend (VABAL).
3741 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3742 InstrItinClass itin, string OpcodeStr, string Dt,
3743 SDPatternOperator IntOp, SDNode ExtOp, SDNode OpNode> {
3744 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3745 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3746 IntOp, ExtOp, OpNode>;
3747 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3748 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3749 IntOp, ExtOp, OpNode>;
3750 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3751 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3752 IntOp, ExtOp, OpNode>;
3756 // Neon Pairwise long 2-register intrinsics,
3757 // element sizes of 8, 16 and 32 bits:
3758 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3759 bits<5> op11_7, bit op4,
3760 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3761 // 64-bit vector types.
3762 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3763 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3764 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3765 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3766 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3767 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3769 // 128-bit vector types.
3770 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3771 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3772 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3773 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3774 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3775 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3779 // Neon Pairwise long 2-register accumulate intrinsics,
3780 // element sizes of 8, 16 and 32 bits:
3781 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3782 bits<5> op11_7, bit op4,
3783 string OpcodeStr, string Dt, SDPatternOperator IntOp> {
3784 // 64-bit vector types.
3785 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3786 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3787 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3788 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3789 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3790 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3792 // 128-bit vector types.
3793 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3794 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3795 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3796 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3797 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3798 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3802 // Neon 2-register vector shift by immediate,
3803 // with f of either N2RegVShLFrm or N2RegVShRFrm
3804 // element sizes of 8, 16, 32 and 64 bits:
3805 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3806 InstrItinClass itin, string OpcodeStr, string Dt,
3808 // 64-bit vector types.
3809 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3810 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3811 let Inst{21-19} = 0b001; // imm6 = 001xxx
3813 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3814 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3815 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3817 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3818 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3819 let Inst{21} = 0b1; // imm6 = 1xxxxx
3821 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3822 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3825 // 128-bit vector types.
3826 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3827 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3828 let Inst{21-19} = 0b001; // imm6 = 001xxx
3830 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3831 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3832 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3834 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3835 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3836 let Inst{21} = 0b1; // imm6 = 1xxxxx
3838 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3839 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3842 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3843 InstrItinClass itin, string OpcodeStr, string Dt,
3844 string baseOpc, SDNode OpNode> {
3845 // 64-bit vector types.
3846 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3847 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3848 let Inst{21-19} = 0b001; // imm6 = 001xxx
3850 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3851 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3852 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3854 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3855 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3856 let Inst{21} = 0b1; // imm6 = 1xxxxx
3858 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3859 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3862 // 128-bit vector types.
3863 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3864 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3865 let Inst{21-19} = 0b001; // imm6 = 001xxx
3867 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3868 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3869 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3871 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3872 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3873 let Inst{21} = 0b1; // imm6 = 1xxxxx
3875 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3876 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3880 // Neon Shift-Accumulate vector operations,
3881 // element sizes of 8, 16, 32 and 64 bits:
3882 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3883 string OpcodeStr, string Dt, SDNode ShOp> {
3884 // 64-bit vector types.
3885 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3886 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3887 let Inst{21-19} = 0b001; // imm6 = 001xxx
3889 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3890 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3891 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3893 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3894 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3895 let Inst{21} = 0b1; // imm6 = 1xxxxx
3897 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3898 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3901 // 128-bit vector types.
3902 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3903 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3904 let Inst{21-19} = 0b001; // imm6 = 001xxx
3906 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3907 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3908 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3910 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3911 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3912 let Inst{21} = 0b1; // imm6 = 1xxxxx
3914 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3915 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3919 // Neon Shift-Insert vector operations,
3920 // with f of either N2RegVShLFrm or N2RegVShRFrm
3921 // element sizes of 8, 16, 32 and 64 bits:
3922 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3924 // 64-bit vector types.
3925 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3926 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3927 let Inst{21-19} = 0b001; // imm6 = 001xxx
3929 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3930 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3931 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3933 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3934 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3935 let Inst{21} = 0b1; // imm6 = 1xxxxx
3937 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3938 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3941 // 128-bit vector types.
3942 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3943 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3944 let Inst{21-19} = 0b001; // imm6 = 001xxx
3946 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3947 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3948 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3950 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3951 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3952 let Inst{21} = 0b1; // imm6 = 1xxxxx
3954 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3955 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3958 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3960 // 64-bit vector types.
3961 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3962 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3963 let Inst{21-19} = 0b001; // imm6 = 001xxx
3965 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3966 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3967 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3969 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3970 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3971 let Inst{21} = 0b1; // imm6 = 1xxxxx
3973 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3974 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3977 // 128-bit vector types.
3978 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3979 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3980 let Inst{21-19} = 0b001; // imm6 = 001xxx
3982 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3983 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3984 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3986 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3987 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3988 let Inst{21} = 0b1; // imm6 = 1xxxxx
3990 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3991 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3995 // Neon Shift Long operations,
3996 // element sizes of 8, 16, 32 bits:
3997 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3998 bit op4, string OpcodeStr, string Dt,
3999 SDPatternOperator OpNode> {
4000 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4001 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
4002 let Inst{21-19} = 0b001; // imm6 = 001xxx
4004 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4005 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
4006 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4008 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
4009 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
4010 let Inst{21} = 0b1; // imm6 = 1xxxxx
4014 // Neon Shift Narrow operations,
4015 // element sizes of 16, 32, 64 bits:
4016 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
4017 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
4018 SDPatternOperator OpNode> {
4019 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4020 OpcodeStr, !strconcat(Dt, "16"),
4021 v8i8, v8i16, shr_imm8, OpNode> {
4022 let Inst{21-19} = 0b001; // imm6 = 001xxx
4024 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4025 OpcodeStr, !strconcat(Dt, "32"),
4026 v4i16, v4i32, shr_imm16, OpNode> {
4027 let Inst{21-20} = 0b01; // imm6 = 01xxxx
4029 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
4030 OpcodeStr, !strconcat(Dt, "64"),
4031 v2i32, v2i64, shr_imm32, OpNode> {
4032 let Inst{21} = 0b1; // imm6 = 1xxxxx
4036 //===----------------------------------------------------------------------===//
4037 // Instruction Definitions.
4038 //===----------------------------------------------------------------------===//
4040 // Vector Add Operations.
4042 // VADD : Vector Add (integer and floating-point)
4043 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
4045 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
4046 v2f32, v2f32, fadd, 1>;
4047 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
4048 v4f32, v4f32, fadd, 1>;
4049 // VADDL : Vector Add Long (Q = D + D)
4050 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4051 "vaddl", "s", add, sext, 1>;
4052 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
4053 "vaddl", "u", add, zext, 1>;
4054 // VADDW : Vector Add Wide (Q = Q + D)
4055 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
4056 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
4057 // VHADD : Vector Halving Add
4058 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
4059 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4060 "vhadd", "s", int_arm_neon_vhadds, 1>;
4061 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
4062 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4063 "vhadd", "u", int_arm_neon_vhaddu, 1>;
4064 // VRHADD : Vector Rounding Halving Add
4065 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
4066 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4067 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
4068 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
4069 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4070 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
4071 // VQADD : Vector Saturating Add
4072 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
4073 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4074 "vqadd", "s", int_arm_neon_vqadds, 1>;
4075 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
4076 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
4077 "vqadd", "u", int_arm_neon_vqaddu, 1>;
4078 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
4079 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i", null_frag, 1>;
4080 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
4081 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
4082 int_arm_neon_vraddhn, 1>;
4084 def : Pat<(v8i8 (trunc (NEONvshru (add (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4085 (VADDHNv8i8 QPR:$Vn, QPR:$Vm)>;
4086 def : Pat<(v4i16 (trunc (NEONvshru (add (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4087 (VADDHNv4i16 QPR:$Vn, QPR:$Vm)>;
4088 def : Pat<(v2i32 (trunc (NEONvshru (add (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4089 (VADDHNv2i32 QPR:$Vn, QPR:$Vm)>;
4091 // Vector Multiply Operations.
4093 // VMUL : Vector Multiply (integer, polynomial and floating-point)
4094 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
4095 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
4096 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
4097 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
4098 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
4099 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
4100 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
4101 v2f32, v2f32, fmul, 1>;
4102 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
4103 v4f32, v4f32, fmul, 1>;
4104 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
4105 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
4106 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
4109 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
4110 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
4111 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
4112 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4113 (DSubReg_i16_reg imm:$lane))),
4114 (SubReg_i16_lane imm:$lane)))>;
4115 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
4116 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
4117 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
4118 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4119 (DSubReg_i32_reg imm:$lane))),
4120 (SubReg_i32_lane imm:$lane)))>;
4121 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
4122 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
4123 (v4f32 (VMULslfq (v4f32 QPR:$src1),
4124 (v2f32 (EXTRACT_SUBREG QPR:$src2,
4125 (DSubReg_i32_reg imm:$lane))),
4126 (SubReg_i32_lane imm:$lane)))>;
4129 def : Pat<(v2f32 (fmul DPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4131 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4133 def : Pat<(v4f32 (fmul QPR:$Rn, (NEONvdup (f32 SPR:$Rm)))),
4135 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4139 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
4140 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
4141 IIC_VMULi16Q, IIC_VMULi32Q,
4142 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
4143 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
4144 IIC_VMULi16Q, IIC_VMULi32Q,
4145 "vqdmulh", "s", int_arm_neon_vqdmulh>;
4146 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
4147 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4149 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
4150 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4151 (DSubReg_i16_reg imm:$lane))),
4152 (SubReg_i16_lane imm:$lane)))>;
4153 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
4154 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4156 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
4157 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4158 (DSubReg_i32_reg imm:$lane))),
4159 (SubReg_i32_lane imm:$lane)))>;
4161 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
4162 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
4163 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
4164 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
4165 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
4166 IIC_VMULi16Q, IIC_VMULi32Q,
4167 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
4168 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
4169 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
4171 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
4172 (v4i16 (EXTRACT_SUBREG QPR:$src2,
4173 (DSubReg_i16_reg imm:$lane))),
4174 (SubReg_i16_lane imm:$lane)))>;
4175 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
4176 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
4178 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
4179 (v2i32 (EXTRACT_SUBREG QPR:$src2,
4180 (DSubReg_i32_reg imm:$lane))),
4181 (SubReg_i32_lane imm:$lane)))>;
4183 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
4184 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
4185 DecoderNamespace = "NEONData" in {
4186 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4187 "vmull", "s", NEONvmulls, 1>;
4188 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
4189 "vmull", "u", NEONvmullu, 1>;
4190 def VMULLp8 : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
4191 v8i16, v8i8, int_arm_neon_vmullp, 1>;
4192 def VMULLp64 : N3VLIntnp<0b00101, 0b10, 0b1110, 0, 0, NoItinerary,
4193 "vmull", "p64", v2i64, v1i64, int_arm_neon_vmullp, 1>,
4194 Requires<[HasV8, HasCrypto]>;
4196 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
4197 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
4199 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
4200 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
4201 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
4202 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
4203 "vqdmull", "s", int_arm_neon_vqdmull>;
4205 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
4207 // VMLA : Vector Multiply Accumulate (integer and floating-point)
4208 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4209 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4210 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
4211 v2f32, fmul_su, fadd_mlx>,
4212 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4213 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
4214 v4f32, fmul_su, fadd_mlx>,
4215 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4216 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
4217 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
4218 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
4219 v2f32, fmul_su, fadd_mlx>,
4220 Requires<[HasNEON, UseFPVMLx]>;
4221 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
4222 v4f32, v2f32, fmul_su, fadd_mlx>,
4223 Requires<[HasNEON, UseFPVMLx]>;
4225 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
4226 (mul (v8i16 QPR:$src2),
4227 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4228 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4229 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4230 (DSubReg_i16_reg imm:$lane))),
4231 (SubReg_i16_lane imm:$lane)))>;
4233 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
4234 (mul (v4i32 QPR:$src2),
4235 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4236 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4237 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4238 (DSubReg_i32_reg imm:$lane))),
4239 (SubReg_i32_lane imm:$lane)))>;
4241 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
4242 (fmul_su (v4f32 QPR:$src2),
4243 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4244 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
4246 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4247 (DSubReg_i32_reg imm:$lane))),
4248 (SubReg_i32_lane imm:$lane)))>,
4249 Requires<[HasNEON, UseFPVMLx]>;
4251 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
4252 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4253 "vmlal", "s", NEONvmulls, add>;
4254 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
4255 "vmlal", "u", NEONvmullu, add>;
4257 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
4258 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
4260 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
4261 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4262 "vqdmlal", "s", null_frag>;
4263 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", null_frag>;
4265 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4266 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4267 (v4i16 DPR:$Vm))))),
4268 (VQDMLALv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4269 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4270 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4271 (v2i32 DPR:$Vm))))),
4272 (VQDMLALv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4273 def : Pat<(v4i32 (int_arm_neon_vqadds (v4i32 QPR:$src1),
4274 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4275 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4277 (VQDMLALslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4278 def : Pat<(v2i64 (int_arm_neon_vqadds (v2i64 QPR:$src1),
4279 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4280 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4282 (VQDMLALslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4284 // VMLS : Vector Multiply Subtract (integer and floating-point)
4285 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
4286 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4287 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
4288 v2f32, fmul_su, fsub_mlx>,
4289 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4290 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
4291 v4f32, fmul_su, fsub_mlx>,
4292 Requires<[HasNEON, UseFPVMLx, DontUseFusedMAC]>;
4293 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
4294 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
4295 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
4296 v2f32, fmul_su, fsub_mlx>,
4297 Requires<[HasNEON, UseFPVMLx]>;
4298 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
4299 v4f32, v2f32, fmul_su, fsub_mlx>,
4300 Requires<[HasNEON, UseFPVMLx]>;
4302 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
4303 (mul (v8i16 QPR:$src2),
4304 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
4305 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
4306 (v4i16 (EXTRACT_SUBREG QPR:$src3,
4307 (DSubReg_i16_reg imm:$lane))),
4308 (SubReg_i16_lane imm:$lane)))>;
4310 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
4311 (mul (v4i32 QPR:$src2),
4312 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
4313 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
4314 (v2i32 (EXTRACT_SUBREG QPR:$src3,
4315 (DSubReg_i32_reg imm:$lane))),
4316 (SubReg_i32_lane imm:$lane)))>;
4318 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
4319 (fmul_su (v4f32 QPR:$src2),
4320 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
4321 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
4322 (v2f32 (EXTRACT_SUBREG QPR:$src3,
4323 (DSubReg_i32_reg imm:$lane))),
4324 (SubReg_i32_lane imm:$lane)))>,
4325 Requires<[HasNEON, UseFPVMLx]>;
4327 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
4328 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4329 "vmlsl", "s", NEONvmulls, sub>;
4330 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
4331 "vmlsl", "u", NEONvmullu, sub>;
4333 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
4334 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
4336 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
4337 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
4338 "vqdmlsl", "s", null_frag>;
4339 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", null_frag>;
4341 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4342 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4343 (v4i16 DPR:$Vm))))),
4344 (VQDMLSLv4i32 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4345 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4346 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4347 (v2i32 DPR:$Vm))))),
4348 (VQDMLSLv2i64 QPR:$src1, DPR:$Vn, DPR:$Vm)>;
4349 def : Pat<(v4i32 (int_arm_neon_vqsubs (v4i32 QPR:$src1),
4350 (v4i32 (int_arm_neon_vqdmull (v4i16 DPR:$Vn),
4351 (v4i16 (NEONvduplane (v4i16 DPR_8:$Vm),
4353 (VQDMLSLslv4i16 QPR:$src1, DPR:$Vn, DPR_8:$Vm, imm:$lane)>;
4354 def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
4355 (v2i64 (int_arm_neon_vqdmull (v2i32 DPR:$Vn),
4356 (v2i32 (NEONvduplane (v2i32 DPR_VFP2:$Vm),
4358 (VQDMLSLslv2i32 QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, imm:$lane)>;
4360 // Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
4361 def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
4362 v2f32, fmul_su, fadd_mlx>,
4363 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4365 def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
4366 v4f32, fmul_su, fadd_mlx>,
4367 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4369 // Fused Vector Multiply Subtract (floating-point)
4370 def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
4371 v2f32, fmul_su, fsub_mlx>,
4372 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4373 def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
4374 v4f32, fmul_su, fsub_mlx>,
4375 Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
4377 // Match @llvm.fma.* intrinsics
4378 def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
4379 (VFMAfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4380 Requires<[HasVFP4]>;
4381 def : Pat<(v4f32 (fma QPR:$Vn, QPR:$Vm, QPR:$src1)),
4382 (VFMAfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4383 Requires<[HasVFP4]>;
4384 def : Pat<(v2f32 (fma (fneg DPR:$Vn), DPR:$Vm, DPR:$src1)),
4385 (VFMSfd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4386 Requires<[HasVFP4]>;
4387 def : Pat<(v4f32 (fma (fneg QPR:$Vn), QPR:$Vm, QPR:$src1)),
4388 (VFMSfq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4389 Requires<[HasVFP4]>;
4391 // Vector Subtract Operations.
4393 // VSUB : Vector Subtract (integer and floating-point)
4394 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
4395 "vsub", "i", sub, 0>;
4396 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
4397 v2f32, v2f32, fsub, 0>;
4398 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
4399 v4f32, v4f32, fsub, 0>;
4400 // VSUBL : Vector Subtract Long (Q = D - D)
4401 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4402 "vsubl", "s", sub, sext, 0>;
4403 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
4404 "vsubl", "u", sub, zext, 0>;
4405 // VSUBW : Vector Subtract Wide (Q = Q - D)
4406 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
4407 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
4408 // VHSUB : Vector Halving Subtract
4409 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
4410 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4411 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4412 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
4413 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4414 "vhsub", "u", int_arm_neon_vhsubu, 0>;
4415 // VQSUB : Vector Saturing Subtract
4416 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
4417 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4418 "vqsub", "s", int_arm_neon_vqsubs, 0>;
4419 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
4420 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4421 "vqsub", "u", int_arm_neon_vqsubu, 0>;
4422 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
4423 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i", null_frag, 0>;
4424 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
4425 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
4426 int_arm_neon_vrsubhn, 0>;
4428 def : Pat<(v8i8 (trunc (NEONvshru (sub (v8i16 QPR:$Vn), QPR:$Vm), 8))),
4429 (VSUBHNv8i8 QPR:$Vn, QPR:$Vm)>;
4430 def : Pat<(v4i16 (trunc (NEONvshru (sub (v4i32 QPR:$Vn), QPR:$Vm), 16))),
4431 (VSUBHNv4i16 QPR:$Vn, QPR:$Vm)>;
4432 def : Pat<(v2i32 (trunc (NEONvshru (sub (v2i64 QPR:$Vn), QPR:$Vm), 32))),
4433 (VSUBHNv2i32 QPR:$Vn, QPR:$Vm)>;
4435 // Vector Comparisons.
4437 // VCEQ : Vector Compare Equal
4438 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4439 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
4440 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
4442 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
4445 let TwoOperandAliasConstraint = "$Vm = $Vd" in
4446 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
4447 "$Vd, $Vm, #0", NEONvceqz>;
4449 // VCGE : Vector Compare Greater Than or Equal
4450 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4451 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4452 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4453 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4454 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4456 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4459 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4460 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4461 "$Vd, $Vm, #0", NEONvcgez>;
4462 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4463 "$Vd, $Vm, #0", NEONvclez>;
4466 // VCGT : Vector Compare Greater Than
4467 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4468 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4469 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4470 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4471 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4473 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4476 let TwoOperandAliasConstraint = "$Vm = $Vd" in {
4477 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4478 "$Vd, $Vm, #0", NEONvcgtz>;
4479 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4480 "$Vd, $Vm, #0", NEONvcltz>;
4483 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4484 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4485 "f32", v2i32, v2f32, int_arm_neon_vacge, 0>;
4486 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4487 "f32", v4i32, v4f32, int_arm_neon_vacge, 0>;
4488 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4489 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4490 "f32", v2i32, v2f32, int_arm_neon_vacgt, 0>;
4491 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4492 "f32", v4i32, v4f32, int_arm_neon_vacgt, 0>;
4493 // VTST : Vector Test Bits
4494 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4495 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4497 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4498 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4499 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vn, $Vm",
4500 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4501 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4502 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vn, pred:$p)>;
4503 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vn, $Vm",
4504 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vn, pred:$p)>;
4506 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4507 (VACGTd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4508 def: NEONInstAlias<"vaclt${p}.f32 $Vd, $Vm",
4509 (VACGTq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4510 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4511 (VACGEd DPR:$Vd, DPR:$Vm, DPR:$Vd, pred:$p)>;
4512 def: NEONInstAlias<"vacle${p}.f32 $Vd, $Vm",
4513 (VACGEq QPR:$Vd, QPR:$Vm, QPR:$Vd, pred:$p)>;
4515 // Vector Bitwise Operations.
4517 def vnotd : PatFrag<(ops node:$in),
4518 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4519 def vnotq : PatFrag<(ops node:$in),
4520 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4523 // VAND : Vector Bitwise AND
4524 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4525 v2i32, v2i32, and, 1>;
4526 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4527 v4i32, v4i32, and, 1>;
4529 // VEOR : Vector Bitwise Exclusive OR
4530 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4531 v2i32, v2i32, xor, 1>;
4532 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4533 v4i32, v4i32, xor, 1>;
4535 // VORR : Vector Bitwise OR
4536 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4537 v2i32, v2i32, or, 1>;
4538 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4539 v4i32, v4i32, or, 1>;
4541 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4542 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4544 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4546 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4547 let Inst{9} = SIMM{9};
4550 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4551 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4553 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4555 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4556 let Inst{10-9} = SIMM{10-9};
4559 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4560 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4562 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4564 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4565 let Inst{9} = SIMM{9};
4568 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4569 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4571 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4573 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4574 let Inst{10-9} = SIMM{10-9};
4578 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4579 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
4580 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4581 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4582 "vbic", "$Vd, $Vn, $Vm", "",
4583 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4584 (vnotd DPR:$Vm))))]>;
4585 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4586 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4587 "vbic", "$Vd, $Vn, $Vm", "",
4588 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4589 (vnotq QPR:$Vm))))]>;
4592 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4593 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4595 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4597 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4598 let Inst{9} = SIMM{9};
4601 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4602 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4604 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4606 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4607 let Inst{10-9} = SIMM{10-9};
4610 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4611 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4613 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4615 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4616 let Inst{9} = SIMM{9};
4619 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4620 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4622 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4624 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4625 let Inst{10-9} = SIMM{10-9};
4628 // VORN : Vector Bitwise OR NOT
4629 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4630 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4631 "vorn", "$Vd, $Vn, $Vm", "",
4632 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4633 (vnotd DPR:$Vm))))]>;
4634 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4635 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4636 "vorn", "$Vd, $Vn, $Vm", "",
4637 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4638 (vnotq QPR:$Vm))))]>;
4640 // VMVN : Vector Bitwise NOT (Immediate)
4642 let isReMaterializable = 1 in {
4644 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4645 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4646 "vmvn", "i16", "$Vd, $SIMM", "",
4647 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4648 let Inst{9} = SIMM{9};
4651 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4652 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4653 "vmvn", "i16", "$Vd, $SIMM", "",
4654 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4655 let Inst{9} = SIMM{9};
4658 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4659 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4660 "vmvn", "i32", "$Vd, $SIMM", "",
4661 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4662 let Inst{11-8} = SIMM{11-8};
4665 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4666 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4667 "vmvn", "i32", "$Vd, $SIMM", "",
4668 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4669 let Inst{11-8} = SIMM{11-8};
4673 // VMVN : Vector Bitwise NOT
4674 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4675 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4676 "vmvn", "$Vd, $Vm", "",
4677 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4678 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4679 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4680 "vmvn", "$Vd, $Vm", "",
4681 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4682 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4683 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4685 // VBSL : Vector Bitwise Select
4686 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4687 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4688 N3RegFrm, IIC_VCNTiD,
4689 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4691 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4692 def : Pat<(v8i8 (int_arm_neon_vbsl (v8i8 DPR:$src1),
4693 (v8i8 DPR:$Vn), (v8i8 DPR:$Vm))),
4694 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4695 Requires<[HasNEON]>;
4696 def : Pat<(v4i16 (int_arm_neon_vbsl (v4i16 DPR:$src1),
4697 (v4i16 DPR:$Vn), (v4i16 DPR:$Vm))),
4698 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4699 Requires<[HasNEON]>;
4700 def : Pat<(v2i32 (int_arm_neon_vbsl (v2i32 DPR:$src1),
4701 (v2i32 DPR:$Vn), (v2i32 DPR:$Vm))),
4702 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4703 Requires<[HasNEON]>;
4704 def : Pat<(v2f32 (int_arm_neon_vbsl (v2f32 DPR:$src1),
4705 (v2f32 DPR:$Vn), (v2f32 DPR:$Vm))),
4706 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4707 Requires<[HasNEON]>;
4708 def : Pat<(v1i64 (int_arm_neon_vbsl (v1i64 DPR:$src1),
4709 (v1i64 DPR:$Vn), (v1i64 DPR:$Vm))),
4710 (VBSLd DPR:$src1, DPR:$Vn, DPR:$Vm)>,
4711 Requires<[HasNEON]>;
4713 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4714 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4715 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4716 Requires<[HasNEON]>;
4718 def : Pat<(v1i64 (or (and DPR:$Vn, DPR:$Vd),
4719 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4720 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>,
4721 Requires<[HasNEON]>;
4723 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4724 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4725 N3RegFrm, IIC_VCNTiQ,
4726 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4728 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4730 def : Pat<(v16i8 (int_arm_neon_vbsl (v16i8 QPR:$src1),
4731 (v16i8 QPR:$Vn), (v16i8 QPR:$Vm))),
4732 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4733 Requires<[HasNEON]>;
4734 def : Pat<(v8i16 (int_arm_neon_vbsl (v8i16 QPR:$src1),
4735 (v8i16 QPR:$Vn), (v8i16 QPR:$Vm))),
4736 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4737 Requires<[HasNEON]>;
4738 def : Pat<(v4i32 (int_arm_neon_vbsl (v4i32 QPR:$src1),
4739 (v4i32 QPR:$Vn), (v4i32 QPR:$Vm))),
4740 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4741 Requires<[HasNEON]>;
4742 def : Pat<(v4f32 (int_arm_neon_vbsl (v4f32 QPR:$src1),
4743 (v4f32 QPR:$Vn), (v4f32 QPR:$Vm))),
4744 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4745 Requires<[HasNEON]>;
4746 def : Pat<(v2i64 (int_arm_neon_vbsl (v2i64 QPR:$src1),
4747 (v2i64 QPR:$Vn), (v2i64 QPR:$Vm))),
4748 (VBSLq QPR:$src1, QPR:$Vn, QPR:$Vm)>,
4749 Requires<[HasNEON]>;
4751 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4752 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4753 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4754 Requires<[HasNEON]>;
4755 def : Pat<(v2i64 (or (and QPR:$Vn, QPR:$Vd),
4756 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4757 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>,
4758 Requires<[HasNEON]>;
4760 // VBIF : Vector Bitwise Insert if False
4761 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4762 // FIXME: This instruction's encoding MAY NOT BE correct.
4763 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4764 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4765 N3RegFrm, IIC_VBINiD,
4766 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4768 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4769 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4770 N3RegFrm, IIC_VBINiQ,
4771 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4774 // VBIT : Vector Bitwise Insert if True
4775 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4776 // FIXME: This instruction's encoding MAY NOT BE correct.
4777 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4778 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4779 N3RegFrm, IIC_VBINiD,
4780 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4782 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4783 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4784 N3RegFrm, IIC_VBINiQ,
4785 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4788 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4789 // for equivalent operations with different register constraints; it just
4792 // Vector Absolute Differences.
4794 // VABD : Vector Absolute Difference
4795 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4796 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4797 "vabd", "s", int_arm_neon_vabds, 1>;
4798 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4799 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4800 "vabd", "u", int_arm_neon_vabdu, 1>;
4801 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4802 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4803 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4804 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4806 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4807 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4808 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4809 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4810 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4812 // VABA : Vector Absolute Difference and Accumulate
4813 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4814 "vaba", "s", int_arm_neon_vabds, add>;
4815 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4816 "vaba", "u", int_arm_neon_vabdu, add>;
4818 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4819 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4820 "vabal", "s", int_arm_neon_vabds, zext, add>;
4821 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4822 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4824 // Vector Maximum and Minimum.
4826 // VMAX : Vector Maximum
4827 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4828 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4829 "vmax", "s", int_arm_neon_vmaxs, 1>;
4830 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4831 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4832 "vmax", "u", int_arm_neon_vmaxu, 1>;
4833 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4835 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4836 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4838 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4841 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4842 def VMAXNMND : N3VDIntnp<0b00110, 0b00, 0b1111, 0, 1,
4843 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4844 v2f32, v2f32, int_arm_neon_vmaxnm, 1>,
4845 Requires<[HasV8, HasNEON]>;
4846 def VMAXNMNQ : N3VQIntnp<0b00110, 0b00, 0b1111, 1, 1,
4847 N3RegFrm, NoItinerary, "vmaxnm", "f32",
4848 v4f32, v4f32, int_arm_neon_vmaxnm, 1>,
4849 Requires<[HasV8, HasNEON]>;
4852 // VMIN : Vector Minimum
4853 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4854 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4855 "vmin", "s", int_arm_neon_vmins, 1>;
4856 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4857 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4858 "vmin", "u", int_arm_neon_vminu, 1>;
4859 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4861 v2f32, v2f32, int_arm_neon_vmins, 1>;
4862 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4864 v4f32, v4f32, int_arm_neon_vmins, 1>;
4867 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
4868 def VMINNMND : N3VDIntnp<0b00110, 0b10, 0b1111, 0, 1,
4869 N3RegFrm, NoItinerary, "vminnm", "f32",
4870 v2f32, v2f32, int_arm_neon_vminnm, 1>,
4871 Requires<[HasV8, HasNEON]>;
4872 def VMINNMNQ : N3VQIntnp<0b00110, 0b10, 0b1111, 1, 1,
4873 N3RegFrm, NoItinerary, "vminnm", "f32",
4874 v4f32, v4f32, int_arm_neon_vminnm, 1>,
4875 Requires<[HasV8, HasNEON]>;
4878 // Vector Pairwise Operations.
4880 // VPADD : Vector Pairwise Add
4881 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4883 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4884 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4886 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4887 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4889 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4890 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4891 IIC_VPBIND, "vpadd", "f32",
4892 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4894 // VPADDL : Vector Pairwise Add Long
4895 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4896 int_arm_neon_vpaddls>;
4897 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4898 int_arm_neon_vpaddlu>;
4900 // VPADAL : Vector Pairwise Add and Accumulate Long
4901 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4902 int_arm_neon_vpadals>;
4903 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4904 int_arm_neon_vpadalu>;
4906 // VPMAX : Vector Pairwise Maximum
4907 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4908 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4909 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4910 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4911 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4912 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4913 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4914 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4915 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4916 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4917 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4918 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4919 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4920 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4922 // VPMIN : Vector Pairwise Minimum
4923 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4924 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4925 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4926 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4927 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4928 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4929 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4930 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4931 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4932 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4933 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4934 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4935 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4936 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4938 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4940 // VRECPE : Vector Reciprocal Estimate
4941 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4942 IIC_VUNAD, "vrecpe", "u32",
4943 v2i32, v2i32, int_arm_neon_vrecpe>;
4944 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4945 IIC_VUNAQ, "vrecpe", "u32",
4946 v4i32, v4i32, int_arm_neon_vrecpe>;
4947 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4948 IIC_VUNAD, "vrecpe", "f32",
4949 v2f32, v2f32, int_arm_neon_vrecpe>;
4950 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4951 IIC_VUNAQ, "vrecpe", "f32",
4952 v4f32, v4f32, int_arm_neon_vrecpe>;
4954 // VRECPS : Vector Reciprocal Step
4955 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4956 IIC_VRECSD, "vrecps", "f32",
4957 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4958 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4959 IIC_VRECSQ, "vrecps", "f32",
4960 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4962 // VRSQRTE : Vector Reciprocal Square Root Estimate
4963 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4964 IIC_VUNAD, "vrsqrte", "u32",
4965 v2i32, v2i32, int_arm_neon_vrsqrte>;
4966 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4967 IIC_VUNAQ, "vrsqrte", "u32",
4968 v4i32, v4i32, int_arm_neon_vrsqrte>;
4969 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4970 IIC_VUNAD, "vrsqrte", "f32",
4971 v2f32, v2f32, int_arm_neon_vrsqrte>;
4972 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4973 IIC_VUNAQ, "vrsqrte", "f32",
4974 v4f32, v4f32, int_arm_neon_vrsqrte>;
4976 // VRSQRTS : Vector Reciprocal Square Root Step
4977 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4978 IIC_VRECSD, "vrsqrts", "f32",
4979 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4980 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4981 IIC_VRECSQ, "vrsqrts", "f32",
4982 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4986 // VSHL : Vector Shift
4987 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4988 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4989 "vshl", "s", int_arm_neon_vshifts>;
4990 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4991 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4992 "vshl", "u", int_arm_neon_vshiftu>;
4994 // VSHL : Vector Shift Left (Immediate)
4995 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4997 // VSHR : Vector Shift Right (Immediate)
4998 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s", "VSHRs",
5000 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u", "VSHRu",
5003 // VSHLL : Vector Shift Left Long
5004 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s",
5005 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (sext node:$LHS), node:$RHS)>>;
5006 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u",
5007 PatFrag<(ops node:$LHS, node:$RHS), (NEONvshl (zext node:$LHS), node:$RHS)>>;
5009 // VSHLL : Vector Shift Left Long (with maximum shift count)
5010 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
5011 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
5012 ValueType OpTy, Operand ImmTy>
5013 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
5014 ResTy, OpTy, ImmTy, null_frag> {
5015 let Inst{21-16} = op21_16;
5016 let DecoderMethod = "DecodeVSHLMaxInstruction";
5018 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
5020 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
5021 v4i32, v4i16, imm16>;
5022 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
5023 v2i64, v2i32, imm32>;
5025 def : Pat<(v8i16 (NEONvshl (zext (v8i8 DPR:$Rn)), (i32 8))),
5026 (VSHLLi8 DPR:$Rn, 8)>;
5027 def : Pat<(v4i32 (NEONvshl (zext (v4i16 DPR:$Rn)), (i32 16))),
5028 (VSHLLi16 DPR:$Rn, 16)>;
5029 def : Pat<(v2i64 (NEONvshl (zext (v2i32 DPR:$Rn)), (i32 32))),
5030 (VSHLLi32 DPR:$Rn, 32)>;
5031 def : Pat<(v8i16 (NEONvshl (sext (v8i8 DPR:$Rn)), (i32 8))),
5032 (VSHLLi8 DPR:$Rn, 8)>;
5033 def : Pat<(v4i32 (NEONvshl (sext (v4i16 DPR:$Rn)), (i32 16))),
5034 (VSHLLi16 DPR:$Rn, 16)>;
5035 def : Pat<(v2i64 (NEONvshl (sext (v2i32 DPR:$Rn)), (i32 32))),
5036 (VSHLLi32 DPR:$Rn, 32)>;
5038 // VSHRN : Vector Shift Right and Narrow
5039 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
5040 PatFrag<(ops node:$Rn, node:$amt),
5041 (trunc (NEONvshrs node:$Rn, node:$amt))>>;
5043 def : Pat<(v8i8 (trunc (NEONvshru (v8i16 QPR:$Vn), shr_imm8:$amt))),
5044 (VSHRNv8i8 QPR:$Vn, shr_imm8:$amt)>;
5045 def : Pat<(v4i16 (trunc (NEONvshru (v4i32 QPR:$Vn), shr_imm16:$amt))),
5046 (VSHRNv4i16 QPR:$Vn, shr_imm16:$amt)>;
5047 def : Pat<(v2i32 (trunc (NEONvshru (v2i64 QPR:$Vn), shr_imm32:$amt))),
5048 (VSHRNv2i32 QPR:$Vn, shr_imm32:$amt)>;
5050 // VRSHL : Vector Rounding Shift
5051 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
5052 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5053 "vrshl", "s", int_arm_neon_vrshifts>;
5054 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
5055 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5056 "vrshl", "u", int_arm_neon_vrshiftu>;
5057 // VRSHR : Vector Rounding Shift Right
5058 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s", "VRSHRs",
5060 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u", "VRSHRu",
5063 // VRSHRN : Vector Rounding Shift Right and Narrow
5064 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
5067 // VQSHL : Vector Saturating Shift
5068 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
5069 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5070 "vqshl", "s", int_arm_neon_vqshifts>;
5071 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
5072 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5073 "vqshl", "u", int_arm_neon_vqshiftu>;
5074 // VQSHL : Vector Saturating Shift Left (Immediate)
5075 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
5076 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
5078 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
5079 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
5081 // VQSHRN : Vector Saturating Shift Right and Narrow
5082 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
5084 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
5087 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
5088 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
5091 // VQRSHL : Vector Saturating Rounding Shift
5092 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
5093 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5094 "vqrshl", "s", int_arm_neon_vqrshifts>;
5095 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
5096 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
5097 "vqrshl", "u", int_arm_neon_vqrshiftu>;
5099 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
5100 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
5102 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
5105 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
5106 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
5109 // VSRA : Vector Shift Right and Accumulate
5110 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
5111 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
5112 // VRSRA : Vector Rounding Shift Right and Accumulate
5113 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
5114 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
5116 // VSLI : Vector Shift Left and Insert
5117 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
5119 // VSRI : Vector Shift Right and Insert
5120 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
5122 // Vector Absolute and Saturating Absolute.
5124 // VABS : Vector Absolute Value
5125 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
5126 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
5128 def VABSfd : N2VD<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5130 v2f32, v2f32, fabs>;
5131 def VABSfq : N2VQ<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
5133 v4f32, v4f32, fabs>;
5135 def : Pat<(xor (v2i32 (bitconvert (v8i8 (NEONvshrs DPR:$src, (i32 7))))),
5136 (v2i32 (bitconvert (v8i8 (add DPR:$src,
5137 (NEONvshrs DPR:$src, (i32 7))))))),
5138 (VABSv8i8 DPR:$src)>;
5139 def : Pat<(xor (v2i32 (bitconvert (v4i16 (NEONvshrs DPR:$src, (i32 15))))),
5140 (v2i32 (bitconvert (v4i16 (add DPR:$src,
5141 (NEONvshrs DPR:$src, (i32 15))))))),
5142 (VABSv4i16 DPR:$src)>;
5143 def : Pat<(xor (v2i32 (NEONvshrs DPR:$src, (i32 31))),
5144 (v2i32 (add DPR:$src, (NEONvshrs DPR:$src, (i32 31))))),
5145 (VABSv2i32 DPR:$src)>;
5146 def : Pat<(xor (v4i32 (bitconvert (v16i8 (NEONvshrs QPR:$src, (i32 7))))),
5147 (v4i32 (bitconvert (v16i8 (add QPR:$src,
5148 (NEONvshrs QPR:$src, (i32 7))))))),
5149 (VABSv16i8 QPR:$src)>;
5150 def : Pat<(xor (v4i32 (bitconvert (v8i16 (NEONvshrs QPR:$src, (i32 15))))),
5151 (v4i32 (bitconvert (v8i16 (add QPR:$src,
5152 (NEONvshrs QPR:$src, (i32 15))))))),
5153 (VABSv8i16 QPR:$src)>;
5154 def : Pat<(xor (v4i32 (NEONvshrs QPR:$src, (i32 31))),
5155 (v4i32 (add QPR:$src, (NEONvshrs QPR:$src, (i32 31))))),
5156 (VABSv4i32 QPR:$src)>;
5158 // VQABS : Vector Saturating Absolute Value
5159 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
5160 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
5161 int_arm_neon_vqabs>;
5165 def vnegd : PatFrag<(ops node:$in),
5166 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
5167 def vnegq : PatFrag<(ops node:$in),
5168 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
5170 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5171 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
5172 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
5173 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
5174 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
5175 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
5176 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
5177 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
5179 // VNEG : Vector Negate (integer)
5180 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
5181 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
5182 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
5183 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
5184 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
5185 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
5187 // VNEG : Vector Negate (floating-point)
5188 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
5189 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
5190 "vneg", "f32", "$Vd, $Vm", "",
5191 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
5192 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
5193 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
5194 "vneg", "f32", "$Vd, $Vm", "",
5195 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
5197 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
5198 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
5199 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
5200 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
5201 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
5202 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
5204 // VQNEG : Vector Saturating Negate
5205 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
5206 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
5207 int_arm_neon_vqneg>;
5209 // Vector Bit Counting Operations.
5211 // VCLS : Vector Count Leading Sign Bits
5212 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
5213 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
5215 // VCLZ : Vector Count Leading Zeros
5216 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
5217 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
5219 // VCNT : Vector Count One Bits
5220 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5221 IIC_VCNTiD, "vcnt", "8",
5223 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
5224 IIC_VCNTiQ, "vcnt", "8",
5225 v16i8, v16i8, ctpop>;
5228 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
5229 (outs DPR:$Vd, DPR:$Vm), (ins DPR:$in1, DPR:$in2),
5230 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5232 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
5233 (outs QPR:$Vd, QPR:$Vm), (ins QPR:$in1, QPR:$in2),
5234 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5237 // Vector Move Operations.
5239 // VMOV : Vector Move (Register)
5240 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5241 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5242 def : NEONInstAlias<"vmov${p} $Vd, $Vm",
5243 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5245 // VMOV : Vector Move (Immediate)
5247 let isReMaterializable = 1 in {
5248 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
5249 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5250 "vmov", "i8", "$Vd, $SIMM", "",
5251 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
5252 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
5253 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
5254 "vmov", "i8", "$Vd, $SIMM", "",
5255 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
5257 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
5258 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5259 "vmov", "i16", "$Vd, $SIMM", "",
5260 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
5261 let Inst{9} = SIMM{9};
5264 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
5265 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
5266 "vmov", "i16", "$Vd, $SIMM", "",
5267 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
5268 let Inst{9} = SIMM{9};
5271 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
5272 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5273 "vmov", "i32", "$Vd, $SIMM", "",
5274 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
5275 let Inst{11-8} = SIMM{11-8};
5278 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
5279 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
5280 "vmov", "i32", "$Vd, $SIMM", "",
5281 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
5282 let Inst{11-8} = SIMM{11-8};
5285 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
5286 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5287 "vmov", "i64", "$Vd, $SIMM", "",
5288 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
5289 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
5290 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
5291 "vmov", "i64", "$Vd, $SIMM", "",
5292 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
5294 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
5295 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5296 "vmov", "f32", "$Vd, $SIMM", "",
5297 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
5298 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
5299 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
5300 "vmov", "f32", "$Vd, $SIMM", "",
5301 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
5302 } // isReMaterializable
5305 // On some CPUs the two instructions "vmov.i32 dD, #0" and "vmov.i32 qD, #0"
5306 // require zero cycles to execute so they should be used wherever possible for
5307 // setting a register to zero.
5309 // Even without these pseudo-insts we would probably end up with the correct
5310 // instruction, but we could not mark the general ones with "isAsCheapAsAMove"
5311 // since they are sometimes rather expensive (in general).
5313 let AddedComplexity = 50, isAsCheapAsAMove = 1, isReMaterializable = 1 in {
5314 def VMOVD0 : ARMPseudoExpand<(outs DPR:$Vd), (ins), 4, IIC_VMOVImm,
5315 [(set DPR:$Vd, (v2i32 NEONimmAllZerosV))],
5316 (VMOVv2i32 DPR:$Vd, 0, (ops 14, zero_reg))>,
5318 def VMOVQ0 : ARMPseudoExpand<(outs QPR:$Vd), (ins), 4, IIC_VMOVImm,
5319 [(set QPR:$Vd, (v4i32 NEONimmAllZerosV))],
5320 (VMOVv4i32 QPR:$Vd, 0, (ops 14, zero_reg))>,
5324 // VMOV : Vector Get Lane (move scalar to ARM core register)
5326 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
5327 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5328 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
5329 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
5331 let Inst{21} = lane{2};
5332 let Inst{6-5} = lane{1-0};
5334 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
5335 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5336 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
5337 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
5339 let Inst{21} = lane{1};
5340 let Inst{6} = lane{0};
5342 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
5343 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
5344 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
5345 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
5347 let Inst{21} = lane{2};
5348 let Inst{6-5} = lane{1-0};
5350 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
5351 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
5352 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
5353 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
5355 let Inst{21} = lane{1};
5356 let Inst{6} = lane{0};
5358 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
5359 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
5360 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
5361 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
5363 Requires<[HasNEON, HasFastVGETLNi32]> {
5364 let Inst{21} = lane{0};
5366 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
5367 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
5368 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5369 (DSubReg_i8_reg imm:$lane))),
5370 (SubReg_i8_lane imm:$lane))>;
5371 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
5372 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5373 (DSubReg_i16_reg imm:$lane))),
5374 (SubReg_i16_lane imm:$lane))>;
5375 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
5376 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
5377 (DSubReg_i8_reg imm:$lane))),
5378 (SubReg_i8_lane imm:$lane))>;
5379 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
5380 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
5381 (DSubReg_i16_reg imm:$lane))),
5382 (SubReg_i16_lane imm:$lane))>;
5383 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5384 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
5385 (DSubReg_i32_reg imm:$lane))),
5386 (SubReg_i32_lane imm:$lane))>,
5387 Requires<[HasNEON, HasFastVGETLNi32]>;
5388 def : Pat<(extractelt (v2i32 DPR:$src), imm:$lane),
5390 (i32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5391 Requires<[HasNEON, HasSlowVGETLNi32]>;
5392 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
5394 (i32 (EXTRACT_SUBREG QPR:$src, (SSubReg_f32_reg imm:$lane))), GPR)>,
5395 Requires<[HasNEON, HasSlowVGETLNi32]>;
5396 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
5397 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
5398 (SSubReg_f32_reg imm:$src2))>;
5399 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
5400 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
5401 (SSubReg_f32_reg imm:$src2))>;
5402 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
5403 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5404 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
5405 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
5408 // VMOV : Vector Set Lane (move ARM core register to scalar)
5410 let Constraints = "$src1 = $V" in {
5411 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
5412 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
5413 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
5414 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
5415 GPR:$R, imm:$lane))]> {
5416 let Inst{21} = lane{2};
5417 let Inst{6-5} = lane{1-0};
5419 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
5420 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
5421 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
5422 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
5423 GPR:$R, imm:$lane))]> {
5424 let Inst{21} = lane{1};
5425 let Inst{6} = lane{0};
5427 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
5428 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
5429 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
5430 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
5431 GPR:$R, imm:$lane))]> {
5432 let Inst{21} = lane{0};
5435 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
5436 (v16i8 (INSERT_SUBREG QPR:$src1,
5437 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
5438 (DSubReg_i8_reg imm:$lane))),
5439 GPR:$src2, (SubReg_i8_lane imm:$lane))),
5440 (DSubReg_i8_reg imm:$lane)))>;
5441 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
5442 (v8i16 (INSERT_SUBREG QPR:$src1,
5443 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
5444 (DSubReg_i16_reg imm:$lane))),
5445 GPR:$src2, (SubReg_i16_lane imm:$lane))),
5446 (DSubReg_i16_reg imm:$lane)))>;
5447 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
5448 (v4i32 (INSERT_SUBREG QPR:$src1,
5449 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
5450 (DSubReg_i32_reg imm:$lane))),
5451 GPR:$src2, (SubReg_i32_lane imm:$lane))),
5452 (DSubReg_i32_reg imm:$lane)))>;
5454 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
5455 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
5456 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5457 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
5458 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
5459 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
5461 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5462 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5463 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
5464 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
5466 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
5467 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5468 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
5469 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5470 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
5471 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5473 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
5474 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5475 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
5476 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5477 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
5478 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5480 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
5481 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5482 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5484 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
5485 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
5486 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5488 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
5489 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
5490 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
5493 // VDUP : Vector Duplicate (from ARM core register to all elements)
5495 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5496 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
5497 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5498 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5499 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
5500 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
5501 IIC_VMOVIS, "vdup", Dt, "$V, $R",
5502 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
5504 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
5505 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
5506 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>,
5507 Requires<[HasNEON, HasFastVDUP32]>;
5508 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
5509 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
5510 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
5512 // NEONvdup patterns for uarchs with fast VDUP.32.
5513 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>,
5514 Requires<[HasNEON,HasFastVDUP32]>;
5515 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
5517 // NEONvdup patterns for uarchs with slow VDUP.32 - use VMOVDRR instead.
5518 def : Pat<(v2i32 (NEONvdup (i32 GPR:$R))), (VMOVDRR GPR:$R, GPR:$R)>,
5519 Requires<[HasNEON,HasSlowVDUP32]>;
5520 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VMOVDRR GPR:$R, GPR:$R)>,
5521 Requires<[HasNEON,HasSlowVDUP32]>;
5523 // VDUP : Vector Duplicate Lane (from scalar to all elements)
5525 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
5526 ValueType Ty, Operand IdxTy>
5527 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5528 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
5529 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
5531 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
5532 ValueType ResTy, ValueType OpTy, Operand IdxTy>
5533 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
5534 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
5535 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
5536 VectorIndex32:$lane)))]>;
5538 // Inst{19-16} is partially specified depending on the element size.
5540 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
5542 let Inst{19-17} = lane{2-0};
5544 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
5546 let Inst{19-18} = lane{1-0};
5548 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
5550 let Inst{19} = lane{0};
5552 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
5554 let Inst{19-17} = lane{2-0};
5556 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
5558 let Inst{19-18} = lane{1-0};
5560 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
5562 let Inst{19} = lane{0};
5565 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5566 (VDUPLN32d DPR:$Vm, imm:$lane)>;
5568 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
5569 (VDUPLN32q DPR:$Vm, imm:$lane)>;
5571 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
5572 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
5573 (DSubReg_i8_reg imm:$lane))),
5574 (SubReg_i8_lane imm:$lane)))>;
5575 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
5576 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
5577 (DSubReg_i16_reg imm:$lane))),
5578 (SubReg_i16_lane imm:$lane)))>;
5579 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
5580 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
5581 (DSubReg_i32_reg imm:$lane))),
5582 (SubReg_i32_lane imm:$lane)))>;
5583 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
5584 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
5585 (DSubReg_i32_reg imm:$lane))),
5586 (SubReg_i32_lane imm:$lane)))>;
5588 def : Pat<(v2f32 (NEONvdup (f32 SPR:$src))),
5589 (v2f32 (VDUPLN32d (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5590 SPR:$src, ssub_0), (i32 0)))>;
5591 def : Pat<(v4f32 (NEONvdup (f32 SPR:$src))),
5592 (v4f32 (VDUPLN32q (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)),
5593 SPR:$src, ssub_0), (i32 0)))>;
5595 // VMOVN : Vector Narrowing Move
5596 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
5597 "vmovn", "i", trunc>;
5598 // VQMOVN : Vector Saturating Narrowing Move
5599 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
5600 "vqmovn", "s", int_arm_neon_vqmovns>;
5601 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
5602 "vqmovn", "u", int_arm_neon_vqmovnu>;
5603 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
5604 "vqmovun", "s", int_arm_neon_vqmovnsu>;
5605 // VMOVL : Vector Lengthening Move
5606 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
5607 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
5608 def : Pat<(v8i16 (anyext (v8i8 DPR:$Vm))), (VMOVLuv8i16 DPR:$Vm)>;
5609 def : Pat<(v4i32 (anyext (v4i16 DPR:$Vm))), (VMOVLuv4i32 DPR:$Vm)>;
5610 def : Pat<(v2i64 (anyext (v2i32 DPR:$Vm))), (VMOVLuv2i64 DPR:$Vm)>;
5612 // Vector Conversions.
5614 // VCVT : Vector Convert Between Floating-Point and Integers
5615 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5616 v2i32, v2f32, fp_to_sint>;
5617 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5618 v2i32, v2f32, fp_to_uint>;
5619 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5620 v2f32, v2i32, sint_to_fp>;
5621 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5622 v2f32, v2i32, uint_to_fp>;
5624 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
5625 v4i32, v4f32, fp_to_sint>;
5626 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
5627 v4i32, v4f32, fp_to_uint>;
5628 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
5629 v4f32, v4i32, sint_to_fp>;
5630 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
5631 v4f32, v4i32, uint_to_fp>;
5634 multiclass VCVT_FPI<string op, bits<3> op10_8, SDPatternOperator IntS,
5635 SDPatternOperator IntU> {
5636 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5637 def SD : N2VDIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5638 "s32.f32", v2i32, v2f32, IntS>, Requires<[HasV8, HasNEON]>;
5639 def SQ : N2VQIntnp<0b11, op10_8, 0, NoItinerary, !strconcat("vcvt", op),
5640 "s32.f32", v4i32, v4f32, IntS>, Requires<[HasV8, HasNEON]>;
5641 def UD : N2VDIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5642 "u32.f32", v2i32, v2f32, IntU>, Requires<[HasV8, HasNEON]>;
5643 def UQ : N2VQIntnp<0b11, op10_8, 1, NoItinerary, !strconcat("vcvt", op),
5644 "u32.f32", v4i32, v4f32, IntU>, Requires<[HasV8, HasNEON]>;
5648 defm VCVTAN : VCVT_FPI<"a", 0b000, int_arm_neon_vcvtas, int_arm_neon_vcvtau>;
5649 defm VCVTNN : VCVT_FPI<"n", 0b001, int_arm_neon_vcvtns, int_arm_neon_vcvtnu>;
5650 defm VCVTPN : VCVT_FPI<"p", 0b010, int_arm_neon_vcvtps, int_arm_neon_vcvtpu>;
5651 defm VCVTMN : VCVT_FPI<"m", 0b011, int_arm_neon_vcvtms, int_arm_neon_vcvtmu>;
5653 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
5654 let DecoderMethod = "DecodeVCVTD" in {
5655 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5656 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
5657 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5658 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
5659 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5660 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
5661 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5662 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5665 let DecoderMethod = "DecodeVCVTQ" in {
5666 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5667 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5668 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5669 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5670 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5671 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5672 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5673 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5676 def : NEONInstAlias<"vcvt${p}.s32.f32 $Dd, $Dm, #0",
5677 (VCVTf2sd DPR:$Dd, DPR:$Dm, pred:$p)>;
5678 def : NEONInstAlias<"vcvt${p}.u32.f32 $Dd, $Dm, #0",
5679 (VCVTf2ud DPR:$Dd, DPR:$Dm, pred:$p)>;
5680 def : NEONInstAlias<"vcvt${p}.f32.s32 $Dd, $Dm, #0",
5681 (VCVTs2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5682 def : NEONInstAlias<"vcvt${p}.f32.u32 $Dd, $Dm, #0",
5683 (VCVTu2fd DPR:$Dd, DPR:$Dm, pred:$p)>;
5685 def : NEONInstAlias<"vcvt${p}.s32.f32 $Qd, $Qm, #0",
5686 (VCVTf2sq QPR:$Qd, QPR:$Qm, pred:$p)>;
5687 def : NEONInstAlias<"vcvt${p}.u32.f32 $Qd, $Qm, #0",
5688 (VCVTf2uq QPR:$Qd, QPR:$Qm, pred:$p)>;
5689 def : NEONInstAlias<"vcvt${p}.f32.s32 $Qd, $Qm, #0",
5690 (VCVTs2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5691 def : NEONInstAlias<"vcvt${p}.f32.u32 $Qd, $Qm, #0",
5692 (VCVTu2fq QPR:$Qd, QPR:$Qm, pred:$p)>;
5695 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5696 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5697 IIC_VUNAQ, "vcvt", "f16.f32",
5698 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5699 Requires<[HasNEON, HasFP16]>;
5700 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5701 IIC_VUNAQ, "vcvt", "f32.f16",
5702 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5703 Requires<[HasNEON, HasFP16]>;
5707 // VREV64 : Vector Reverse elements within 64-bit doublewords
5709 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5710 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5711 (ins DPR:$Vm), IIC_VMOVD,
5712 OpcodeStr, Dt, "$Vd, $Vm", "",
5713 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5714 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5715 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5716 (ins QPR:$Vm), IIC_VMOVQ,
5717 OpcodeStr, Dt, "$Vd, $Vm", "",
5718 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5720 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5721 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5722 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5723 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5725 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5726 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5727 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5728 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5730 // VREV32 : Vector Reverse elements within 32-bit words
5732 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5733 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5734 (ins DPR:$Vm), IIC_VMOVD,
5735 OpcodeStr, Dt, "$Vd, $Vm", "",
5736 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5737 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5738 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5739 (ins QPR:$Vm), IIC_VMOVQ,
5740 OpcodeStr, Dt, "$Vd, $Vm", "",
5741 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5743 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5744 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5746 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5747 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5749 // VREV16 : Vector Reverse elements within 16-bit halfwords
5751 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5752 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5753 (ins DPR:$Vm), IIC_VMOVD,
5754 OpcodeStr, Dt, "$Vd, $Vm", "",
5755 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5756 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5757 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5758 (ins QPR:$Vm), IIC_VMOVQ,
5759 OpcodeStr, Dt, "$Vd, $Vm", "",
5760 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5762 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5763 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5765 // Other Vector Shuffles.
5767 // Aligned extractions: really just dropping registers
5769 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5770 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5771 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5773 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5775 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5777 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5779 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5781 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5784 // VEXT : Vector Extract
5787 // All of these have a two-operand InstAlias.
5788 let TwoOperandAliasConstraint = "$Vn = $Vd" in {
5789 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5790 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5791 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5792 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5793 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5794 (Ty DPR:$Vm), imm:$index)))]> {
5797 let Inst{10-8} = index{2-0};
5800 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5801 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5802 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5803 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5804 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5805 (Ty QPR:$Vm), imm:$index)))]> {
5807 let Inst{11-8} = index{3-0};
5811 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5812 let Inst{10-8} = index{2-0};
5814 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5815 let Inst{10-9} = index{1-0};
5818 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5819 let Inst{10} = index{0};
5820 let Inst{9-8} = 0b00;
5822 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5825 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5827 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5828 let Inst{11-8} = index{3-0};
5830 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5831 let Inst{11-9} = index{2-0};
5834 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5835 let Inst{11-10} = index{1-0};
5836 let Inst{9-8} = 0b00;
5838 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5839 let Inst{11} = index{0};
5840 let Inst{10-8} = 0b000;
5842 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5845 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5847 // VTRN : Vector Transpose
5849 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5850 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5851 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5853 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5854 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5855 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5857 // VUZP : Vector Unzip (Deinterleave)
5859 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5860 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5861 // vuzp.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5862 def : NEONInstAlias<"vuzp${p}.32 $Dd, $Dm",
5863 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5865 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5866 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5867 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5869 // VZIP : Vector Zip (Interleave)
5871 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5872 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5873 // vzip.32 Dd, Dm is a pseudo-instruction expanded to vtrn.32 Dd, Dm.
5874 def : NEONInstAlias<"vzip${p}.32 $Dd, $Dm",
5875 (VTRNd32 DPR:$Dd, DPR:$Dm, pred:$p)>;
5877 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5878 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5879 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5881 // Vector Table Lookup and Table Extension.
5883 // VTBL : Vector Table Lookup
5884 let DecoderMethod = "DecodeTBLInstruction" in {
5886 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5887 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5888 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5889 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5890 let hasExtraSrcRegAllocReq = 1 in {
5892 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5893 (ins VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5894 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5896 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5897 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5898 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5900 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5901 (ins VecListFourD:$Vn, DPR:$Vm),
5903 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5904 } // hasExtraSrcRegAllocReq = 1
5907 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5909 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5911 // VTBX : Vector Table Extension
5913 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5914 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5915 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5916 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5917 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5918 let hasExtraSrcRegAllocReq = 1 in {
5920 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5921 (ins DPR:$orig, VecListDPair:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5922 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5924 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5925 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5926 NVTBLFrm, IIC_VTBX3,
5927 "vtbx", "8", "$Vd, $Vn, $Vm",
5930 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5931 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5932 "vtbx", "8", "$Vd, $Vn, $Vm",
5934 } // hasExtraSrcRegAllocReq = 1
5937 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5938 IIC_VTBX3, "$orig = $dst", []>;
5940 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5941 IIC_VTBX4, "$orig = $dst", []>;
5942 } // DecoderMethod = "DecodeTBLInstruction"
5944 // VRINT : Vector Rounding
5945 multiclass VRINT_FPI<string op, bits<3> op9_7, SDPatternOperator Int> {
5946 let PostEncoderMethod = "NEONThumb2V8PostEncoder", DecoderNamespace = "v8NEON" in {
5947 def D : N2VDIntnp<0b10, 0b100, 0, NoItinerary,
5948 !strconcat("vrint", op), "f32",
5949 v2f32, v2f32, Int>, Requires<[HasV8, HasNEON]> {
5950 let Inst{9-7} = op9_7;
5952 def Q : N2VQIntnp<0b10, 0b100, 0, NoItinerary,
5953 !strconcat("vrint", op), "f32",
5954 v4f32, v4f32, Int>, Requires<[HasV8, HasNEON]> {
5955 let Inst{9-7} = op9_7;
5959 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Dd, $Dm"),
5960 (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm)>;
5961 def : NEONInstAlias<!strconcat("vrint", op, ".f32.f32\t$Qd, $Qm"),
5962 (!cast<Instruction>(NAME#"Q") QPR:$Qd, QPR:$Qm)>;
5965 defm VRINTNN : VRINT_FPI<"n", 0b000, int_arm_neon_vrintn>;
5966 defm VRINTXN : VRINT_FPI<"x", 0b001, int_arm_neon_vrintx>;
5967 defm VRINTAN : VRINT_FPI<"a", 0b010, int_arm_neon_vrinta>;
5968 defm VRINTZN : VRINT_FPI<"z", 0b011, int_arm_neon_vrintz>;
5969 defm VRINTMN : VRINT_FPI<"m", 0b101, int_arm_neon_vrintm>;
5970 defm VRINTPN : VRINT_FPI<"p", 0b111, int_arm_neon_vrintp>;
5972 // Cryptography instructions
5973 let PostEncoderMethod = "NEONThumb2DataIPostEncoder",
5974 DecoderNamespace = "v8Crypto", hasSideEffects = 0 in {
5975 class AES<string op, bit op7, bit op6, SDPatternOperator Int>
5976 : N2VQIntXnp<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5977 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5978 Requires<[HasV8, HasCrypto]>;
5979 class AES2Op<string op, bit op7, bit op6, SDPatternOperator Int>
5980 : N2VQIntX2np<0b00, 0b00, 0b011, op6, op7, NoItinerary,
5981 !strconcat("aes", op), "8", v16i8, v16i8, Int>,
5982 Requires<[HasV8, HasCrypto]>;
5983 class N2SHA<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5984 SDPatternOperator Int>
5985 : N2VQIntXnp<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5986 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5987 Requires<[HasV8, HasCrypto]>;
5988 class N2SHA2Op<string op, bits<2> op17_16, bits<3> op10_8, bit op7, bit op6,
5989 SDPatternOperator Int>
5990 : N2VQIntX2np<0b10, op17_16, op10_8, op6, op7, NoItinerary,
5991 !strconcat("sha", op), "32", v4i32, v4i32, Int>,
5992 Requires<[HasV8, HasCrypto]>;
5993 class N3SHA3Op<string op, bits<5> op27_23, bits<2> op21_20, SDPatternOperator Int>
5994 : N3VQInt3np<op27_23, op21_20, 0b1100, 1, 0, N3RegFrm, NoItinerary,
5995 !strconcat("sha", op), "32", v4i32, v4i32, Int, 0>,
5996 Requires<[HasV8, HasCrypto]>;
5999 def AESD : AES2Op<"d", 0, 1, int_arm_neon_aesd>;
6000 def AESE : AES2Op<"e", 0, 0, int_arm_neon_aese>;
6001 def AESIMC : AES<"imc", 1, 1, int_arm_neon_aesimc>;
6002 def AESMC : AES<"mc", 1, 0, int_arm_neon_aesmc>;
6004 def SHA1H : N2SHA<"1h", 0b01, 0b010, 1, 1, null_frag>;
6005 def SHA1SU1 : N2SHA2Op<"1su1", 0b10, 0b011, 1, 0, int_arm_neon_sha1su1>;
6006 def SHA256SU0 : N2SHA2Op<"256su0", 0b10, 0b011, 1, 1, int_arm_neon_sha256su0>;
6007 def SHA1C : N3SHA3Op<"1c", 0b00100, 0b00, null_frag>;
6008 def SHA1M : N3SHA3Op<"1m", 0b00100, 0b10, null_frag>;
6009 def SHA1P : N3SHA3Op<"1p", 0b00100, 0b01, null_frag>;
6010 def SHA1SU0 : N3SHA3Op<"1su0", 0b00100, 0b11, int_arm_neon_sha1su0>;
6011 def SHA256H : N3SHA3Op<"256h", 0b00110, 0b00, int_arm_neon_sha256h>;
6012 def SHA256H2 : N3SHA3Op<"256h2", 0b00110, 0b01, int_arm_neon_sha256h2>;
6013 def SHA256SU1 : N3SHA3Op<"256su1", 0b00110, 0b10, int_arm_neon_sha256su1>;
6015 def : Pat<(i32 (int_arm_neon_sha1h i32:$Rn)),
6016 (COPY_TO_REGCLASS (f32 (EXTRACT_SUBREG
6017 (SHA1H (SUBREG_TO_REG (i64 0),
6018 (f32 (COPY_TO_REGCLASS i32:$Rn, SPR)),
6022 def : Pat<(v4i32 (int_arm_neon_sha1c v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6023 (SHA1C v4i32:$hash_abcd,
6024 (SUBREG_TO_REG (i64 0),
6025 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6029 def : Pat<(v4i32 (int_arm_neon_sha1m v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6030 (SHA1M v4i32:$hash_abcd,
6031 (SUBREG_TO_REG (i64 0),
6032 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6036 def : Pat<(v4i32 (int_arm_neon_sha1p v4i32:$hash_abcd, i32:$hash_e, v4i32:$wk)),
6037 (SHA1P v4i32:$hash_abcd,
6038 (SUBREG_TO_REG (i64 0),
6039 (f32 (COPY_TO_REGCLASS i32:$hash_e, SPR)),
6043 //===----------------------------------------------------------------------===//
6044 // NEON instructions for single-precision FP math
6045 //===----------------------------------------------------------------------===//
6047 class N2VSPat<SDNode OpNode, NeonI Inst>
6048 : NEONFPPat<(f32 (OpNode SPR:$a)),
6050 (v2f32 (COPY_TO_REGCLASS (Inst
6052 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6053 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
6055 class N3VSPat<SDNode OpNode, NeonI Inst>
6056 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
6058 (v2f32 (COPY_TO_REGCLASS (Inst
6060 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6063 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6064 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6066 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
6067 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
6069 (v2f32 (COPY_TO_REGCLASS (Inst
6071 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6074 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6077 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
6078 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
6080 def : N3VSPat<fadd, VADDfd>;
6081 def : N3VSPat<fsub, VSUBfd>;
6082 def : N3VSPat<fmul, VMULfd>;
6083 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
6084 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6085 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
6086 Requires<[HasNEON, UseNEONForFP, UseFPVMLx, DontUseFusedMAC]>;
6087 def : N3VSMulOpPat<fmul, fadd, VFMAfd>,
6088 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6089 def : N3VSMulOpPat<fmul, fsub, VFMSfd>,
6090 Requires<[HasVFP4, UseNEONForFP, UseFusedMAC]>;
6091 def : N2VSPat<fabs, VABSfd>;
6092 def : N2VSPat<fneg, VNEGfd>;
6093 def : N3VSPat<NEONfmax, VMAXfd>;
6094 def : N3VSPat<NEONfmin, VMINfd>;
6095 def : N2VSPat<arm_ftosi, VCVTf2sd>;
6096 def : N2VSPat<arm_ftoui, VCVTf2ud>;
6097 def : N2VSPat<arm_sitof, VCVTs2fd>;
6098 def : N2VSPat<arm_uitof, VCVTu2fd>;
6100 // Prefer VMOVDRR for i32 -> f32 bitcasts, it can write all DPR registers.
6101 def : Pat<(f32 (bitconvert GPR:$a)),
6102 (EXTRACT_SUBREG (VMOVDRR GPR:$a, GPR:$a), ssub_0)>,
6103 Requires<[HasNEON, DontUseVMOVSR]>;
6105 //===----------------------------------------------------------------------===//
6106 // Non-Instruction Patterns
6107 //===----------------------------------------------------------------------===//
6110 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
6111 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
6112 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
6113 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
6114 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
6115 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
6116 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
6117 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
6118 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
6119 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
6120 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
6121 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
6122 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
6123 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
6124 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
6125 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
6126 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
6127 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
6128 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
6129 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
6130 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
6131 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
6132 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
6133 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
6134 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
6135 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
6136 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
6137 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
6138 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
6139 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
6141 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
6142 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
6143 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
6144 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
6145 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
6146 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
6147 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
6148 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
6149 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
6150 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
6151 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
6152 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
6153 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
6154 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
6155 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
6156 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
6157 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
6158 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
6159 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
6160 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
6161 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
6162 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
6163 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
6164 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
6165 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
6166 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
6167 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
6168 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
6169 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
6170 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
6172 // Fold extracting an element out of a v2i32 into a vfp register.
6173 def : Pat<(f32 (bitconvert (i32 (extractelt (v2i32 DPR:$src), imm:$lane)))),
6174 (f32 (EXTRACT_SUBREG DPR:$src, (SSubReg_f32_reg imm:$lane)))>;
6176 // Vector lengthening move with load, matching extending loads.
6178 // extload, zextload and sextload for a standard lengthening load. Example:
6179 // Lengthen_Single<"8", "i16", "8"> =
6180 // Pat<(v8i16 (extloadvi8 addrmode6:$addr))
6181 // (VMOVLuv8i16 (VLD1d8 addrmode6:$addr,
6182 // (f64 (IMPLICIT_DEF)), (i32 0)))>;
6183 multiclass Lengthen_Single<string DestLanes, string DestTy, string SrcTy> {
6184 let AddedComplexity = 10 in {
6185 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6186 (!cast<PatFrag>("extloadvi" # SrcTy) addrmode6:$addr)),
6187 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6188 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6190 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6191 (!cast<PatFrag>("zextloadvi" # SrcTy) addrmode6:$addr)),
6192 (!cast<Instruction>("VMOVLuv" # DestLanes # DestTy)
6193 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6195 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6196 (!cast<PatFrag>("sextloadvi" # SrcTy) addrmode6:$addr)),
6197 (!cast<Instruction>("VMOVLsv" # DestLanes # DestTy)
6198 (!cast<Instruction>("VLD1d" # SrcTy) addrmode6:$addr))>;
6202 // extload, zextload and sextload for a lengthening load which only uses
6203 // half the lanes available. Example:
6204 // Lengthen_HalfSingle<"4", "i16", "8", "i16", "i8"> =
6205 // Pat<(v4i16 (extloadvi8 addrmode6oneL32:$addr)),
6206 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6207 // (f64 (IMPLICIT_DEF)), (i32 0))),
6209 multiclass Lengthen_HalfSingle<string DestLanes, string DestTy, string SrcTy,
6210 string InsnLanes, string InsnTy> {
6211 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6212 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6213 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6214 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6216 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6217 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6218 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # InsnLanes # InsnTy)
6219 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6221 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6222 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6223 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # InsnLanes # InsnTy)
6224 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6228 // extload, zextload and sextload for a lengthening load followed by another
6229 // lengthening load, to quadruple the initial length.
6231 // Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32"> =
6232 // Pat<(v4i32 (extloadvi8 addrmode6oneL32:$addr))
6233 // (EXTRACT_SUBREG (VMOVLuv4i32
6234 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd32 addrmode6oneL32:$addr,
6235 // (f64 (IMPLICIT_DEF)),
6239 multiclass Lengthen_Double<string DestLanes, string DestTy, string SrcTy,
6240 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6242 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6243 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6oneL32:$addr)),
6244 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6245 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6246 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6248 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6249 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6oneL32:$addr)),
6250 (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6251 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6252 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6254 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6255 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6oneL32:$addr)),
6256 (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6257 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6258 (VLD1LNd32 addrmode6oneL32:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6262 // extload, zextload and sextload for a lengthening load followed by another
6263 // lengthening load, to quadruple the initial length, but which ends up only
6264 // requiring half the available lanes (a 64-bit outcome instead of a 128-bit).
6266 // Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32"> =
6267 // Pat<(v2i32 (extloadvi8 addrmode6:$addr))
6268 // (EXTRACT_SUBREG (VMOVLuv4i32
6269 // (EXTRACT_SUBREG (VMOVLuv8i16 (VLD1LNd16 addrmode6:$addr,
6270 // (f64 (IMPLICIT_DEF)), (i32 0))),
6273 multiclass Lengthen_HalfDouble<string DestLanes, string DestTy, string SrcTy,
6274 string Insn1Lanes, string Insn1Ty, string Insn2Lanes,
6276 def _Any : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6277 (!cast<PatFrag>("extloadv" # SrcTy) addrmode6:$addr)),
6278 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6279 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6280 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6283 def _Z : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6284 (!cast<PatFrag>("zextloadv" # SrcTy) addrmode6:$addr)),
6285 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn2Lanes # Insn2Ty)
6286 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLuv" # Insn1Lanes # Insn1Ty)
6287 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6290 def _S : Pat<(!cast<ValueType>("v" # DestLanes # DestTy)
6291 (!cast<PatFrag>("sextloadv" # SrcTy) addrmode6:$addr)),
6292 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn2Lanes # Insn2Ty)
6293 (EXTRACT_SUBREG (!cast<Instruction>("VMOVLsv" # Insn1Lanes # Insn1Ty)
6294 (VLD1LNd16 addrmode6:$addr, (f64 (IMPLICIT_DEF)), (i32 0))),
6299 defm : Lengthen_Single<"8", "i16", "8">; // v8i8 -> v8i16
6300 defm : Lengthen_Single<"4", "i32", "16">; // v4i16 -> v4i32
6301 defm : Lengthen_Single<"2", "i64", "32">; // v2i32 -> v2i64
6303 defm : Lengthen_HalfSingle<"4", "i16", "i8", "8", "i16">; // v4i8 -> v4i16
6304 defm : Lengthen_HalfSingle<"2", "i32", "i16", "4", "i32">; // v2i16 -> v2i32
6306 // Double lengthening - v4i8 -> v4i16 -> v4i32
6307 defm : Lengthen_Double<"4", "i32", "i8", "8", "i16", "4", "i32">;
6308 // v2i8 -> v2i16 -> v2i32
6309 defm : Lengthen_HalfDouble<"2", "i32", "i8", "8", "i16", "4", "i32">;
6310 // v2i16 -> v2i32 -> v2i64
6311 defm : Lengthen_Double<"2", "i64", "i16", "4", "i32", "2", "i64">;
6313 // Triple lengthening - v2i8 -> v2i16 -> v2i32 -> v2i64
6314 def : Pat<(v2i64 (extloadvi8 addrmode6:$addr)),
6315 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6316 (VLD1LNd16 addrmode6:$addr,
6317 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6318 def : Pat<(v2i64 (zextloadvi8 addrmode6:$addr)),
6319 (VMOVLuv2i64 (EXTRACT_SUBREG (VMOVLuv4i32 (EXTRACT_SUBREG (VMOVLuv8i16
6320 (VLD1LNd16 addrmode6:$addr,
6321 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6322 def : Pat<(v2i64 (sextloadvi8 addrmode6:$addr)),
6323 (VMOVLsv2i64 (EXTRACT_SUBREG (VMOVLsv4i32 (EXTRACT_SUBREG (VMOVLsv8i16
6324 (VLD1LNd16 addrmode6:$addr,
6325 (f64 (IMPLICIT_DEF)), (i32 0))), dsub_0)), dsub_0))>;
6327 //===----------------------------------------------------------------------===//
6328 // Assembler aliases
6331 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
6332 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
6333 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
6334 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
6336 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
6337 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6338 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6339 defm : NEONDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
6340 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6341 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6342 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6343 defm : NEONDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
6344 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6345 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6346 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6347 defm : NEONDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
6348 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6349 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6350 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
6351 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
6352 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
6353 // ... two-operand aliases
6354 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6355 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6356 defm : NEONDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
6357 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6358 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6359 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6360 defm : NEONDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
6361 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6362 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6363 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
6364 defm : NEONDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
6365 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
6367 // VLD1 single-lane pseudo-instructions. These need special handling for
6368 // the lane index that an InstAlias can't handle, so we use these instead.
6369 def VLD1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr",
6370 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6372 def VLD1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr",
6373 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6375 def VLD1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr",
6376 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6379 def VLD1LNdWB_fixed_Asm_8 :
6380 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr!",
6381 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6383 def VLD1LNdWB_fixed_Asm_16 :
6384 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr!",
6385 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6387 def VLD1LNdWB_fixed_Asm_32 :
6388 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr!",
6389 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6391 def VLD1LNdWB_register_Asm_8 :
6392 NEONDataTypeAsmPseudoInst<"vld1${p}", ".8", "$list, $addr, $Rm",
6393 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6394 rGPR:$Rm, pred:$p)>;
6395 def VLD1LNdWB_register_Asm_16 :
6396 NEONDataTypeAsmPseudoInst<"vld1${p}", ".16", "$list, $addr, $Rm",
6397 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6398 rGPR:$Rm, pred:$p)>;
6399 def VLD1LNdWB_register_Asm_32 :
6400 NEONDataTypeAsmPseudoInst<"vld1${p}", ".32", "$list, $addr, $Rm",
6401 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6402 rGPR:$Rm, pred:$p)>;
6405 // VST1 single-lane pseudo-instructions. These need special handling for
6406 // the lane index that an InstAlias can't handle, so we use these instead.
6407 def VST1LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr",
6408 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6410 def VST1LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr",
6411 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6413 def VST1LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr",
6414 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6417 def VST1LNdWB_fixed_Asm_8 :
6418 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr!",
6419 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6421 def VST1LNdWB_fixed_Asm_16 :
6422 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr!",
6423 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6425 def VST1LNdWB_fixed_Asm_32 :
6426 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr!",
6427 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6429 def VST1LNdWB_register_Asm_8 :
6430 NEONDataTypeAsmPseudoInst<"vst1${p}", ".8", "$list, $addr, $Rm",
6431 (ins VecListOneDByteIndexed:$list, addrmode6alignNone:$addr,
6432 rGPR:$Rm, pred:$p)>;
6433 def VST1LNdWB_register_Asm_16 :
6434 NEONDataTypeAsmPseudoInst<"vst1${p}", ".16", "$list, $addr, $Rm",
6435 (ins VecListOneDHWordIndexed:$list, addrmode6align16:$addr,
6436 rGPR:$Rm, pred:$p)>;
6437 def VST1LNdWB_register_Asm_32 :
6438 NEONDataTypeAsmPseudoInst<"vst1${p}", ".32", "$list, $addr, $Rm",
6439 (ins VecListOneDWordIndexed:$list, addrmode6align32:$addr,
6440 rGPR:$Rm, pred:$p)>;
6442 // VLD2 single-lane pseudo-instructions. These need special handling for
6443 // the lane index that an InstAlias can't handle, so we use these instead.
6444 def VLD2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr",
6445 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6447 def VLD2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6448 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6450 def VLD2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6451 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr, pred:$p)>;
6452 def VLD2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr",
6453 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6455 def VLD2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr",
6456 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6459 def VLD2LNdWB_fixed_Asm_8 :
6460 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr!",
6461 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6463 def VLD2LNdWB_fixed_Asm_16 :
6464 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6465 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6467 def VLD2LNdWB_fixed_Asm_32 :
6468 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6469 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6471 def VLD2LNqWB_fixed_Asm_16 :
6472 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr!",
6473 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6475 def VLD2LNqWB_fixed_Asm_32 :
6476 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr!",
6477 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6479 def VLD2LNdWB_register_Asm_8 :
6480 NEONDataTypeAsmPseudoInst<"vld2${p}", ".8", "$list, $addr, $Rm",
6481 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6482 rGPR:$Rm, pred:$p)>;
6483 def VLD2LNdWB_register_Asm_16 :
6484 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6485 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6486 rGPR:$Rm, pred:$p)>;
6487 def VLD2LNdWB_register_Asm_32 :
6488 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6489 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6490 rGPR:$Rm, pred:$p)>;
6491 def VLD2LNqWB_register_Asm_16 :
6492 NEONDataTypeAsmPseudoInst<"vld2${p}", ".16", "$list, $addr, $Rm",
6493 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6494 rGPR:$Rm, pred:$p)>;
6495 def VLD2LNqWB_register_Asm_32 :
6496 NEONDataTypeAsmPseudoInst<"vld2${p}", ".32", "$list, $addr, $Rm",
6497 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6498 rGPR:$Rm, pred:$p)>;
6501 // VST2 single-lane pseudo-instructions. These need special handling for
6502 // the lane index that an InstAlias can't handle, so we use these instead.
6503 def VST2LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr",
6504 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6506 def VST2LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6507 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6509 def VST2LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6510 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6512 def VST2LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr",
6513 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6515 def VST2LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr",
6516 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6519 def VST2LNdWB_fixed_Asm_8 :
6520 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr!",
6521 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6523 def VST2LNdWB_fixed_Asm_16 :
6524 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6525 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6527 def VST2LNdWB_fixed_Asm_32 :
6528 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6529 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6531 def VST2LNqWB_fixed_Asm_16 :
6532 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16", "$list, $addr!",
6533 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6535 def VST2LNqWB_fixed_Asm_32 :
6536 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr!",
6537 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6539 def VST2LNdWB_register_Asm_8 :
6540 NEONDataTypeAsmPseudoInst<"vst2${p}", ".8", "$list, $addr, $Rm",
6541 (ins VecListTwoDByteIndexed:$list, addrmode6align16:$addr,
6542 rGPR:$Rm, pred:$p)>;
6543 def VST2LNdWB_register_Asm_16 :
6544 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6545 (ins VecListTwoDHWordIndexed:$list, addrmode6align32:$addr,
6546 rGPR:$Rm, pred:$p)>;
6547 def VST2LNdWB_register_Asm_32 :
6548 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6549 (ins VecListTwoDWordIndexed:$list, addrmode6align64:$addr,
6550 rGPR:$Rm, pred:$p)>;
6551 def VST2LNqWB_register_Asm_16 :
6552 NEONDataTypeAsmPseudoInst<"vst2${p}", ".16","$list, $addr, $Rm",
6553 (ins VecListTwoQHWordIndexed:$list, addrmode6align32:$addr,
6554 rGPR:$Rm, pred:$p)>;
6555 def VST2LNqWB_register_Asm_32 :
6556 NEONDataTypeAsmPseudoInst<"vst2${p}", ".32", "$list, $addr, $Rm",
6557 (ins VecListTwoQWordIndexed:$list, addrmode6align64:$addr,
6558 rGPR:$Rm, pred:$p)>;
6560 // VLD3 all-lanes pseudo-instructions. These need special handling for
6561 // the lane index that an InstAlias can't handle, so we use these instead.
6562 def VLD3DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6563 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6565 def VLD3DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6566 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6568 def VLD3DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6569 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6571 def VLD3DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6572 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6574 def VLD3DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6575 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6577 def VLD3DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6578 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6581 def VLD3DUPdWB_fixed_Asm_8 :
6582 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6583 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6585 def VLD3DUPdWB_fixed_Asm_16 :
6586 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6587 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6589 def VLD3DUPdWB_fixed_Asm_32 :
6590 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6591 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6593 def VLD3DUPqWB_fixed_Asm_8 :
6594 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6595 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6597 def VLD3DUPqWB_fixed_Asm_16 :
6598 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6599 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6601 def VLD3DUPqWB_fixed_Asm_32 :
6602 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6603 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6605 def VLD3DUPdWB_register_Asm_8 :
6606 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6607 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6608 rGPR:$Rm, pred:$p)>;
6609 def VLD3DUPdWB_register_Asm_16 :
6610 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6611 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6612 rGPR:$Rm, pred:$p)>;
6613 def VLD3DUPdWB_register_Asm_32 :
6614 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6615 (ins VecListThreeDAllLanes:$list, addrmode6dupalignNone:$addr,
6616 rGPR:$Rm, pred:$p)>;
6617 def VLD3DUPqWB_register_Asm_8 :
6618 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6619 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6620 rGPR:$Rm, pred:$p)>;
6621 def VLD3DUPqWB_register_Asm_16 :
6622 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6623 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6624 rGPR:$Rm, pred:$p)>;
6625 def VLD3DUPqWB_register_Asm_32 :
6626 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6627 (ins VecListThreeQAllLanes:$list, addrmode6dupalignNone:$addr,
6628 rGPR:$Rm, pred:$p)>;
6631 // VLD3 single-lane pseudo-instructions. These need special handling for
6632 // the lane index that an InstAlias can't handle, so we use these instead.
6633 def VLD3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6634 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6636 def VLD3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6637 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6639 def VLD3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6640 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6642 def VLD3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6643 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6645 def VLD3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6646 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6649 def VLD3LNdWB_fixed_Asm_8 :
6650 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6651 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6653 def VLD3LNdWB_fixed_Asm_16 :
6654 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6655 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6657 def VLD3LNdWB_fixed_Asm_32 :
6658 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6659 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6661 def VLD3LNqWB_fixed_Asm_16 :
6662 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6663 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6665 def VLD3LNqWB_fixed_Asm_32 :
6666 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6667 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6669 def VLD3LNdWB_register_Asm_8 :
6670 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6671 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6672 rGPR:$Rm, pred:$p)>;
6673 def VLD3LNdWB_register_Asm_16 :
6674 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6675 (ins VecListThreeDHWordIndexed:$list,
6676 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6677 def VLD3LNdWB_register_Asm_32 :
6678 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6679 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6680 rGPR:$Rm, pred:$p)>;
6681 def VLD3LNqWB_register_Asm_16 :
6682 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6683 (ins VecListThreeQHWordIndexed:$list,
6684 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6685 def VLD3LNqWB_register_Asm_32 :
6686 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6687 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6688 rGPR:$Rm, pred:$p)>;
6690 // VLD3 multiple structure pseudo-instructions. These need special handling for
6691 // the vector operands that the normal instructions don't yet model.
6692 // FIXME: Remove these when the register classes and instructions are updated.
6693 def VLD3dAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6694 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6695 def VLD3dAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6696 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6697 def VLD3dAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6698 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6699 def VLD3qAsm_8 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr",
6700 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6701 def VLD3qAsm_16 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr",
6702 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6703 def VLD3qAsm_32 : NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr",
6704 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6706 def VLD3dWB_fixed_Asm_8 :
6707 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6708 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6709 def VLD3dWB_fixed_Asm_16 :
6710 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6711 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6712 def VLD3dWB_fixed_Asm_32 :
6713 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6714 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6715 def VLD3qWB_fixed_Asm_8 :
6716 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr!",
6717 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6718 def VLD3qWB_fixed_Asm_16 :
6719 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr!",
6720 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6721 def VLD3qWB_fixed_Asm_32 :
6722 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr!",
6723 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6724 def VLD3dWB_register_Asm_8 :
6725 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6726 (ins VecListThreeD:$list, addrmode6align64:$addr,
6727 rGPR:$Rm, pred:$p)>;
6728 def VLD3dWB_register_Asm_16 :
6729 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6730 (ins VecListThreeD:$list, addrmode6align64:$addr,
6731 rGPR:$Rm, pred:$p)>;
6732 def VLD3dWB_register_Asm_32 :
6733 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6734 (ins VecListThreeD:$list, addrmode6align64:$addr,
6735 rGPR:$Rm, pred:$p)>;
6736 def VLD3qWB_register_Asm_8 :
6737 NEONDataTypeAsmPseudoInst<"vld3${p}", ".8", "$list, $addr, $Rm",
6738 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6739 rGPR:$Rm, pred:$p)>;
6740 def VLD3qWB_register_Asm_16 :
6741 NEONDataTypeAsmPseudoInst<"vld3${p}", ".16", "$list, $addr, $Rm",
6742 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6743 rGPR:$Rm, pred:$p)>;
6744 def VLD3qWB_register_Asm_32 :
6745 NEONDataTypeAsmPseudoInst<"vld3${p}", ".32", "$list, $addr, $Rm",
6746 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6747 rGPR:$Rm, pred:$p)>;
6749 // VST3 single-lane pseudo-instructions. These need special handling for
6750 // the lane index that an InstAlias can't handle, so we use these instead.
6751 def VST3LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6752 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6754 def VST3LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6755 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6757 def VST3LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6758 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6760 def VST3LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6761 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6763 def VST3LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6764 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6767 def VST3LNdWB_fixed_Asm_8 :
6768 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6769 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6771 def VST3LNdWB_fixed_Asm_16 :
6772 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6773 (ins VecListThreeDHWordIndexed:$list, addrmode6alignNone:$addr,
6775 def VST3LNdWB_fixed_Asm_32 :
6776 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6777 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6779 def VST3LNqWB_fixed_Asm_16 :
6780 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6781 (ins VecListThreeQHWordIndexed:$list, addrmode6alignNone:$addr,
6783 def VST3LNqWB_fixed_Asm_32 :
6784 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6785 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6787 def VST3LNdWB_register_Asm_8 :
6788 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6789 (ins VecListThreeDByteIndexed:$list, addrmode6alignNone:$addr,
6790 rGPR:$Rm, pred:$p)>;
6791 def VST3LNdWB_register_Asm_16 :
6792 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6793 (ins VecListThreeDHWordIndexed:$list,
6794 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6795 def VST3LNdWB_register_Asm_32 :
6796 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6797 (ins VecListThreeDWordIndexed:$list, addrmode6alignNone:$addr,
6798 rGPR:$Rm, pred:$p)>;
6799 def VST3LNqWB_register_Asm_16 :
6800 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6801 (ins VecListThreeQHWordIndexed:$list,
6802 addrmode6alignNone:$addr, rGPR:$Rm, pred:$p)>;
6803 def VST3LNqWB_register_Asm_32 :
6804 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6805 (ins VecListThreeQWordIndexed:$list, addrmode6alignNone:$addr,
6806 rGPR:$Rm, pred:$p)>;
6809 // VST3 multiple structure pseudo-instructions. These need special handling for
6810 // the vector operands that the normal instructions don't yet model.
6811 // FIXME: Remove these when the register classes and instructions are updated.
6812 def VST3dAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6813 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6814 def VST3dAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6815 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6816 def VST3dAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6817 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6818 def VST3qAsm_8 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr",
6819 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6820 def VST3qAsm_16 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr",
6821 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6822 def VST3qAsm_32 : NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr",
6823 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6825 def VST3dWB_fixed_Asm_8 :
6826 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6827 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6828 def VST3dWB_fixed_Asm_16 :
6829 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6830 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6831 def VST3dWB_fixed_Asm_32 :
6832 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6833 (ins VecListThreeD:$list, addrmode6align64:$addr, pred:$p)>;
6834 def VST3qWB_fixed_Asm_8 :
6835 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr!",
6836 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6837 def VST3qWB_fixed_Asm_16 :
6838 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr!",
6839 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6840 def VST3qWB_fixed_Asm_32 :
6841 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr!",
6842 (ins VecListThreeQ:$list, addrmode6align64:$addr, pred:$p)>;
6843 def VST3dWB_register_Asm_8 :
6844 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6845 (ins VecListThreeD:$list, addrmode6align64:$addr,
6846 rGPR:$Rm, pred:$p)>;
6847 def VST3dWB_register_Asm_16 :
6848 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6849 (ins VecListThreeD:$list, addrmode6align64:$addr,
6850 rGPR:$Rm, pred:$p)>;
6851 def VST3dWB_register_Asm_32 :
6852 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6853 (ins VecListThreeD:$list, addrmode6align64:$addr,
6854 rGPR:$Rm, pred:$p)>;
6855 def VST3qWB_register_Asm_8 :
6856 NEONDataTypeAsmPseudoInst<"vst3${p}", ".8", "$list, $addr, $Rm",
6857 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6858 rGPR:$Rm, pred:$p)>;
6859 def VST3qWB_register_Asm_16 :
6860 NEONDataTypeAsmPseudoInst<"vst3${p}", ".16", "$list, $addr, $Rm",
6861 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6862 rGPR:$Rm, pred:$p)>;
6863 def VST3qWB_register_Asm_32 :
6864 NEONDataTypeAsmPseudoInst<"vst3${p}", ".32", "$list, $addr, $Rm",
6865 (ins VecListThreeQ:$list, addrmode6align64:$addr,
6866 rGPR:$Rm, pred:$p)>;
6868 // VLD4 all-lanes pseudo-instructions. These need special handling for
6869 // the lane index that an InstAlias can't handle, so we use these instead.
6870 def VLD4DUPdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6871 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6873 def VLD4DUPdAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6874 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6876 def VLD4DUPdAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6877 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6879 def VLD4DUPqAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6880 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6882 def VLD4DUPqAsm_16: NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6883 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6885 def VLD4DUPqAsm_32: NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6886 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6889 def VLD4DUPdWB_fixed_Asm_8 :
6890 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6891 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6893 def VLD4DUPdWB_fixed_Asm_16 :
6894 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6895 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6897 def VLD4DUPdWB_fixed_Asm_32 :
6898 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6899 (ins VecListFourDAllLanes:$list, addrmode6dupalign64or128:$addr,
6901 def VLD4DUPqWB_fixed_Asm_8 :
6902 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6903 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6905 def VLD4DUPqWB_fixed_Asm_16 :
6906 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6907 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6909 def VLD4DUPqWB_fixed_Asm_32 :
6910 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6911 (ins VecListFourQAllLanes:$list, addrmode6dupalign64or128:$addr,
6913 def VLD4DUPdWB_register_Asm_8 :
6914 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6915 (ins VecListFourDAllLanes:$list, addrmode6dupalign32:$addr,
6916 rGPR:$Rm, pred:$p)>;
6917 def VLD4DUPdWB_register_Asm_16 :
6918 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6919 (ins VecListFourDAllLanes:$list, addrmode6dupalign64:$addr,
6920 rGPR:$Rm, pred:$p)>;
6921 def VLD4DUPdWB_register_Asm_32 :
6922 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6923 (ins VecListFourDAllLanes:$list,
6924 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
6925 def VLD4DUPqWB_register_Asm_8 :
6926 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6927 (ins VecListFourQAllLanes:$list, addrmode6dupalign32:$addr,
6928 rGPR:$Rm, pred:$p)>;
6929 def VLD4DUPqWB_register_Asm_16 :
6930 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6931 (ins VecListFourQAllLanes:$list, addrmode6dupalign64:$addr,
6932 rGPR:$Rm, pred:$p)>;
6933 def VLD4DUPqWB_register_Asm_32 :
6934 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6935 (ins VecListFourQAllLanes:$list,
6936 addrmode6dupalign64or128:$addr, rGPR:$Rm, pred:$p)>;
6939 // VLD4 single-lane pseudo-instructions. These need special handling for
6940 // the lane index that an InstAlias can't handle, so we use these instead.
6941 def VLD4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
6942 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6944 def VLD4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6945 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6947 def VLD4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6948 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
6950 def VLD4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
6951 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6953 def VLD4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
6954 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
6957 def VLD4LNdWB_fixed_Asm_8 :
6958 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
6959 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6961 def VLD4LNdWB_fixed_Asm_16 :
6962 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6963 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6965 def VLD4LNdWB_fixed_Asm_32 :
6966 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6967 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
6969 def VLD4LNqWB_fixed_Asm_16 :
6970 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
6971 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6973 def VLD4LNqWB_fixed_Asm_32 :
6974 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
6975 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
6977 def VLD4LNdWB_register_Asm_8 :
6978 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
6979 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
6980 rGPR:$Rm, pred:$p)>;
6981 def VLD4LNdWB_register_Asm_16 :
6982 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6983 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
6984 rGPR:$Rm, pred:$p)>;
6985 def VLD4LNdWB_register_Asm_32 :
6986 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6987 (ins VecListFourDWordIndexed:$list,
6988 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
6989 def VLD4LNqWB_register_Asm_16 :
6990 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
6991 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
6992 rGPR:$Rm, pred:$p)>;
6993 def VLD4LNqWB_register_Asm_32 :
6994 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
6995 (ins VecListFourQWordIndexed:$list,
6996 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7000 // VLD4 multiple structure pseudo-instructions. These need special handling for
7001 // the vector operands that the normal instructions don't yet model.
7002 // FIXME: Remove these when the register classes and instructions are updated.
7003 def VLD4dAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7004 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7006 def VLD4dAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7007 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7009 def VLD4dAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7010 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7012 def VLD4qAsm_8 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr",
7013 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7015 def VLD4qAsm_16 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr",
7016 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7018 def VLD4qAsm_32 : NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr",
7019 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7022 def VLD4dWB_fixed_Asm_8 :
7023 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7024 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7026 def VLD4dWB_fixed_Asm_16 :
7027 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7028 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7030 def VLD4dWB_fixed_Asm_32 :
7031 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7032 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7034 def VLD4qWB_fixed_Asm_8 :
7035 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr!",
7036 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7038 def VLD4qWB_fixed_Asm_16 :
7039 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr!",
7040 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7042 def VLD4qWB_fixed_Asm_32 :
7043 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr!",
7044 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7046 def VLD4dWB_register_Asm_8 :
7047 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7048 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7049 rGPR:$Rm, pred:$p)>;
7050 def VLD4dWB_register_Asm_16 :
7051 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7052 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7053 rGPR:$Rm, pred:$p)>;
7054 def VLD4dWB_register_Asm_32 :
7055 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7056 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7057 rGPR:$Rm, pred:$p)>;
7058 def VLD4qWB_register_Asm_8 :
7059 NEONDataTypeAsmPseudoInst<"vld4${p}", ".8", "$list, $addr, $Rm",
7060 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7061 rGPR:$Rm, pred:$p)>;
7062 def VLD4qWB_register_Asm_16 :
7063 NEONDataTypeAsmPseudoInst<"vld4${p}", ".16", "$list, $addr, $Rm",
7064 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7065 rGPR:$Rm, pred:$p)>;
7066 def VLD4qWB_register_Asm_32 :
7067 NEONDataTypeAsmPseudoInst<"vld4${p}", ".32", "$list, $addr, $Rm",
7068 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7069 rGPR:$Rm, pred:$p)>;
7071 // VST4 single-lane pseudo-instructions. These need special handling for
7072 // the lane index that an InstAlias can't handle, so we use these instead.
7073 def VST4LNdAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7074 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7076 def VST4LNdAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7077 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7079 def VST4LNdAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7080 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7082 def VST4LNqAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7083 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7085 def VST4LNqAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7086 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7089 def VST4LNdWB_fixed_Asm_8 :
7090 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7091 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7093 def VST4LNdWB_fixed_Asm_16 :
7094 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7095 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7097 def VST4LNdWB_fixed_Asm_32 :
7098 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7099 (ins VecListFourDWordIndexed:$list, addrmode6align64or128:$addr,
7101 def VST4LNqWB_fixed_Asm_16 :
7102 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7103 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7105 def VST4LNqWB_fixed_Asm_32 :
7106 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7107 (ins VecListFourQWordIndexed:$list, addrmode6align64or128:$addr,
7109 def VST4LNdWB_register_Asm_8 :
7110 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7111 (ins VecListFourDByteIndexed:$list, addrmode6align32:$addr,
7112 rGPR:$Rm, pred:$p)>;
7113 def VST4LNdWB_register_Asm_16 :
7114 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7115 (ins VecListFourDHWordIndexed:$list, addrmode6align64:$addr,
7116 rGPR:$Rm, pred:$p)>;
7117 def VST4LNdWB_register_Asm_32 :
7118 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7119 (ins VecListFourDWordIndexed:$list,
7120 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7121 def VST4LNqWB_register_Asm_16 :
7122 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7123 (ins VecListFourQHWordIndexed:$list, addrmode6align64:$addr,
7124 rGPR:$Rm, pred:$p)>;
7125 def VST4LNqWB_register_Asm_32 :
7126 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7127 (ins VecListFourQWordIndexed:$list,
7128 addrmode6align64or128:$addr, rGPR:$Rm, pred:$p)>;
7131 // VST4 multiple structure pseudo-instructions. These need special handling for
7132 // the vector operands that the normal instructions don't yet model.
7133 // FIXME: Remove these when the register classes and instructions are updated.
7134 def VST4dAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7135 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7137 def VST4dAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7138 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7140 def VST4dAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7141 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7143 def VST4qAsm_8 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr",
7144 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7146 def VST4qAsm_16 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr",
7147 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7149 def VST4qAsm_32 : NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr",
7150 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7153 def VST4dWB_fixed_Asm_8 :
7154 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7155 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7157 def VST4dWB_fixed_Asm_16 :
7158 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7159 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7161 def VST4dWB_fixed_Asm_32 :
7162 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7163 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7165 def VST4qWB_fixed_Asm_8 :
7166 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr!",
7167 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7169 def VST4qWB_fixed_Asm_16 :
7170 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr!",
7171 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7173 def VST4qWB_fixed_Asm_32 :
7174 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr!",
7175 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7177 def VST4dWB_register_Asm_8 :
7178 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7179 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7180 rGPR:$Rm, pred:$p)>;
7181 def VST4dWB_register_Asm_16 :
7182 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7183 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7184 rGPR:$Rm, pred:$p)>;
7185 def VST4dWB_register_Asm_32 :
7186 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7187 (ins VecListFourD:$list, addrmode6align64or128or256:$addr,
7188 rGPR:$Rm, pred:$p)>;
7189 def VST4qWB_register_Asm_8 :
7190 NEONDataTypeAsmPseudoInst<"vst4${p}", ".8", "$list, $addr, $Rm",
7191 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7192 rGPR:$Rm, pred:$p)>;
7193 def VST4qWB_register_Asm_16 :
7194 NEONDataTypeAsmPseudoInst<"vst4${p}", ".16", "$list, $addr, $Rm",
7195 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7196 rGPR:$Rm, pred:$p)>;
7197 def VST4qWB_register_Asm_32 :
7198 NEONDataTypeAsmPseudoInst<"vst4${p}", ".32", "$list, $addr, $Rm",
7199 (ins VecListFourQ:$list, addrmode6align64or128or256:$addr,
7200 rGPR:$Rm, pred:$p)>;
7202 // VMOV/VMVN takes an optional datatype suffix
7203 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7204 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
7205 defm : NEONDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
7206 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
7208 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7209 (VMVNd DPR:$Vd, DPR:$Vm, pred:$p)>;
7210 defm : NEONDTAnyInstAlias<"vmvn${p}", "$Vd, $Vm",
7211 (VMVNq QPR:$Vd, QPR:$Vm, pred:$p)>;
7213 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7214 // D-register versions.
7215 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
7216 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7217 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
7218 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7219 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
7220 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7221 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
7222 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7223 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
7224 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7225 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
7226 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7227 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
7228 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7229 // Q-register versions.
7230 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
7231 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7232 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
7233 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7234 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
7235 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7236 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
7237 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7238 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
7239 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7240 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
7241 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7242 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
7243 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7245 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
7246 // D-register versions.
7247 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
7248 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7249 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
7250 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7251 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
7252 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7253 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
7254 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7255 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
7256 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7257 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
7258 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7259 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
7260 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
7261 // Q-register versions.
7262 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
7263 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7264 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
7265 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7266 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
7267 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7268 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
7269 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7270 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
7271 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7272 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
7273 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7274 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
7275 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
7277 // VSWP allows, but does not require, a type suffix.
7278 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7279 (VSWPd DPR:$Vd, DPR:$Vm, pred:$p)>;
7280 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
7281 (VSWPq QPR:$Vd, QPR:$Vm, pred:$p)>;
7283 // VBIF, VBIT, and VBSL allow, but do not require, a type suffix.
7284 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7285 (VBIFd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7286 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7287 (VBITd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7288 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7289 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
7290 defm : NEONDTAnyInstAlias<"vbif${p}", "$Vd, $Vn, $Vm",
7291 (VBIFq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7292 defm : NEONDTAnyInstAlias<"vbit${p}", "$Vd, $Vn, $Vm",
7293 (VBITq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7294 defm : NEONDTAnyInstAlias<"vbsl${p}", "$Vd, $Vn, $Vm",
7295 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
7297 // "vmov Rd, #-imm" can be handled via "vmvn".
7298 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7299 (VMVNv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7300 def : NEONInstAlias<"vmov${p}.i32 $Vd, $imm",
7301 (VMVNv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7302 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7303 (VMOVv2i32 DPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7304 def : NEONInstAlias<"vmvn${p}.i32 $Vd, $imm",
7305 (VMOVv4i32 QPR:$Vd, nImmVMOVI32Neg:$imm, pred:$p)>;
7307 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
7308 // these should restrict to just the Q register variants, but the register
7309 // classes are enough to match correctly regardless, so we keep it simple
7310 // and just use MnemonicAlias.
7311 def : NEONMnemonicAlias<"vbicq", "vbic">;
7312 def : NEONMnemonicAlias<"vandq", "vand">;
7313 def : NEONMnemonicAlias<"veorq", "veor">;
7314 def : NEONMnemonicAlias<"vorrq", "vorr">;
7316 def : NEONMnemonicAlias<"vmovq", "vmov">;
7317 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
7318 // Explicit versions for floating point so that the FPImm variants get
7319 // handled early. The parser gets confused otherwise.
7320 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
7321 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
7323 def : NEONMnemonicAlias<"vaddq", "vadd">;
7324 def : NEONMnemonicAlias<"vsubq", "vsub">;
7326 def : NEONMnemonicAlias<"vminq", "vmin">;
7327 def : NEONMnemonicAlias<"vmaxq", "vmax">;
7329 def : NEONMnemonicAlias<"vmulq", "vmul">;
7331 def : NEONMnemonicAlias<"vabsq", "vabs">;
7333 def : NEONMnemonicAlias<"vshlq", "vshl">;
7334 def : NEONMnemonicAlias<"vshrq", "vshr">;
7336 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
7338 def : NEONMnemonicAlias<"vcleq", "vcle">;
7339 def : NEONMnemonicAlias<"vceqq", "vceq">;
7341 def : NEONMnemonicAlias<"vzipq", "vzip">;
7342 def : NEONMnemonicAlias<"vswpq", "vswp">;
7344 def : NEONMnemonicAlias<"vrecpeq.f32", "vrecpe.f32">;
7345 def : NEONMnemonicAlias<"vrecpeq.u32", "vrecpe.u32">;
7348 // Alias for loading floating point immediates that aren't representable
7349 // using the vmov.f32 encoding but the bitpattern is representable using
7350 // the .i32 encoding.
7351 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7352 (VMOVv4i32 QPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;
7353 def : NEONInstAlias<"vmov${p}.f32 $Vd, $imm",
7354 (VMOVv2i32 DPR:$Vd, nImmVMOVI32:$imm, pred:$p)>;