1 //===- ARMInstrNEON.td - NEON support for ARM -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the ARM NEON instruction set.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // NEON-specific Operands.
17 //===----------------------------------------------------------------------===//
18 def nModImm : Operand<i32> {
19 let PrintMethod = "printNEONModImmOperand";
22 def nImmSplatI8AsmOperand : AsmOperandClass { let Name = "NEONi8splat"; }
23 def nImmSplatI8 : Operand<i32> {
24 let PrintMethod = "printNEONModImmOperand";
25 let ParserMatchClass = nImmSplatI8AsmOperand;
27 def nImmSplatI16AsmOperand : AsmOperandClass { let Name = "NEONi16splat"; }
28 def nImmSplatI16 : Operand<i32> {
29 let PrintMethod = "printNEONModImmOperand";
30 let ParserMatchClass = nImmSplatI16AsmOperand;
32 def nImmSplatI32AsmOperand : AsmOperandClass { let Name = "NEONi32splat"; }
33 def nImmSplatI32 : Operand<i32> {
34 let PrintMethod = "printNEONModImmOperand";
35 let ParserMatchClass = nImmSplatI32AsmOperand;
37 def nImmVMOVI32AsmOperand : AsmOperandClass { let Name = "NEONi32vmov"; }
38 def nImmVMOVI32 : Operand<i32> {
39 let PrintMethod = "printNEONModImmOperand";
40 let ParserMatchClass = nImmVMOVI32AsmOperand;
42 def nImmVMOVF32 : Operand<i32> {
43 let PrintMethod = "printFPImmOperand";
44 let ParserMatchClass = FPImmOperand;
46 def nImmSplatI64AsmOperand : AsmOperandClass { let Name = "NEONi64splat"; }
47 def nImmSplatI64 : Operand<i32> {
48 let PrintMethod = "printNEONModImmOperand";
49 let ParserMatchClass = nImmSplatI64AsmOperand;
52 def VectorIndex8Operand : AsmOperandClass { let Name = "VectorIndex8"; }
53 def VectorIndex16Operand : AsmOperandClass { let Name = "VectorIndex16"; }
54 def VectorIndex32Operand : AsmOperandClass { let Name = "VectorIndex32"; }
55 def VectorIndex8 : Operand<i32>, ImmLeaf<i32, [{
56 return ((uint64_t)Imm) < 8;
58 let ParserMatchClass = VectorIndex8Operand;
59 let PrintMethod = "printVectorIndex";
60 let MIOperandInfo = (ops i32imm);
62 def VectorIndex16 : Operand<i32>, ImmLeaf<i32, [{
63 return ((uint64_t)Imm) < 4;
65 let ParserMatchClass = VectorIndex16Operand;
66 let PrintMethod = "printVectorIndex";
67 let MIOperandInfo = (ops i32imm);
69 def VectorIndex32 : Operand<i32>, ImmLeaf<i32, [{
70 return ((uint64_t)Imm) < 2;
72 let ParserMatchClass = VectorIndex32Operand;
73 let PrintMethod = "printVectorIndex";
74 let MIOperandInfo = (ops i32imm);
77 // Register list of one D register.
78 def VecListOneDAsmOperand : AsmOperandClass {
79 let Name = "VecListOneD";
80 let ParserMethod = "parseVectorList";
81 let RenderMethod = "addVecListOperands";
83 def VecListOneD : RegisterOperand<DPR, "printVectorListOne"> {
84 let ParserMatchClass = VecListOneDAsmOperand;
86 // Register list of two sequential D registers.
87 def VecListTwoDAsmOperand : AsmOperandClass {
88 let Name = "VecListTwoD";
89 let ParserMethod = "parseVectorList";
90 let RenderMethod = "addVecListOperands";
92 def VecListTwoD : RegisterOperand<DPR, "printVectorListTwo"> {
93 let ParserMatchClass = VecListTwoDAsmOperand;
95 // Register list of three sequential D registers.
96 def VecListThreeDAsmOperand : AsmOperandClass {
97 let Name = "VecListThreeD";
98 let ParserMethod = "parseVectorList";
99 let RenderMethod = "addVecListOperands";
101 def VecListThreeD : RegisterOperand<DPR, "printVectorListThree"> {
102 let ParserMatchClass = VecListThreeDAsmOperand;
104 // Register list of four sequential D registers.
105 def VecListFourDAsmOperand : AsmOperandClass {
106 let Name = "VecListFourD";
107 let ParserMethod = "parseVectorList";
108 let RenderMethod = "addVecListOperands";
110 def VecListFourD : RegisterOperand<DPR, "printVectorListFour"> {
111 let ParserMatchClass = VecListFourDAsmOperand;
113 // Register list of two D registers spaced by 2 (two sequential Q registers).
114 def VecListTwoQAsmOperand : AsmOperandClass {
115 let Name = "VecListTwoQ";
116 let ParserMethod = "parseVectorList";
117 let RenderMethod = "addVecListOperands";
119 def VecListTwoQ : RegisterOperand<DPR, "printVectorListTwoSpaced"> {
120 let ParserMatchClass = VecListTwoQAsmOperand;
123 // Register list of one D register, with "all lanes" subscripting.
124 def VecListOneDAllLanesAsmOperand : AsmOperandClass {
125 let Name = "VecListOneDAllLanes";
126 let ParserMethod = "parseVectorList";
127 let RenderMethod = "addVecListOperands";
129 def VecListOneDAllLanes : RegisterOperand<DPR, "printVectorListOneAllLanes"> {
130 let ParserMatchClass = VecListOneDAllLanesAsmOperand;
132 // Register list of two D registers, with "all lanes" subscripting.
133 def VecListTwoDAllLanesAsmOperand : AsmOperandClass {
134 let Name = "VecListTwoDAllLanes";
135 let ParserMethod = "parseVectorList";
136 let RenderMethod = "addVecListOperands";
138 def VecListTwoDAllLanes : RegisterOperand<DPR, "printVectorListTwoAllLanes"> {
139 let ParserMatchClass = VecListTwoDAllLanesAsmOperand;
142 // Register list of one D register, with byte lane subscripting.
143 def VecListOneDByteIndexAsmOperand : AsmOperandClass {
144 let Name = "VecListOneDByteIndexed";
145 let ParserMethod = "parseVectorList";
146 let RenderMethod = "addVecListIndexedOperands";
148 def VecListOneDByteIndexed : Operand<i32> {
149 let ParserMatchClass = VecListOneDByteIndexAsmOperand;
150 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
152 // ...with half-word lane subscripting.
153 def VecListOneDHWordIndexAsmOperand : AsmOperandClass {
154 let Name = "VecListOneDHWordIndexed";
155 let ParserMethod = "parseVectorList";
156 let RenderMethod = "addVecListIndexedOperands";
158 def VecListOneDHWordIndexed : Operand<i32> {
159 let ParserMatchClass = VecListOneDHWordIndexAsmOperand;
160 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
162 // ...with word lane subscripting.
163 def VecListOneDWordIndexAsmOperand : AsmOperandClass {
164 let Name = "VecListOneDWordIndexed";
165 let ParserMethod = "parseVectorList";
166 let RenderMethod = "addVecListIndexedOperands";
168 def VecListOneDWordIndexed : Operand<i32> {
169 let ParserMatchClass = VecListOneDWordIndexAsmOperand;
170 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
172 // Register list of two D registers, with byte lane subscripting.
173 def VecListTwoDByteIndexAsmOperand : AsmOperandClass {
174 let Name = "VecListTwoDByteIndexed";
175 let ParserMethod = "parseVectorList";
176 let RenderMethod = "addVecListIndexedOperands";
178 def VecListTwoDByteIndexed : Operand<i32> {
179 let ParserMatchClass = VecListTwoDByteIndexAsmOperand;
180 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
182 // ...with half-word lane subscripting.
183 def VecListTwoDHWordIndexAsmOperand : AsmOperandClass {
184 let Name = "VecListTwoDHWordIndexed";
185 let ParserMethod = "parseVectorList";
186 let RenderMethod = "addVecListIndexedOperands";
188 def VecListTwoDHWordIndexed : Operand<i32> {
189 let ParserMatchClass = VecListTwoDHWordIndexAsmOperand;
190 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
192 // ...with word lane subscripting.
193 def VecListTwoDWordIndexAsmOperand : AsmOperandClass {
194 let Name = "VecListTwoDWordIndexed";
195 let ParserMethod = "parseVectorList";
196 let RenderMethod = "addVecListIndexedOperands";
198 def VecListTwoDWordIndexed : Operand<i32> {
199 let ParserMatchClass = VecListTwoDWordIndexAsmOperand;
200 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
203 //===----------------------------------------------------------------------===//
204 // NEON-specific DAG Nodes.
205 //===----------------------------------------------------------------------===//
207 def SDTARMVCMP : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<1, 2>]>;
208 def SDTARMVCMPZ : SDTypeProfile<1, 1, []>;
210 def NEONvceq : SDNode<"ARMISD::VCEQ", SDTARMVCMP>;
211 def NEONvceqz : SDNode<"ARMISD::VCEQZ", SDTARMVCMPZ>;
212 def NEONvcge : SDNode<"ARMISD::VCGE", SDTARMVCMP>;
213 def NEONvcgez : SDNode<"ARMISD::VCGEZ", SDTARMVCMPZ>;
214 def NEONvclez : SDNode<"ARMISD::VCLEZ", SDTARMVCMPZ>;
215 def NEONvcgeu : SDNode<"ARMISD::VCGEU", SDTARMVCMP>;
216 def NEONvcgt : SDNode<"ARMISD::VCGT", SDTARMVCMP>;
217 def NEONvcgtz : SDNode<"ARMISD::VCGTZ", SDTARMVCMPZ>;
218 def NEONvcltz : SDNode<"ARMISD::VCLTZ", SDTARMVCMPZ>;
219 def NEONvcgtu : SDNode<"ARMISD::VCGTU", SDTARMVCMP>;
220 def NEONvtst : SDNode<"ARMISD::VTST", SDTARMVCMP>;
222 // Types for vector shift by immediates. The "SHX" version is for long and
223 // narrow operations where the source and destination vectors have different
224 // types. The "SHINS" version is for shift and insert operations.
225 def SDTARMVSH : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
227 def SDTARMVSHX : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
229 def SDTARMVSHINS : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
230 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
232 def NEONvshl : SDNode<"ARMISD::VSHL", SDTARMVSH>;
233 def NEONvshrs : SDNode<"ARMISD::VSHRs", SDTARMVSH>;
234 def NEONvshru : SDNode<"ARMISD::VSHRu", SDTARMVSH>;
235 def NEONvshlls : SDNode<"ARMISD::VSHLLs", SDTARMVSHX>;
236 def NEONvshllu : SDNode<"ARMISD::VSHLLu", SDTARMVSHX>;
237 def NEONvshlli : SDNode<"ARMISD::VSHLLi", SDTARMVSHX>;
238 def NEONvshrn : SDNode<"ARMISD::VSHRN", SDTARMVSHX>;
240 def NEONvrshrs : SDNode<"ARMISD::VRSHRs", SDTARMVSH>;
241 def NEONvrshru : SDNode<"ARMISD::VRSHRu", SDTARMVSH>;
242 def NEONvrshrn : SDNode<"ARMISD::VRSHRN", SDTARMVSHX>;
244 def NEONvqshls : SDNode<"ARMISD::VQSHLs", SDTARMVSH>;
245 def NEONvqshlu : SDNode<"ARMISD::VQSHLu", SDTARMVSH>;
246 def NEONvqshlsu : SDNode<"ARMISD::VQSHLsu", SDTARMVSH>;
247 def NEONvqshrns : SDNode<"ARMISD::VQSHRNs", SDTARMVSHX>;
248 def NEONvqshrnu : SDNode<"ARMISD::VQSHRNu", SDTARMVSHX>;
249 def NEONvqshrnsu : SDNode<"ARMISD::VQSHRNsu", SDTARMVSHX>;
251 def NEONvqrshrns : SDNode<"ARMISD::VQRSHRNs", SDTARMVSHX>;
252 def NEONvqrshrnu : SDNode<"ARMISD::VQRSHRNu", SDTARMVSHX>;
253 def NEONvqrshrnsu : SDNode<"ARMISD::VQRSHRNsu", SDTARMVSHX>;
255 def NEONvsli : SDNode<"ARMISD::VSLI", SDTARMVSHINS>;
256 def NEONvsri : SDNode<"ARMISD::VSRI", SDTARMVSHINS>;
258 def SDTARMVGETLN : SDTypeProfile<1, 2, [SDTCisVT<0, i32>, SDTCisInt<1>,
260 def NEONvgetlaneu : SDNode<"ARMISD::VGETLANEu", SDTARMVGETLN>;
261 def NEONvgetlanes : SDNode<"ARMISD::VGETLANEs", SDTARMVGETLN>;
263 def SDTARMVMOVIMM : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisVT<1, i32>]>;
264 def NEONvmovImm : SDNode<"ARMISD::VMOVIMM", SDTARMVMOVIMM>;
265 def NEONvmvnImm : SDNode<"ARMISD::VMVNIMM", SDTARMVMOVIMM>;
266 def NEONvmovFPImm : SDNode<"ARMISD::VMOVFPIMM", SDTARMVMOVIMM>;
268 def SDTARMVORRIMM : SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
270 def NEONvorrImm : SDNode<"ARMISD::VORRIMM", SDTARMVORRIMM>;
271 def NEONvbicImm : SDNode<"ARMISD::VBICIMM", SDTARMVORRIMM>;
273 def NEONvbsl : SDNode<"ARMISD::VBSL",
274 SDTypeProfile<1, 3, [SDTCisVec<0>,
277 SDTCisSameAs<0, 3>]>>;
279 def NEONvdup : SDNode<"ARMISD::VDUP", SDTypeProfile<1, 1, [SDTCisVec<0>]>>;
281 // VDUPLANE can produce a quad-register result from a double-register source,
282 // so the result is not constrained to match the source.
283 def NEONvduplane : SDNode<"ARMISD::VDUPLANE",
284 SDTypeProfile<1, 2, [SDTCisVec<0>, SDTCisVec<1>,
287 def SDTARMVEXT : SDTypeProfile<1, 3, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
288 SDTCisSameAs<0, 2>, SDTCisVT<3, i32>]>;
289 def NEONvext : SDNode<"ARMISD::VEXT", SDTARMVEXT>;
291 def SDTARMVSHUF : SDTypeProfile<1, 1, [SDTCisVec<0>, SDTCisSameAs<0, 1>]>;
292 def NEONvrev64 : SDNode<"ARMISD::VREV64", SDTARMVSHUF>;
293 def NEONvrev32 : SDNode<"ARMISD::VREV32", SDTARMVSHUF>;
294 def NEONvrev16 : SDNode<"ARMISD::VREV16", SDTARMVSHUF>;
296 def SDTARMVSHUF2 : SDTypeProfile<2, 2, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
298 SDTCisSameAs<0, 3>]>;
299 def NEONzip : SDNode<"ARMISD::VZIP", SDTARMVSHUF2>;
300 def NEONuzp : SDNode<"ARMISD::VUZP", SDTARMVSHUF2>;
301 def NEONtrn : SDNode<"ARMISD::VTRN", SDTARMVSHUF2>;
303 def SDTARMVMULL : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>,
304 SDTCisSameAs<1, 2>]>;
305 def NEONvmulls : SDNode<"ARMISD::VMULLs", SDTARMVMULL>;
306 def NEONvmullu : SDNode<"ARMISD::VMULLu", SDTARMVMULL>;
308 def SDTARMFMAX : SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisSameAs<0, 1>,
309 SDTCisSameAs<0, 2>]>;
310 def NEONfmax : SDNode<"ARMISD::FMAX", SDTARMFMAX>;
311 def NEONfmin : SDNode<"ARMISD::FMIN", SDTARMFMAX>;
313 def NEONimmAllZerosV: PatLeaf<(NEONvmovImm (i32 timm)), [{
314 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
315 unsigned EltBits = 0;
316 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
317 return (EltBits == 32 && EltVal == 0);
320 def NEONimmAllOnesV: PatLeaf<(NEONvmovImm (i32 timm)), [{
321 ConstantSDNode *ConstVal = cast<ConstantSDNode>(N->getOperand(0));
322 unsigned EltBits = 0;
323 uint64_t EltVal = ARM_AM::decodeNEONModImm(ConstVal->getZExtValue(), EltBits);
324 return (EltBits == 8 && EltVal == 0xff);
327 //===----------------------------------------------------------------------===//
328 // NEON load / store instructions
329 //===----------------------------------------------------------------------===//
331 // Use VLDM to load a Q register as a D register pair.
332 // This is a pseudo instruction that is expanded to VLDMD after reg alloc.
334 : PseudoVFPLdStM<(outs QPR:$dst), (ins GPR:$Rn),
336 [(set QPR:$dst, (v2f64 (load GPR:$Rn)))]>;
338 // Use VSTM to store a Q register as a D register pair.
339 // This is a pseudo instruction that is expanded to VSTMD after reg alloc.
341 : PseudoVFPLdStM<(outs), (ins QPR:$src, GPR:$Rn),
343 [(store (v2f64 QPR:$src), GPR:$Rn)]>;
345 // Classes for VLD* pseudo-instructions with multi-register operands.
346 // These are expanded to real instructions after register allocation.
347 class VLDQPseudo<InstrItinClass itin>
348 : PseudoNLdSt<(outs QPR:$dst), (ins addrmode6:$addr), itin, "">;
349 class VLDQWBPseudo<InstrItinClass itin>
350 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
351 (ins addrmode6:$addr, am6offset:$offset), itin,
353 class VLDQWBfixedPseudo<InstrItinClass itin>
354 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
355 (ins addrmode6:$addr), itin,
357 class VLDQWBregisterPseudo<InstrItinClass itin>
358 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
359 (ins addrmode6:$addr, rGPR:$offset), itin,
362 class VLDQQPseudo<InstrItinClass itin>
363 : PseudoNLdSt<(outs QQPR:$dst), (ins addrmode6:$addr), itin, "">;
364 class VLDQQWBPseudo<InstrItinClass itin>
365 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
366 (ins addrmode6:$addr, am6offset:$offset), itin,
368 class VLDQQWBfixedPseudo<InstrItinClass itin>
369 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
370 (ins addrmode6:$addr), itin,
372 class VLDQQWBregisterPseudo<InstrItinClass itin>
373 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
374 (ins addrmode6:$addr, rGPR:$offset), itin,
378 class VLDQQQQPseudo<InstrItinClass itin>
379 : PseudoNLdSt<(outs QQQQPR:$dst), (ins addrmode6:$addr, QQQQPR:$src),itin,
381 class VLDQQQQWBPseudo<InstrItinClass itin>
382 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
383 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
384 "$addr.addr = $wb, $src = $dst">;
386 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
388 // VLD1 : Vector Load (multiple single elements)
389 class VLD1D<bits<4> op7_4, string Dt>
390 : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd),
391 (ins addrmode6:$Rn), IIC_VLD1,
392 "vld1", Dt, "$Vd, $Rn", "", []> {
395 let DecoderMethod = "DecodeVLDInstruction";
397 class VLD1Q<bits<4> op7_4, string Dt>
398 : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd),
399 (ins addrmode6:$Rn), IIC_VLD1x2,
400 "vld1", Dt, "$Vd, $Rn", "", []> {
402 let Inst{5-4} = Rn{5-4};
403 let DecoderMethod = "DecodeVLDInstruction";
406 def VLD1d8 : VLD1D<{0,0,0,?}, "8">;
407 def VLD1d16 : VLD1D<{0,1,0,?}, "16">;
408 def VLD1d32 : VLD1D<{1,0,0,?}, "32">;
409 def VLD1d64 : VLD1D<{1,1,0,?}, "64">;
411 def VLD1q8 : VLD1Q<{0,0,?,?}, "8">;
412 def VLD1q16 : VLD1Q<{0,1,?,?}, "16">;
413 def VLD1q32 : VLD1Q<{1,0,?,?}, "32">;
414 def VLD1q64 : VLD1Q<{1,1,?,?}, "64">;
416 def VLD1q8Pseudo : VLDQPseudo<IIC_VLD1x2>;
417 def VLD1q16Pseudo : VLDQPseudo<IIC_VLD1x2>;
418 def VLD1q32Pseudo : VLDQPseudo<IIC_VLD1x2>;
419 def VLD1q64Pseudo : VLDQPseudo<IIC_VLD1x2>;
421 // ...with address register writeback:
422 multiclass VLD1DWB<bits<4> op7_4, string Dt> {
423 def _fixed : NLdSt<0,0b10, 0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
424 (ins addrmode6:$Rn), IIC_VLD1u,
425 "vld1", Dt, "$Vd, $Rn!",
426 "$Rn.addr = $wb", []> {
427 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
429 let DecoderMethod = "DecodeVLDInstruction";
430 let AsmMatchConverter = "cvtVLDwbFixed";
432 def _register : NLdSt<0,0b10,0b0111,op7_4, (outs VecListOneD:$Vd, GPR:$wb),
433 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
434 "vld1", Dt, "$Vd, $Rn, $Rm",
435 "$Rn.addr = $wb", []> {
437 let DecoderMethod = "DecodeVLDInstruction";
438 let AsmMatchConverter = "cvtVLDwbRegister";
441 multiclass VLD1QWB<bits<4> op7_4, string Dt> {
442 def _fixed : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
443 (ins addrmode6:$Rn), IIC_VLD1x2u,
444 "vld1", Dt, "$Vd, $Rn!",
445 "$Rn.addr = $wb", []> {
446 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
447 let Inst{5-4} = Rn{5-4};
448 let DecoderMethod = "DecodeVLDInstruction";
449 let AsmMatchConverter = "cvtVLDwbFixed";
451 def _register : NLdSt<0,0b10,0b1010,op7_4, (outs VecListTwoD:$Vd, GPR:$wb),
452 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
453 "vld1", Dt, "$Vd, $Rn, $Rm",
454 "$Rn.addr = $wb", []> {
455 let Inst{5-4} = Rn{5-4};
456 let DecoderMethod = "DecodeVLDInstruction";
457 let AsmMatchConverter = "cvtVLDwbRegister";
461 defm VLD1d8wb : VLD1DWB<{0,0,0,?}, "8">;
462 defm VLD1d16wb : VLD1DWB<{0,1,0,?}, "16">;
463 defm VLD1d32wb : VLD1DWB<{1,0,0,?}, "32">;
464 defm VLD1d64wb : VLD1DWB<{1,1,0,?}, "64">;
465 defm VLD1q8wb : VLD1QWB<{0,0,?,?}, "8">;
466 defm VLD1q16wb : VLD1QWB<{0,1,?,?}, "16">;
467 defm VLD1q32wb : VLD1QWB<{1,0,?,?}, "32">;
468 defm VLD1q64wb : VLD1QWB<{1,1,?,?}, "64">;
470 def VLD1q8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
471 def VLD1q16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
472 def VLD1q32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
473 def VLD1q64PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1x2u>;
474 def VLD1q8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
475 def VLD1q16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
476 def VLD1q32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
477 def VLD1q64PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1x2u>;
479 // ...with 3 registers
480 class VLD1D3<bits<4> op7_4, string Dt>
481 : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd),
482 (ins addrmode6:$Rn), IIC_VLD1x3, "vld1", Dt,
483 "$Vd, $Rn", "", []> {
486 let DecoderMethod = "DecodeVLDInstruction";
488 multiclass VLD1D3WB<bits<4> op7_4, string Dt> {
489 def _fixed : NLdSt<0,0b10,0b0110, op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
490 (ins addrmode6:$Rn), IIC_VLD1x2u,
491 "vld1", Dt, "$Vd, $Rn!",
492 "$Rn.addr = $wb", []> {
493 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
495 let DecoderMethod = "DecodeVLDInstruction";
496 let AsmMatchConverter = "cvtVLDwbFixed";
498 def _register : NLdSt<0,0b10,0b0110,op7_4, (outs VecListThreeD:$Vd, GPR:$wb),
499 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
500 "vld1", Dt, "$Vd, $Rn, $Rm",
501 "$Rn.addr = $wb", []> {
503 let DecoderMethod = "DecodeVLDInstruction";
504 let AsmMatchConverter = "cvtVLDwbRegister";
508 def VLD1d8T : VLD1D3<{0,0,0,?}, "8">;
509 def VLD1d16T : VLD1D3<{0,1,0,?}, "16">;
510 def VLD1d32T : VLD1D3<{1,0,0,?}, "32">;
511 def VLD1d64T : VLD1D3<{1,1,0,?}, "64">;
513 defm VLD1d8Twb : VLD1D3WB<{0,0,0,?}, "8">;
514 defm VLD1d16Twb : VLD1D3WB<{0,1,0,?}, "16">;
515 defm VLD1d32Twb : VLD1D3WB<{1,0,0,?}, "32">;
516 defm VLD1d64Twb : VLD1D3WB<{1,1,0,?}, "64">;
518 def VLD1d64TPseudo : VLDQQPseudo<IIC_VLD1x3>;
520 // ...with 4 registers
521 class VLD1D4<bits<4> op7_4, string Dt>
522 : NLdSt<0, 0b10, 0b0010, op7_4, (outs VecListFourD:$Vd),
523 (ins addrmode6:$Rn), IIC_VLD1x4, "vld1", Dt,
524 "$Vd, $Rn", "", []> {
526 let Inst{5-4} = Rn{5-4};
527 let DecoderMethod = "DecodeVLDInstruction";
529 multiclass VLD1D4WB<bits<4> op7_4, string Dt> {
530 def _fixed : NLdSt<0,0b10,0b0010, op7_4, (outs VecListFourD:$Vd, GPR:$wb),
531 (ins addrmode6:$Rn), IIC_VLD1x2u,
532 "vld1", Dt, "$Vd, $Rn!",
533 "$Rn.addr = $wb", []> {
534 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
535 let Inst{5-4} = Rn{5-4};
536 let DecoderMethod = "DecodeVLDInstruction";
537 let AsmMatchConverter = "cvtVLDwbFixed";
539 def _register : NLdSt<0,0b10,0b0010,op7_4, (outs VecListFourD:$Vd, GPR:$wb),
540 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
541 "vld1", Dt, "$Vd, $Rn, $Rm",
542 "$Rn.addr = $wb", []> {
543 let Inst{5-4} = Rn{5-4};
544 let DecoderMethod = "DecodeVLDInstruction";
545 let AsmMatchConverter = "cvtVLDwbRegister";
549 def VLD1d8Q : VLD1D4<{0,0,?,?}, "8">;
550 def VLD1d16Q : VLD1D4<{0,1,?,?}, "16">;
551 def VLD1d32Q : VLD1D4<{1,0,?,?}, "32">;
552 def VLD1d64Q : VLD1D4<{1,1,?,?}, "64">;
554 defm VLD1d8Qwb : VLD1D4WB<{0,0,?,?}, "8">;
555 defm VLD1d16Qwb : VLD1D4WB<{0,1,?,?}, "16">;
556 defm VLD1d32Qwb : VLD1D4WB<{1,0,?,?}, "32">;
557 defm VLD1d64Qwb : VLD1D4WB<{1,1,?,?}, "64">;
559 def VLD1d64QPseudo : VLDQQPseudo<IIC_VLD1x4>;
561 // VLD2 : Vector Load (multiple 2-element structures)
562 class VLD2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
564 : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd),
565 (ins addrmode6:$Rn), itin,
566 "vld2", Dt, "$Vd, $Rn", "", []> {
568 let Inst{5-4} = Rn{5-4};
569 let DecoderMethod = "DecodeVLDInstruction";
572 def VLD2d8 : VLD2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2>;
573 def VLD2d16 : VLD2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2>;
574 def VLD2d32 : VLD2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2>;
576 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2>;
577 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2>;
578 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2>;
580 def VLD2d8Pseudo : VLDQPseudo<IIC_VLD2>;
581 def VLD2d16Pseudo : VLDQPseudo<IIC_VLD2>;
582 def VLD2d32Pseudo : VLDQPseudo<IIC_VLD2>;
584 def VLD2q8Pseudo : VLDQQPseudo<IIC_VLD2x2>;
585 def VLD2q16Pseudo : VLDQQPseudo<IIC_VLD2x2>;
586 def VLD2q32Pseudo : VLDQQPseudo<IIC_VLD2x2>;
588 // ...with address register writeback:
589 multiclass VLD2WB<bits<4> op11_8, bits<4> op7_4, string Dt,
590 RegisterOperand VdTy, InstrItinClass itin> {
591 def _fixed : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
592 (ins addrmode6:$Rn), itin,
593 "vld2", Dt, "$Vd, $Rn!",
594 "$Rn.addr = $wb", []> {
595 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
596 let Inst{5-4} = Rn{5-4};
597 let DecoderMethod = "DecodeVLDInstruction";
598 let AsmMatchConverter = "cvtVLDwbFixed";
600 def _register : NLdSt<0, 0b10, op11_8, op7_4, (outs VdTy:$Vd, GPR:$wb),
601 (ins addrmode6:$Rn, rGPR:$Rm), itin,
602 "vld2", Dt, "$Vd, $Rn, $Rm",
603 "$Rn.addr = $wb", []> {
604 let Inst{5-4} = Rn{5-4};
605 let DecoderMethod = "DecodeVLDInstruction";
606 let AsmMatchConverter = "cvtVLDwbRegister";
610 defm VLD2d8wb : VLD2WB<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VLD2u>;
611 defm VLD2d16wb : VLD2WB<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VLD2u>;
612 defm VLD2d32wb : VLD2WB<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VLD2u>;
614 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u>;
615 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u>;
616 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u>;
618 def VLD2d8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
619 def VLD2d16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
620 def VLD2d32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD2u>;
621 def VLD2d8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
622 def VLD2d16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
623 def VLD2d32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD2u>;
625 def VLD2q8PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
626 def VLD2q16PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
627 def VLD2q32PseudoWB_fixed : VLDQQWBfixedPseudo<IIC_VLD2x2u>;
628 def VLD2q8PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
629 def VLD2q16PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
630 def VLD2q32PseudoWB_register : VLDQQWBregisterPseudo<IIC_VLD2x2u>;
632 // ...with double-spaced registers
633 def VLD2b8 : VLD2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2>;
634 def VLD2b16 : VLD2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2>;
635 def VLD2b32 : VLD2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2>;
636 defm VLD2b8wb : VLD2WB<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VLD2u>;
637 defm VLD2b16wb : VLD2WB<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VLD2u>;
638 defm VLD2b32wb : VLD2WB<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VLD2u>;
640 // VLD3 : Vector Load (multiple 3-element structures)
641 class VLD3D<bits<4> op11_8, bits<4> op7_4, string Dt>
642 : NLdSt<0, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
643 (ins addrmode6:$Rn), IIC_VLD3,
644 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn", "", []> {
647 let DecoderMethod = "DecodeVLDInstruction";
650 def VLD3d8 : VLD3D<0b0100, {0,0,0,?}, "8">;
651 def VLD3d16 : VLD3D<0b0100, {0,1,0,?}, "16">;
652 def VLD3d32 : VLD3D<0b0100, {1,0,0,?}, "32">;
654 def VLD3d8Pseudo : VLDQQPseudo<IIC_VLD3>;
655 def VLD3d16Pseudo : VLDQQPseudo<IIC_VLD3>;
656 def VLD3d32Pseudo : VLDQQPseudo<IIC_VLD3>;
658 // ...with address register writeback:
659 class VLD3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
660 : NLdSt<0, 0b10, op11_8, op7_4,
661 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
662 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD3u,
663 "vld3", Dt, "\\{$Vd, $dst2, $dst3\\}, $Rn$Rm",
664 "$Rn.addr = $wb", []> {
666 let DecoderMethod = "DecodeVLDInstruction";
669 def VLD3d8_UPD : VLD3DWB<0b0100, {0,0,0,?}, "8">;
670 def VLD3d16_UPD : VLD3DWB<0b0100, {0,1,0,?}, "16">;
671 def VLD3d32_UPD : VLD3DWB<0b0100, {1,0,0,?}, "32">;
673 def VLD3d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
674 def VLD3d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
675 def VLD3d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3u>;
677 // ...with double-spaced registers:
678 def VLD3q8 : VLD3D<0b0101, {0,0,0,?}, "8">;
679 def VLD3q16 : VLD3D<0b0101, {0,1,0,?}, "16">;
680 def VLD3q32 : VLD3D<0b0101, {1,0,0,?}, "32">;
681 def VLD3q8_UPD : VLD3DWB<0b0101, {0,0,0,?}, "8">;
682 def VLD3q16_UPD : VLD3DWB<0b0101, {0,1,0,?}, "16">;
683 def VLD3q32_UPD : VLD3DWB<0b0101, {1,0,0,?}, "32">;
685 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
686 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
687 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
689 // ...alternate versions to be allocated odd register numbers:
690 def VLD3q8oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
691 def VLD3q16oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
692 def VLD3q32oddPseudo : VLDQQQQPseudo<IIC_VLD3>;
694 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
695 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
696 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD3u>;
698 // VLD4 : Vector Load (multiple 4-element structures)
699 class VLD4D<bits<4> op11_8, bits<4> op7_4, string Dt>
700 : NLdSt<0, 0b10, op11_8, op7_4,
701 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
702 (ins addrmode6:$Rn), IIC_VLD4,
703 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn", "", []> {
705 let Inst{5-4} = Rn{5-4};
706 let DecoderMethod = "DecodeVLDInstruction";
709 def VLD4d8 : VLD4D<0b0000, {0,0,?,?}, "8">;
710 def VLD4d16 : VLD4D<0b0000, {0,1,?,?}, "16">;
711 def VLD4d32 : VLD4D<0b0000, {1,0,?,?}, "32">;
713 def VLD4d8Pseudo : VLDQQPseudo<IIC_VLD4>;
714 def VLD4d16Pseudo : VLDQQPseudo<IIC_VLD4>;
715 def VLD4d32Pseudo : VLDQQPseudo<IIC_VLD4>;
717 // ...with address register writeback:
718 class VLD4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
719 : NLdSt<0, 0b10, op11_8, op7_4,
720 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
721 (ins addrmode6:$Rn, am6offset:$Rm), IIC_VLD4u,
722 "vld4", Dt, "\\{$Vd, $dst2, $dst3, $dst4\\}, $Rn$Rm",
723 "$Rn.addr = $wb", []> {
724 let Inst{5-4} = Rn{5-4};
725 let DecoderMethod = "DecodeVLDInstruction";
728 def VLD4d8_UPD : VLD4DWB<0b0000, {0,0,?,?}, "8">;
729 def VLD4d16_UPD : VLD4DWB<0b0000, {0,1,?,?}, "16">;
730 def VLD4d32_UPD : VLD4DWB<0b0000, {1,0,?,?}, "32">;
732 def VLD4d8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
733 def VLD4d16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
734 def VLD4d32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4u>;
736 // ...with double-spaced registers:
737 def VLD4q8 : VLD4D<0b0001, {0,0,?,?}, "8">;
738 def VLD4q16 : VLD4D<0b0001, {0,1,?,?}, "16">;
739 def VLD4q32 : VLD4D<0b0001, {1,0,?,?}, "32">;
740 def VLD4q8_UPD : VLD4DWB<0b0001, {0,0,?,?}, "8">;
741 def VLD4q16_UPD : VLD4DWB<0b0001, {0,1,?,?}, "16">;
742 def VLD4q32_UPD : VLD4DWB<0b0001, {1,0,?,?}, "32">;
744 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
745 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
746 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
748 // ...alternate versions to be allocated odd register numbers:
749 def VLD4q8oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
750 def VLD4q16oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
751 def VLD4q32oddPseudo : VLDQQQQPseudo<IIC_VLD4>;
753 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
754 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
755 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo<IIC_VLD4u>;
757 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
759 // Classes for VLD*LN pseudo-instructions with multi-register operands.
760 // These are expanded to real instructions after register allocation.
761 class VLDQLNPseudo<InstrItinClass itin>
762 : PseudoNLdSt<(outs QPR:$dst),
763 (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
764 itin, "$src = $dst">;
765 class VLDQLNWBPseudo<InstrItinClass itin>
766 : PseudoNLdSt<(outs QPR:$dst, GPR:$wb),
767 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
768 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
769 class VLDQQLNPseudo<InstrItinClass itin>
770 : PseudoNLdSt<(outs QQPR:$dst),
771 (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
772 itin, "$src = $dst">;
773 class VLDQQLNWBPseudo<InstrItinClass itin>
774 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
775 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
776 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
777 class VLDQQQQLNPseudo<InstrItinClass itin>
778 : PseudoNLdSt<(outs QQQQPR:$dst),
779 (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
780 itin, "$src = $dst">;
781 class VLDQQQQLNWBPseudo<InstrItinClass itin>
782 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
783 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
784 nohash_imm:$lane), itin, "$addr.addr = $wb, $src = $dst">;
786 // VLD1LN : Vector Load (single element to one lane)
787 class VLD1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
789 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
790 (ins addrmode6:$Rn, DPR:$src, nohash_imm:$lane),
791 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
793 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
794 (i32 (LoadOp addrmode6:$Rn)),
797 let DecoderMethod = "DecodeVLD1LN";
799 class VLD1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
801 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd),
802 (ins addrmode6oneL32:$Rn, DPR:$src, nohash_imm:$lane),
803 IIC_VLD1ln, "vld1", Dt, "\\{$Vd[$lane]\\}, $Rn",
805 [(set DPR:$Vd, (vector_insert (Ty DPR:$src),
806 (i32 (LoadOp addrmode6oneL32:$Rn)),
809 let DecoderMethod = "DecodeVLD1LN";
811 class VLD1QLNPseudo<ValueType Ty, PatFrag LoadOp> : VLDQLNPseudo<IIC_VLD1ln> {
812 let Pattern = [(set QPR:$dst, (vector_insert (Ty QPR:$src),
813 (i32 (LoadOp addrmode6:$addr)),
817 def VLD1LNd8 : VLD1LN<0b0000, {?,?,?,0}, "8", v8i8, extloadi8> {
818 let Inst{7-5} = lane{2-0};
820 def VLD1LNd16 : VLD1LN<0b0100, {?,?,0,?}, "16", v4i16, extloadi16> {
821 let Inst{7-6} = lane{1-0};
822 let Inst{5-4} = Rn{5-4};
824 def VLD1LNd32 : VLD1LN32<0b1000, {?,0,?,?}, "32", v2i32, load> {
825 let Inst{7} = lane{0};
826 let Inst{5-4} = Rn{5-4};
829 def VLD1LNq8Pseudo : VLD1QLNPseudo<v16i8, extloadi8>;
830 def VLD1LNq16Pseudo : VLD1QLNPseudo<v8i16, extloadi16>;
831 def VLD1LNq32Pseudo : VLD1QLNPseudo<v4i32, load>;
833 def : Pat<(vector_insert (v2f32 DPR:$src),
834 (f32 (load addrmode6:$addr)), imm:$lane),
835 (VLD1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
836 def : Pat<(vector_insert (v4f32 QPR:$src),
837 (f32 (load addrmode6:$addr)), imm:$lane),
838 (VLD1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
840 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
842 // ...with address register writeback:
843 class VLD1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
844 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, GPR:$wb),
845 (ins addrmode6:$Rn, am6offset:$Rm,
846 DPR:$src, nohash_imm:$lane), IIC_VLD1lnu, "vld1", Dt,
847 "\\{$Vd[$lane]\\}, $Rn$Rm",
848 "$src = $Vd, $Rn.addr = $wb", []> {
849 let DecoderMethod = "DecodeVLD1LN";
852 def VLD1LNd8_UPD : VLD1LNWB<0b0000, {?,?,?,0}, "8"> {
853 let Inst{7-5} = lane{2-0};
855 def VLD1LNd16_UPD : VLD1LNWB<0b0100, {?,?,0,?}, "16"> {
856 let Inst{7-6} = lane{1-0};
859 def VLD1LNd32_UPD : VLD1LNWB<0b1000, {?,0,?,?}, "32"> {
860 let Inst{7} = lane{0};
865 def VLD1LNq8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
866 def VLD1LNq16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
867 def VLD1LNq32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD1lnu>;
869 // VLD2LN : Vector Load (single 2-element structure to one lane)
870 class VLD2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
871 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2),
872 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, nohash_imm:$lane),
873 IIC_VLD2ln, "vld2", Dt, "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn",
874 "$src1 = $Vd, $src2 = $dst2", []> {
877 let DecoderMethod = "DecodeVLD2LN";
880 def VLD2LNd8 : VLD2LN<0b0001, {?,?,?,?}, "8"> {
881 let Inst{7-5} = lane{2-0};
883 def VLD2LNd16 : VLD2LN<0b0101, {?,?,0,?}, "16"> {
884 let Inst{7-6} = lane{1-0};
886 def VLD2LNd32 : VLD2LN<0b1001, {?,0,0,?}, "32"> {
887 let Inst{7} = lane{0};
890 def VLD2LNd8Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
891 def VLD2LNd16Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
892 def VLD2LNd32Pseudo : VLDQLNPseudo<IIC_VLD2ln>;
894 // ...with double-spaced registers:
895 def VLD2LNq16 : VLD2LN<0b0101, {?,?,1,?}, "16"> {
896 let Inst{7-6} = lane{1-0};
898 def VLD2LNq32 : VLD2LN<0b1001, {?,1,0,?}, "32"> {
899 let Inst{7} = lane{0};
902 def VLD2LNq16Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
903 def VLD2LNq32Pseudo : VLDQQLNPseudo<IIC_VLD2ln>;
905 // ...with address register writeback:
906 class VLD2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
907 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
908 (ins addrmode6:$Rn, am6offset:$Rm,
909 DPR:$src1, DPR:$src2, nohash_imm:$lane), IIC_VLD2lnu, "vld2", Dt,
910 "\\{$Vd[$lane], $dst2[$lane]\\}, $Rn$Rm",
911 "$src1 = $Vd, $src2 = $dst2, $Rn.addr = $wb", []> {
913 let DecoderMethod = "DecodeVLD2LN";
916 def VLD2LNd8_UPD : VLD2LNWB<0b0001, {?,?,?,?}, "8"> {
917 let Inst{7-5} = lane{2-0};
919 def VLD2LNd16_UPD : VLD2LNWB<0b0101, {?,?,0,?}, "16"> {
920 let Inst{7-6} = lane{1-0};
922 def VLD2LNd32_UPD : VLD2LNWB<0b1001, {?,0,0,?}, "32"> {
923 let Inst{7} = lane{0};
926 def VLD2LNd8Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
927 def VLD2LNd16Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
928 def VLD2LNd32Pseudo_UPD : VLDQLNWBPseudo<IIC_VLD2lnu>;
930 def VLD2LNq16_UPD : VLD2LNWB<0b0101, {?,?,1,?}, "16"> {
931 let Inst{7-6} = lane{1-0};
933 def VLD2LNq32_UPD : VLD2LNWB<0b1001, {?,1,0,?}, "32"> {
934 let Inst{7} = lane{0};
937 def VLD2LNq16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
938 def VLD2LNq32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD2lnu>;
940 // VLD3LN : Vector Load (single 3-element structure to one lane)
941 class VLD3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
942 : NLdStLn<1, 0b10, op11_8, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
943 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3,
944 nohash_imm:$lane), IIC_VLD3ln, "vld3", Dt,
945 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn",
946 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3", []> {
948 let DecoderMethod = "DecodeVLD3LN";
951 def VLD3LNd8 : VLD3LN<0b0010, {?,?,?,0}, "8"> {
952 let Inst{7-5} = lane{2-0};
954 def VLD3LNd16 : VLD3LN<0b0110, {?,?,0,0}, "16"> {
955 let Inst{7-6} = lane{1-0};
957 def VLD3LNd32 : VLD3LN<0b1010, {?,0,0,0}, "32"> {
958 let Inst{7} = lane{0};
961 def VLD3LNd8Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
962 def VLD3LNd16Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
963 def VLD3LNd32Pseudo : VLDQQLNPseudo<IIC_VLD3ln>;
965 // ...with double-spaced registers:
966 def VLD3LNq16 : VLD3LN<0b0110, {?,?,1,0}, "16"> {
967 let Inst{7-6} = lane{1-0};
969 def VLD3LNq32 : VLD3LN<0b1010, {?,1,0,0}, "32"> {
970 let Inst{7} = lane{0};
973 def VLD3LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
974 def VLD3LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD3ln>;
976 // ...with address register writeback:
977 class VLD3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
978 : NLdStLn<1, 0b10, op11_8, op7_4,
979 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
980 (ins addrmode6:$Rn, am6offset:$Rm,
981 DPR:$src1, DPR:$src2, DPR:$src3, nohash_imm:$lane),
982 IIC_VLD3lnu, "vld3", Dt,
983 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane]\\}, $Rn$Rm",
984 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $Rn.addr = $wb",
986 let DecoderMethod = "DecodeVLD3LN";
989 def VLD3LNd8_UPD : VLD3LNWB<0b0010, {?,?,?,0}, "8"> {
990 let Inst{7-5} = lane{2-0};
992 def VLD3LNd16_UPD : VLD3LNWB<0b0110, {?,?,0,0}, "16"> {
993 let Inst{7-6} = lane{1-0};
995 def VLD3LNd32_UPD : VLD3LNWB<0b1010, {?,0,0,0}, "32"> {
996 let Inst{7} = lane{0};
999 def VLD3LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1000 def VLD3LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1001 def VLD3LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD3lnu>;
1003 def VLD3LNq16_UPD : VLD3LNWB<0b0110, {?,?,1,0}, "16"> {
1004 let Inst{7-6} = lane{1-0};
1006 def VLD3LNq32_UPD : VLD3LNWB<0b1010, {?,1,0,0}, "32"> {
1007 let Inst{7} = lane{0};
1010 def VLD3LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1011 def VLD3LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD3lnu>;
1013 // VLD4LN : Vector Load (single 4-element structure to one lane)
1014 class VLD4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1015 : NLdStLn<1, 0b10, op11_8, op7_4,
1016 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1017 (ins addrmode6:$Rn, DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4,
1018 nohash_imm:$lane), IIC_VLD4ln, "vld4", Dt,
1019 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn",
1020 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4", []> {
1022 let Inst{4} = Rn{4};
1023 let DecoderMethod = "DecodeVLD4LN";
1026 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1027 let Inst{7-5} = lane{2-0};
1029 def VLD4LNd16 : VLD4LN<0b0111, {?,?,0,?}, "16"> {
1030 let Inst{7-6} = lane{1-0};
1032 def VLD4LNd32 : VLD4LN<0b1011, {?,0,?,?}, "32"> {
1033 let Inst{7} = lane{0};
1034 let Inst{5} = Rn{5};
1037 def VLD4LNd8Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1038 def VLD4LNd16Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1039 def VLD4LNd32Pseudo : VLDQQLNPseudo<IIC_VLD4ln>;
1041 // ...with double-spaced registers:
1042 def VLD4LNq16 : VLD4LN<0b0111, {?,?,1,?}, "16"> {
1043 let Inst{7-6} = lane{1-0};
1045 def VLD4LNq32 : VLD4LN<0b1011, {?,1,?,?}, "32"> {
1046 let Inst{7} = lane{0};
1047 let Inst{5} = Rn{5};
1050 def VLD4LNq16Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1051 def VLD4LNq32Pseudo : VLDQQQQLNPseudo<IIC_VLD4ln>;
1053 // ...with address register writeback:
1054 class VLD4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1055 : NLdStLn<1, 0b10, op11_8, op7_4,
1056 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1057 (ins addrmode6:$Rn, am6offset:$Rm,
1058 DPR:$src1, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
1059 IIC_VLD4lnu, "vld4", Dt,
1060 "\\{$Vd[$lane], $dst2[$lane], $dst3[$lane], $dst4[$lane]\\}, $Rn$Rm",
1061 "$src1 = $Vd, $src2 = $dst2, $src3 = $dst3, $src4 = $dst4, $Rn.addr = $wb",
1063 let Inst{4} = Rn{4};
1064 let DecoderMethod = "DecodeVLD4LN" ;
1067 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1068 let Inst{7-5} = lane{2-0};
1070 def VLD4LNd16_UPD : VLD4LNWB<0b0111, {?,?,0,?}, "16"> {
1071 let Inst{7-6} = lane{1-0};
1073 def VLD4LNd32_UPD : VLD4LNWB<0b1011, {?,0,?,?}, "32"> {
1074 let Inst{7} = lane{0};
1075 let Inst{5} = Rn{5};
1078 def VLD4LNd8Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1079 def VLD4LNd16Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1080 def VLD4LNd32Pseudo_UPD : VLDQQLNWBPseudo<IIC_VLD4lnu>;
1082 def VLD4LNq16_UPD : VLD4LNWB<0b0111, {?,?,1,?}, "16"> {
1083 let Inst{7-6} = lane{1-0};
1085 def VLD4LNq32_UPD : VLD4LNWB<0b1011, {?,1,?,?}, "32"> {
1086 let Inst{7} = lane{0};
1087 let Inst{5} = Rn{5};
1090 def VLD4LNq16Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1091 def VLD4LNq32Pseudo_UPD : VLDQQQQLNWBPseudo<IIC_VLD4lnu>;
1093 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1095 // VLD1DUP : Vector Load (single element to all lanes)
1096 class VLD1DUP<bits<4> op7_4, string Dt, ValueType Ty, PatFrag LoadOp>
1097 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListOneDAllLanes:$Vd),
1098 (ins addrmode6dup:$Rn),
1099 IIC_VLD1dup, "vld1", Dt, "$Vd, $Rn", "",
1100 [(set VecListOneDAllLanes:$Vd,
1101 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$Rn)))))]> {
1103 let Inst{4} = Rn{4};
1104 let DecoderMethod = "DecodeVLD1DupInstruction";
1106 class VLD1QDUPPseudo<ValueType Ty, PatFrag LoadOp> : VLDQPseudo<IIC_VLD1dup> {
1107 let Pattern = [(set QPR:$dst,
1108 (Ty (NEONvdup (i32 (LoadOp addrmode6dup:$addr)))))];
1111 def VLD1DUPd8 : VLD1DUP<{0,0,0,?}, "8", v8i8, extloadi8>;
1112 def VLD1DUPd16 : VLD1DUP<{0,1,0,?}, "16", v4i16, extloadi16>;
1113 def VLD1DUPd32 : VLD1DUP<{1,0,0,?}, "32", v2i32, load>;
1115 def VLD1DUPq8Pseudo : VLD1QDUPPseudo<v16i8, extloadi8>;
1116 def VLD1DUPq16Pseudo : VLD1QDUPPseudo<v8i16, extloadi16>;
1117 def VLD1DUPq32Pseudo : VLD1QDUPPseudo<v4i32, load>;
1119 def : Pat<(v2f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1120 (VLD1DUPd32 addrmode6:$addr)>;
1121 def : Pat<(v4f32 (NEONvdup (f32 (load addrmode6dup:$addr)))),
1122 (VLD1DUPq32Pseudo addrmode6:$addr)>;
1124 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
1126 class VLD1QDUP<bits<4> op7_4, string Dt>
1127 : NLdSt<1, 0b10, 0b1100, op7_4, (outs VecListTwoDAllLanes:$Vd),
1128 (ins addrmode6dup:$Rn), IIC_VLD1dup,
1129 "vld1", Dt, "$Vd, $Rn", "", []> {
1131 let Inst{4} = Rn{4};
1132 let DecoderMethod = "DecodeVLD1DupInstruction";
1135 def VLD1DUPq8 : VLD1QDUP<{0,0,1,0}, "8">;
1136 def VLD1DUPq16 : VLD1QDUP<{0,1,1,?}, "16">;
1137 def VLD1DUPq32 : VLD1QDUP<{1,0,1,?}, "32">;
1139 // ...with address register writeback:
1140 multiclass VLD1DUPWB<bits<4> op7_4, string Dt> {
1141 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1142 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1143 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1144 "vld1", Dt, "$Vd, $Rn!",
1145 "$Rn.addr = $wb", []> {
1146 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1147 let Inst{4} = Rn{4};
1148 let DecoderMethod = "DecodeVLD1DupInstruction";
1149 let AsmMatchConverter = "cvtVLDwbFixed";
1151 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1152 (outs VecListOneDAllLanes:$Vd, GPR:$wb),
1153 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1154 "vld1", Dt, "$Vd, $Rn, $Rm",
1155 "$Rn.addr = $wb", []> {
1156 let Inst{4} = Rn{4};
1157 let DecoderMethod = "DecodeVLD1DupInstruction";
1158 let AsmMatchConverter = "cvtVLDwbRegister";
1161 multiclass VLD1QDUPWB<bits<4> op7_4, string Dt> {
1162 def _fixed : NLdSt<1, 0b10, 0b1100, op7_4,
1163 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1164 (ins addrmode6dup:$Rn), IIC_VLD1dupu,
1165 "vld1", Dt, "$Vd, $Rn!",
1166 "$Rn.addr = $wb", []> {
1167 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1168 let Inst{4} = Rn{4};
1169 let DecoderMethod = "DecodeVLD1DupInstruction";
1170 let AsmMatchConverter = "cvtVLDwbFixed";
1172 def _register : NLdSt<1, 0b10, 0b1100, op7_4,
1173 (outs VecListTwoDAllLanes:$Vd, GPR:$wb),
1174 (ins addrmode6dup:$Rn, rGPR:$Rm), IIC_VLD1dupu,
1175 "vld1", Dt, "$Vd, $Rn, $Rm",
1176 "$Rn.addr = $wb", []> {
1177 let Inst{4} = Rn{4};
1178 let DecoderMethod = "DecodeVLD1DupInstruction";
1179 let AsmMatchConverter = "cvtVLDwbRegister";
1183 defm VLD1DUPd8wb : VLD1DUPWB<{0,0,0,0}, "8">;
1184 defm VLD1DUPd16wb : VLD1DUPWB<{0,1,0,?}, "16">;
1185 defm VLD1DUPd32wb : VLD1DUPWB<{1,0,0,?}, "32">;
1187 defm VLD1DUPq8wb : VLD1QDUPWB<{0,0,1,0}, "8">;
1188 defm VLD1DUPq16wb : VLD1QDUPWB<{0,1,1,?}, "16">;
1189 defm VLD1DUPq32wb : VLD1QDUPWB<{1,0,1,?}, "32">;
1191 def VLD1DUPq8PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1192 def VLD1DUPq16PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1193 def VLD1DUPq32PseudoWB_fixed : VLDQWBfixedPseudo<IIC_VLD1dupu>;
1194 def VLD1DUPq8PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1195 def VLD1DUPq16PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1196 def VLD1DUPq32PseudoWB_register : VLDQWBregisterPseudo<IIC_VLD1dupu>;
1198 // VLD2DUP : Vector Load (single 2-element structure to all lanes)
1199 class VLD2DUP<bits<4> op7_4, string Dt>
1200 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2),
1201 (ins addrmode6dup:$Rn), IIC_VLD2dup,
1202 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn", "", []> {
1204 let Inst{4} = Rn{4};
1205 let DecoderMethod = "DecodeVLD2DupInstruction";
1208 def VLD2DUPd8 : VLD2DUP<{0,0,0,?}, "8">;
1209 def VLD2DUPd16 : VLD2DUP<{0,1,0,?}, "16">;
1210 def VLD2DUPd32 : VLD2DUP<{1,0,0,?}, "32">;
1212 def VLD2DUPd8Pseudo : VLDQPseudo<IIC_VLD2dup>;
1213 def VLD2DUPd16Pseudo : VLDQPseudo<IIC_VLD2dup>;
1214 def VLD2DUPd32Pseudo : VLDQPseudo<IIC_VLD2dup>;
1216 // ...with double-spaced registers (not used for codegen):
1217 def VLD2DUPd8x2 : VLD2DUP<{0,0,1,?}, "8">;
1218 def VLD2DUPd16x2 : VLD2DUP<{0,1,1,?}, "16">;
1219 def VLD2DUPd32x2 : VLD2DUP<{1,0,1,?}, "32">;
1221 // ...with address register writeback:
1222 class VLD2DUPWB<bits<4> op7_4, string Dt>
1223 : NLdSt<1, 0b10, 0b1101, op7_4, (outs DPR:$Vd, DPR:$dst2, GPR:$wb),
1224 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD2dupu,
1225 "vld2", Dt, "\\{$Vd[], $dst2[]\\}, $Rn$Rm", "$Rn.addr = $wb", []> {
1226 let Inst{4} = Rn{4};
1227 let DecoderMethod = "DecodeVLD2DupInstruction";
1230 def VLD2DUPd8_UPD : VLD2DUPWB<{0,0,0,0}, "8">;
1231 def VLD2DUPd16_UPD : VLD2DUPWB<{0,1,0,?}, "16">;
1232 def VLD2DUPd32_UPD : VLD2DUPWB<{1,0,0,?}, "32">;
1234 def VLD2DUPd8x2_UPD : VLD2DUPWB<{0,0,1,0}, "8">;
1235 def VLD2DUPd16x2_UPD : VLD2DUPWB<{0,1,1,?}, "16">;
1236 def VLD2DUPd32x2_UPD : VLD2DUPWB<{1,0,1,?}, "32">;
1238 def VLD2DUPd8Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1239 def VLD2DUPd16Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1240 def VLD2DUPd32Pseudo_UPD : VLDQWBPseudo<IIC_VLD2dupu>;
1242 // VLD3DUP : Vector Load (single 3-element structure to all lanes)
1243 class VLD3DUP<bits<4> op7_4, string Dt>
1244 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3),
1245 (ins addrmode6dup:$Rn), IIC_VLD3dup,
1246 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn", "", []> {
1249 let DecoderMethod = "DecodeVLD3DupInstruction";
1252 def VLD3DUPd8 : VLD3DUP<{0,0,0,?}, "8">;
1253 def VLD3DUPd16 : VLD3DUP<{0,1,0,?}, "16">;
1254 def VLD3DUPd32 : VLD3DUP<{1,0,0,?}, "32">;
1256 def VLD3DUPd8Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1257 def VLD3DUPd16Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1258 def VLD3DUPd32Pseudo : VLDQQPseudo<IIC_VLD3dup>;
1260 // ...with double-spaced registers (not used for codegen):
1261 def VLD3DUPd8x2 : VLD3DUP<{0,0,1,?}, "8">;
1262 def VLD3DUPd16x2 : VLD3DUP<{0,1,1,?}, "16">;
1263 def VLD3DUPd32x2 : VLD3DUP<{1,0,1,?}, "32">;
1265 // ...with address register writeback:
1266 class VLD3DUPWB<bits<4> op7_4, string Dt>
1267 : NLdSt<1, 0b10, 0b1110, op7_4, (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, GPR:$wb),
1268 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD3dupu,
1269 "vld3", Dt, "\\{$Vd[], $dst2[], $dst3[]\\}, $Rn$Rm",
1270 "$Rn.addr = $wb", []> {
1272 let DecoderMethod = "DecodeVLD3DupInstruction";
1275 def VLD3DUPd8_UPD : VLD3DUPWB<{0,0,0,0}, "8">;
1276 def VLD3DUPd16_UPD : VLD3DUPWB<{0,1,0,?}, "16">;
1277 def VLD3DUPd32_UPD : VLD3DUPWB<{1,0,0,?}, "32">;
1279 def VLD3DUPd8x2_UPD : VLD3DUPWB<{0,0,1,0}, "8">;
1280 def VLD3DUPd16x2_UPD : VLD3DUPWB<{0,1,1,?}, "16">;
1281 def VLD3DUPd32x2_UPD : VLD3DUPWB<{1,0,1,?}, "32">;
1283 def VLD3DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1284 def VLD3DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1285 def VLD3DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD3dupu>;
1287 // VLD4DUP : Vector Load (single 4-element structure to all lanes)
1288 class VLD4DUP<bits<4> op7_4, string Dt>
1289 : NLdSt<1, 0b10, 0b1111, op7_4,
1290 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4),
1291 (ins addrmode6dup:$Rn), IIC_VLD4dup,
1292 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn", "", []> {
1294 let Inst{4} = Rn{4};
1295 let DecoderMethod = "DecodeVLD4DupInstruction";
1298 def VLD4DUPd8 : VLD4DUP<{0,0,0,?}, "8">;
1299 def VLD4DUPd16 : VLD4DUP<{0,1,0,?}, "16">;
1300 def VLD4DUPd32 : VLD4DUP<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1302 def VLD4DUPd8Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1303 def VLD4DUPd16Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1304 def VLD4DUPd32Pseudo : VLDQQPseudo<IIC_VLD4dup>;
1306 // ...with double-spaced registers (not used for codegen):
1307 def VLD4DUPd8x2 : VLD4DUP<{0,0,1,?}, "8">;
1308 def VLD4DUPd16x2 : VLD4DUP<{0,1,1,?}, "16">;
1309 def VLD4DUPd32x2 : VLD4DUP<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1311 // ...with address register writeback:
1312 class VLD4DUPWB<bits<4> op7_4, string Dt>
1313 : NLdSt<1, 0b10, 0b1111, op7_4,
1314 (outs DPR:$Vd, DPR:$dst2, DPR:$dst3, DPR:$dst4, GPR:$wb),
1315 (ins addrmode6dup:$Rn, am6offset:$Rm), IIC_VLD4dupu,
1316 "vld4", Dt, "\\{$Vd[], $dst2[], $dst3[], $dst4[]\\}, $Rn$Rm",
1317 "$Rn.addr = $wb", []> {
1318 let Inst{4} = Rn{4};
1319 let DecoderMethod = "DecodeVLD4DupInstruction";
1322 def VLD4DUPd8_UPD : VLD4DUPWB<{0,0,0,0}, "8">;
1323 def VLD4DUPd16_UPD : VLD4DUPWB<{0,1,0,?}, "16">;
1324 def VLD4DUPd32_UPD : VLD4DUPWB<{1,?,0,?}, "32"> { let Inst{6} = Rn{5}; }
1326 def VLD4DUPd8x2_UPD : VLD4DUPWB<{0,0,1,0}, "8">;
1327 def VLD4DUPd16x2_UPD : VLD4DUPWB<{0,1,1,?}, "16">;
1328 def VLD4DUPd32x2_UPD : VLD4DUPWB<{1,?,1,?}, "32"> { let Inst{6} = Rn{5}; }
1330 def VLD4DUPd8Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1331 def VLD4DUPd16Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1332 def VLD4DUPd32Pseudo_UPD : VLDQQWBPseudo<IIC_VLD4dupu>;
1334 } // mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1
1336 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1338 // Classes for VST* pseudo-instructions with multi-register operands.
1339 // These are expanded to real instructions after register allocation.
1340 class VSTQPseudo<InstrItinClass itin>
1341 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src), itin, "">;
1342 class VSTQWBPseudo<InstrItinClass itin>
1343 : PseudoNLdSt<(outs GPR:$wb),
1344 (ins addrmode6:$addr, am6offset:$offset, QPR:$src), itin,
1345 "$addr.addr = $wb">;
1346 class VSTQWBfixedPseudo<InstrItinClass itin>
1347 : PseudoNLdSt<(outs GPR:$wb),
1348 (ins addrmode6:$addr, QPR:$src), itin,
1349 "$addr.addr = $wb">;
1350 class VSTQWBregisterPseudo<InstrItinClass itin>
1351 : PseudoNLdSt<(outs GPR:$wb),
1352 (ins addrmode6:$addr, rGPR:$offset, QPR:$src), itin,
1353 "$addr.addr = $wb">;
1354 class VSTQQPseudo<InstrItinClass itin>
1355 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src), itin, "">;
1356 class VSTQQWBPseudo<InstrItinClass itin>
1357 : PseudoNLdSt<(outs GPR:$wb),
1358 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src), itin,
1359 "$addr.addr = $wb">;
1360 class VSTQQQQPseudo<InstrItinClass itin>
1361 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src), itin, "">;
1362 class VSTQQQQWBPseudo<InstrItinClass itin>
1363 : PseudoNLdSt<(outs GPR:$wb),
1364 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), itin,
1365 "$addr.addr = $wb">;
1367 // VST1 : Vector Store (multiple single elements)
1368 class VST1D<bits<4> op7_4, string Dt>
1369 : NLdSt<0,0b00,0b0111,op7_4, (outs), (ins addrmode6:$Rn, VecListOneD:$Vd),
1370 IIC_VST1, "vst1", Dt, "$Vd, $Rn", "", []> {
1372 let Inst{4} = Rn{4};
1373 let DecoderMethod = "DecodeVSTInstruction";
1375 class VST1Q<bits<4> op7_4, string Dt>
1376 : NLdSt<0,0b00,0b1010,op7_4, (outs), (ins addrmode6:$Rn, VecListTwoD:$Vd),
1377 IIC_VST1x2, "vst1", Dt, "$Vd, $Rn", "", []> {
1379 let Inst{5-4} = Rn{5-4};
1380 let DecoderMethod = "DecodeVSTInstruction";
1383 def VST1d8 : VST1D<{0,0,0,?}, "8">;
1384 def VST1d16 : VST1D<{0,1,0,?}, "16">;
1385 def VST1d32 : VST1D<{1,0,0,?}, "32">;
1386 def VST1d64 : VST1D<{1,1,0,?}, "64">;
1388 def VST1q8 : VST1Q<{0,0,?,?}, "8">;
1389 def VST1q16 : VST1Q<{0,1,?,?}, "16">;
1390 def VST1q32 : VST1Q<{1,0,?,?}, "32">;
1391 def VST1q64 : VST1Q<{1,1,?,?}, "64">;
1393 def VST1q8Pseudo : VSTQPseudo<IIC_VST1x2>;
1394 def VST1q16Pseudo : VSTQPseudo<IIC_VST1x2>;
1395 def VST1q32Pseudo : VSTQPseudo<IIC_VST1x2>;
1396 def VST1q64Pseudo : VSTQPseudo<IIC_VST1x2>;
1398 // ...with address register writeback:
1399 multiclass VST1DWB<bits<4> op7_4, string Dt> {
1400 def _fixed : NLdSt<0,0b00, 0b0111,op7_4, (outs GPR:$wb),
1401 (ins addrmode6:$Rn, VecListOneD:$Vd), IIC_VLD1u,
1402 "vst1", Dt, "$Vd, $Rn!",
1403 "$Rn.addr = $wb", []> {
1404 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1405 let Inst{4} = Rn{4};
1406 let DecoderMethod = "DecodeVSTInstruction";
1407 let AsmMatchConverter = "cvtVSTwbFixed";
1409 def _register : NLdSt<0,0b00,0b0111,op7_4, (outs GPR:$wb),
1410 (ins addrmode6:$Rn, rGPR:$Rm, VecListOneD:$Vd),
1412 "vst1", Dt, "$Vd, $Rn, $Rm",
1413 "$Rn.addr = $wb", []> {
1414 let Inst{4} = Rn{4};
1415 let DecoderMethod = "DecodeVSTInstruction";
1416 let AsmMatchConverter = "cvtVSTwbRegister";
1419 multiclass VST1QWB<bits<4> op7_4, string Dt> {
1420 def _fixed : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1421 (ins addrmode6:$Rn, VecListTwoD:$Vd), IIC_VLD1x2u,
1422 "vst1", Dt, "$Vd, $Rn!",
1423 "$Rn.addr = $wb", []> {
1424 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1425 let Inst{5-4} = Rn{5-4};
1426 let DecoderMethod = "DecodeVSTInstruction";
1427 let AsmMatchConverter = "cvtVSTwbFixed";
1429 def _register : NLdSt<0,0b00,0b1010,op7_4, (outs GPR:$wb),
1430 (ins addrmode6:$Rn, rGPR:$Rm, VecListTwoD:$Vd),
1432 "vst1", Dt, "$Vd, $Rn, $Rm",
1433 "$Rn.addr = $wb", []> {
1434 let Inst{5-4} = Rn{5-4};
1435 let DecoderMethod = "DecodeVSTInstruction";
1436 let AsmMatchConverter = "cvtVSTwbRegister";
1440 defm VST1d8wb : VST1DWB<{0,0,0,?}, "8">;
1441 defm VST1d16wb : VST1DWB<{0,1,0,?}, "16">;
1442 defm VST1d32wb : VST1DWB<{1,0,0,?}, "32">;
1443 defm VST1d64wb : VST1DWB<{1,1,0,?}, "64">;
1445 defm VST1q8wb : VST1QWB<{0,0,?,?}, "8">;
1446 defm VST1q16wb : VST1QWB<{0,1,?,?}, "16">;
1447 defm VST1q32wb : VST1QWB<{1,0,?,?}, "32">;
1448 defm VST1q64wb : VST1QWB<{1,1,?,?}, "64">;
1450 def VST1q8PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1451 def VST1q16PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1452 def VST1q32PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1453 def VST1q64PseudoWB_fixed : VSTQWBfixedPseudo<IIC_VST1x2u>;
1454 def VST1q8PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1455 def VST1q16PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1456 def VST1q32PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1457 def VST1q64PseudoWB_register : VSTQWBregisterPseudo<IIC_VST1x2u>;
1459 // ...with 3 registers
1460 class VST1D3<bits<4> op7_4, string Dt>
1461 : NLdSt<0, 0b00, 0b0110, op7_4, (outs),
1462 (ins addrmode6:$Rn, VecListThreeD:$Vd),
1463 IIC_VST1x3, "vst1", Dt, "$Vd, $Rn", "", []> {
1465 let Inst{4} = Rn{4};
1466 let DecoderMethod = "DecodeVSTInstruction";
1468 multiclass VST1D3WB<bits<4> op7_4, string Dt> {
1469 def _fixed : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1470 (ins addrmode6:$Rn, VecListThreeD:$Vd), IIC_VLD1x3u,
1471 "vst1", Dt, "$Vd, $Rn!",
1472 "$Rn.addr = $wb", []> {
1473 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1474 let Inst{5-4} = Rn{5-4};
1475 let DecoderMethod = "DecodeVSTInstruction";
1476 let AsmMatchConverter = "cvtVSTwbFixed";
1478 def _register : NLdSt<0,0b00,0b0110,op7_4, (outs GPR:$wb),
1479 (ins addrmode6:$Rn, rGPR:$Rm, VecListThreeD:$Vd),
1481 "vst1", Dt, "$Vd, $Rn, $Rm",
1482 "$Rn.addr = $wb", []> {
1483 let Inst{5-4} = Rn{5-4};
1484 let DecoderMethod = "DecodeVSTInstruction";
1485 let AsmMatchConverter = "cvtVSTwbRegister";
1489 def VST1d8T : VST1D3<{0,0,0,?}, "8">;
1490 def VST1d16T : VST1D3<{0,1,0,?}, "16">;
1491 def VST1d32T : VST1D3<{1,0,0,?}, "32">;
1492 def VST1d64T : VST1D3<{1,1,0,?}, "64">;
1494 defm VST1d8Twb : VST1D3WB<{0,0,0,?}, "8">;
1495 defm VST1d16Twb : VST1D3WB<{0,1,0,?}, "16">;
1496 defm VST1d32Twb : VST1D3WB<{1,0,0,?}, "32">;
1497 defm VST1d64Twb : VST1D3WB<{1,1,0,?}, "64">;
1499 def VST1d64TPseudo : VSTQQPseudo<IIC_VST1x3>;
1500 def VST1d64TPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x3u>;
1501 def VST1d64TPseudoWB_register : VSTQQWBPseudo<IIC_VST1x3u>;
1503 // ...with 4 registers
1504 class VST1D4<bits<4> op7_4, string Dt>
1505 : NLdSt<0, 0b00, 0b0010, op7_4, (outs),
1506 (ins addrmode6:$Rn, VecListFourD:$Vd),
1507 IIC_VST1x4, "vst1", Dt, "$Vd, $Rn", "",
1510 let Inst{5-4} = Rn{5-4};
1511 let DecoderMethod = "DecodeVSTInstruction";
1513 multiclass VST1D4WB<bits<4> op7_4, string Dt> {
1514 def _fixed : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1515 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1x4u,
1516 "vst1", Dt, "$Vd, $Rn!",
1517 "$Rn.addr = $wb", []> {
1518 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1519 let Inst{5-4} = Rn{5-4};
1520 let DecoderMethod = "DecodeVSTInstruction";
1521 let AsmMatchConverter = "cvtVSTwbFixed";
1523 def _register : NLdSt<0,0b00,0b0010,op7_4, (outs GPR:$wb),
1524 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1526 "vst1", Dt, "$Vd, $Rn, $Rm",
1527 "$Rn.addr = $wb", []> {
1528 let Inst{5-4} = Rn{5-4};
1529 let DecoderMethod = "DecodeVSTInstruction";
1530 let AsmMatchConverter = "cvtVSTwbRegister";
1534 def VST1d8Q : VST1D4<{0,0,?,?}, "8">;
1535 def VST1d16Q : VST1D4<{0,1,?,?}, "16">;
1536 def VST1d32Q : VST1D4<{1,0,?,?}, "32">;
1537 def VST1d64Q : VST1D4<{1,1,?,?}, "64">;
1539 defm VST1d8Qwb : VST1D4WB<{0,0,?,?}, "8">;
1540 defm VST1d16Qwb : VST1D4WB<{0,1,?,?}, "16">;
1541 defm VST1d32Qwb : VST1D4WB<{1,0,?,?}, "32">;
1542 defm VST1d64Qwb : VST1D4WB<{1,1,?,?}, "64">;
1544 def VST1d64QPseudo : VSTQQPseudo<IIC_VST1x4>;
1545 def VST1d64QPseudoWB_fixed : VSTQQWBPseudo<IIC_VST1x4u>;
1546 def VST1d64QPseudoWB_register : VSTQQWBPseudo<IIC_VST1x4u>;
1548 // VST2 : Vector Store (multiple 2-element structures)
1549 class VST2<bits<4> op11_8, bits<4> op7_4, string Dt, RegisterOperand VdTy,
1550 InstrItinClass itin>
1551 : NLdSt<0, 0b00, op11_8, op7_4, (outs), (ins addrmode6:$Rn, VdTy:$Vd),
1552 itin, "vst2", Dt, "$Vd, $Rn", "", []> {
1554 let Inst{5-4} = Rn{5-4};
1555 let DecoderMethod = "DecodeVSTInstruction";
1558 def VST2d8 : VST2<0b1000, {0,0,?,?}, "8", VecListTwoD, IIC_VST2>;
1559 def VST2d16 : VST2<0b1000, {0,1,?,?}, "16", VecListTwoD, IIC_VST2>;
1560 def VST2d32 : VST2<0b1000, {1,0,?,?}, "32", VecListTwoD, IIC_VST2>;
1562 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2>;
1563 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2>;
1564 def VST2q32 : VST2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VST2x2>;
1566 def VST2d8Pseudo : VSTQPseudo<IIC_VST2>;
1567 def VST2d16Pseudo : VSTQPseudo<IIC_VST2>;
1568 def VST2d32Pseudo : VSTQPseudo<IIC_VST2>;
1570 def VST2q8Pseudo : VSTQQPseudo<IIC_VST2x2>;
1571 def VST2q16Pseudo : VSTQQPseudo<IIC_VST2x2>;
1572 def VST2q32Pseudo : VSTQQPseudo<IIC_VST2x2>;
1574 // ...with address register writeback:
1575 multiclass VST2DWB<bits<4> op11_8, bits<4> op7_4, string Dt,
1576 RegisterOperand VdTy> {
1577 def _fixed : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1578 (ins addrmode6:$Rn, VdTy:$Vd), IIC_VLD1u,
1579 "vst2", Dt, "$Vd, $Rn!",
1580 "$Rn.addr = $wb", []> {
1581 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1582 let Inst{5-4} = Rn{5-4};
1583 let DecoderMethod = "DecodeVSTInstruction";
1584 let AsmMatchConverter = "cvtVSTwbFixed";
1586 def _register : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1587 (ins addrmode6:$Rn, rGPR:$Rm, VdTy:$Vd), IIC_VLD1u,
1588 "vst2", Dt, "$Vd, $Rn, $Rm",
1589 "$Rn.addr = $wb", []> {
1590 let Inst{5-4} = Rn{5-4};
1591 let DecoderMethod = "DecodeVSTInstruction";
1592 let AsmMatchConverter = "cvtVSTwbRegister";
1595 multiclass VST2QWB<bits<4> op7_4, string Dt> {
1596 def _fixed : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1597 (ins addrmode6:$Rn, VecListFourD:$Vd), IIC_VLD1u,
1598 "vst2", Dt, "$Vd, $Rn!",
1599 "$Rn.addr = $wb", []> {
1600 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
1601 let Inst{5-4} = Rn{5-4};
1602 let DecoderMethod = "DecodeVSTInstruction";
1603 let AsmMatchConverter = "cvtVSTwbFixed";
1605 def _register : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1606 (ins addrmode6:$Rn, rGPR:$Rm, VecListFourD:$Vd),
1608 "vst2", Dt, "$Vd, $Rn, $Rm",
1609 "$Rn.addr = $wb", []> {
1610 let Inst{5-4} = Rn{5-4};
1611 let DecoderMethod = "DecodeVSTInstruction";
1612 let AsmMatchConverter = "cvtVSTwbRegister";
1616 defm VST2d8wb : VST2DWB<0b1000, {0,0,?,?}, "8", VecListTwoD>;
1617 defm VST2d16wb : VST2DWB<0b1000, {0,1,?,?}, "16", VecListTwoD>;
1618 defm VST2d32wb : VST2DWB<0b1000, {1,0,?,?}, "32", VecListTwoD>;
1620 defm VST2q8wb : VST2QWB<{0,0,?,?}, "8">;
1621 defm VST2q16wb : VST2QWB<{0,1,?,?}, "16">;
1622 defm VST2q32wb : VST2QWB<{1,0,?,?}, "32">;
1624 def VST2d8PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1625 def VST2d16PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1626 def VST2d32PseudoWB_fixed : VSTQWBPseudo<IIC_VST2u>;
1627 def VST2d8PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1628 def VST2d16PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1629 def VST2d32PseudoWB_register : VSTQWBPseudo<IIC_VST2u>;
1631 def VST2q8PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1632 def VST2q16PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1633 def VST2q32PseudoWB_fixed : VSTQQWBPseudo<IIC_VST2x2u>;
1634 def VST2q8PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1635 def VST2q16PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1636 def VST2q32PseudoWB_register : VSTQQWBPseudo<IIC_VST2x2u>;
1638 // ...with double-spaced registers
1639 def VST2b8 : VST2<0b1001, {0,0,?,?}, "8", VecListTwoQ, IIC_VST2>;
1640 def VST2b16 : VST2<0b1001, {0,1,?,?}, "16", VecListTwoQ, IIC_VST2>;
1641 def VST2b32 : VST2<0b1001, {1,0,?,?}, "32", VecListTwoQ, IIC_VST2>;
1642 defm VST2b8wb : VST2DWB<0b1001, {0,0,?,?}, "8", VecListTwoQ>;
1643 defm VST2b16wb : VST2DWB<0b1001, {0,1,?,?}, "16", VecListTwoQ>;
1644 defm VST2b32wb : VST2DWB<0b1001, {1,0,?,?}, "32", VecListTwoQ>;
1646 // VST3 : Vector Store (multiple 3-element structures)
1647 class VST3D<bits<4> op11_8, bits<4> op7_4, string Dt>
1648 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1649 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3,
1650 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn", "", []> {
1652 let Inst{4} = Rn{4};
1653 let DecoderMethod = "DecodeVSTInstruction";
1656 def VST3d8 : VST3D<0b0100, {0,0,0,?}, "8">;
1657 def VST3d16 : VST3D<0b0100, {0,1,0,?}, "16">;
1658 def VST3d32 : VST3D<0b0100, {1,0,0,?}, "32">;
1660 def VST3d8Pseudo : VSTQQPseudo<IIC_VST3>;
1661 def VST3d16Pseudo : VSTQQPseudo<IIC_VST3>;
1662 def VST3d32Pseudo : VSTQQPseudo<IIC_VST3>;
1664 // ...with address register writeback:
1665 class VST3DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1666 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1667 (ins addrmode6:$Rn, am6offset:$Rm,
1668 DPR:$Vd, DPR:$src2, DPR:$src3), IIC_VST3u,
1669 "vst3", Dt, "\\{$Vd, $src2, $src3\\}, $Rn$Rm",
1670 "$Rn.addr = $wb", []> {
1671 let Inst{4} = Rn{4};
1672 let DecoderMethod = "DecodeVSTInstruction";
1675 def VST3d8_UPD : VST3DWB<0b0100, {0,0,0,?}, "8">;
1676 def VST3d16_UPD : VST3DWB<0b0100, {0,1,0,?}, "16">;
1677 def VST3d32_UPD : VST3DWB<0b0100, {1,0,0,?}, "32">;
1679 def VST3d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1680 def VST3d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1681 def VST3d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST3u>;
1683 // ...with double-spaced registers:
1684 def VST3q8 : VST3D<0b0101, {0,0,0,?}, "8">;
1685 def VST3q16 : VST3D<0b0101, {0,1,0,?}, "16">;
1686 def VST3q32 : VST3D<0b0101, {1,0,0,?}, "32">;
1687 def VST3q8_UPD : VST3DWB<0b0101, {0,0,0,?}, "8">;
1688 def VST3q16_UPD : VST3DWB<0b0101, {0,1,0,?}, "16">;
1689 def VST3q32_UPD : VST3DWB<0b0101, {1,0,0,?}, "32">;
1691 def VST3q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1692 def VST3q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1693 def VST3q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1695 // ...alternate versions to be allocated odd register numbers:
1696 def VST3q8oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1697 def VST3q16oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1698 def VST3q32oddPseudo : VSTQQQQPseudo<IIC_VST3>;
1700 def VST3q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1701 def VST3q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1702 def VST3q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST3u>;
1704 // VST4 : Vector Store (multiple 4-element structures)
1705 class VST4D<bits<4> op11_8, bits<4> op7_4, string Dt>
1706 : NLdSt<0, 0b00, op11_8, op7_4, (outs),
1707 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4),
1708 IIC_VST4, "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn",
1711 let Inst{5-4} = Rn{5-4};
1712 let DecoderMethod = "DecodeVSTInstruction";
1715 def VST4d8 : VST4D<0b0000, {0,0,?,?}, "8">;
1716 def VST4d16 : VST4D<0b0000, {0,1,?,?}, "16">;
1717 def VST4d32 : VST4D<0b0000, {1,0,?,?}, "32">;
1719 def VST4d8Pseudo : VSTQQPseudo<IIC_VST4>;
1720 def VST4d16Pseudo : VSTQQPseudo<IIC_VST4>;
1721 def VST4d32Pseudo : VSTQQPseudo<IIC_VST4>;
1723 // ...with address register writeback:
1724 class VST4DWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1725 : NLdSt<0, 0b00, op11_8, op7_4, (outs GPR:$wb),
1726 (ins addrmode6:$Rn, am6offset:$Rm,
1727 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4), IIC_VST4u,
1728 "vst4", Dt, "\\{$Vd, $src2, $src3, $src4\\}, $Rn$Rm",
1729 "$Rn.addr = $wb", []> {
1730 let Inst{5-4} = Rn{5-4};
1731 let DecoderMethod = "DecodeVSTInstruction";
1734 def VST4d8_UPD : VST4DWB<0b0000, {0,0,?,?}, "8">;
1735 def VST4d16_UPD : VST4DWB<0b0000, {0,1,?,?}, "16">;
1736 def VST4d32_UPD : VST4DWB<0b0000, {1,0,?,?}, "32">;
1738 def VST4d8Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1739 def VST4d16Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1740 def VST4d32Pseudo_UPD : VSTQQWBPseudo<IIC_VST4u>;
1742 // ...with double-spaced registers:
1743 def VST4q8 : VST4D<0b0001, {0,0,?,?}, "8">;
1744 def VST4q16 : VST4D<0b0001, {0,1,?,?}, "16">;
1745 def VST4q32 : VST4D<0b0001, {1,0,?,?}, "32">;
1746 def VST4q8_UPD : VST4DWB<0b0001, {0,0,?,?}, "8">;
1747 def VST4q16_UPD : VST4DWB<0b0001, {0,1,?,?}, "16">;
1748 def VST4q32_UPD : VST4DWB<0b0001, {1,0,?,?}, "32">;
1750 def VST4q8Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1751 def VST4q16Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1752 def VST4q32Pseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1754 // ...alternate versions to be allocated odd register numbers:
1755 def VST4q8oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1756 def VST4q16oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1757 def VST4q32oddPseudo : VSTQQQQPseudo<IIC_VST4>;
1759 def VST4q8oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1760 def VST4q16oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1761 def VST4q32oddPseudo_UPD : VSTQQQQWBPseudo<IIC_VST4u>;
1763 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
1765 // Classes for VST*LN pseudo-instructions with multi-register operands.
1766 // These are expanded to real instructions after register allocation.
1767 class VSTQLNPseudo<InstrItinClass itin>
1768 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QPR:$src, nohash_imm:$lane),
1770 class VSTQLNWBPseudo<InstrItinClass itin>
1771 : PseudoNLdSt<(outs GPR:$wb),
1772 (ins addrmode6:$addr, am6offset:$offset, QPR:$src,
1773 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1774 class VSTQQLNPseudo<InstrItinClass itin>
1775 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQPR:$src, nohash_imm:$lane),
1777 class VSTQQLNWBPseudo<InstrItinClass itin>
1778 : PseudoNLdSt<(outs GPR:$wb),
1779 (ins addrmode6:$addr, am6offset:$offset, QQPR:$src,
1780 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1781 class VSTQQQQLNPseudo<InstrItinClass itin>
1782 : PseudoNLdSt<(outs), (ins addrmode6:$addr, QQQQPR:$src, nohash_imm:$lane),
1784 class VSTQQQQLNWBPseudo<InstrItinClass itin>
1785 : PseudoNLdSt<(outs GPR:$wb),
1786 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src,
1787 nohash_imm:$lane), itin, "$addr.addr = $wb">;
1789 // VST1LN : Vector Store (single element from one lane)
1790 class VST1LN<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1791 PatFrag StoreOp, SDNode ExtractOp>
1792 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1793 (ins addrmode6:$Rn, DPR:$Vd, nohash_imm:$lane),
1794 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1795 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6:$Rn)]> {
1797 let DecoderMethod = "DecodeVST1LN";
1799 class VST1LN32<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1800 PatFrag StoreOp, SDNode ExtractOp>
1801 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1802 (ins addrmode6oneL32:$Rn, DPR:$Vd, nohash_imm:$lane),
1803 IIC_VST1ln, "vst1", Dt, "\\{$Vd[$lane]\\}, $Rn", "",
1804 [(StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane), addrmode6oneL32:$Rn)]>{
1806 let DecoderMethod = "DecodeVST1LN";
1808 class VST1QLNPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1809 : VSTQLNPseudo<IIC_VST1ln> {
1810 let Pattern = [(StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1814 def VST1LNd8 : VST1LN<0b0000, {?,?,?,0}, "8", v8i8, truncstorei8,
1816 let Inst{7-5} = lane{2-0};
1818 def VST1LNd16 : VST1LN<0b0100, {?,?,0,?}, "16", v4i16, truncstorei16,
1820 let Inst{7-6} = lane{1-0};
1821 let Inst{4} = Rn{5};
1824 def VST1LNd32 : VST1LN32<0b1000, {?,0,?,?}, "32", v2i32, store, extractelt> {
1825 let Inst{7} = lane{0};
1826 let Inst{5-4} = Rn{5-4};
1829 def VST1LNq8Pseudo : VST1QLNPseudo<v16i8, truncstorei8, NEONvgetlaneu>;
1830 def VST1LNq16Pseudo : VST1QLNPseudo<v8i16, truncstorei16, NEONvgetlaneu>;
1831 def VST1LNq32Pseudo : VST1QLNPseudo<v4i32, store, extractelt>;
1833 def : Pat<(store (extractelt (v2f32 DPR:$src), imm:$lane), addrmode6:$addr),
1834 (VST1LNd32 addrmode6:$addr, DPR:$src, imm:$lane)>;
1835 def : Pat<(store (extractelt (v4f32 QPR:$src), imm:$lane), addrmode6:$addr),
1836 (VST1LNq32Pseudo addrmode6:$addr, QPR:$src, imm:$lane)>;
1838 // ...with address register writeback:
1839 class VST1LNWB<bits<4> op11_8, bits<4> op7_4, string Dt, ValueType Ty,
1840 PatFrag StoreOp, SDNode ExtractOp>
1841 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1842 (ins addrmode6:$Rn, am6offset:$Rm,
1843 DPR:$Vd, nohash_imm:$lane), IIC_VST1lnu, "vst1", Dt,
1844 "\\{$Vd[$lane]\\}, $Rn$Rm",
1846 [(set GPR:$wb, (StoreOp (ExtractOp (Ty DPR:$Vd), imm:$lane),
1847 addrmode6:$Rn, am6offset:$Rm))]> {
1848 let DecoderMethod = "DecodeVST1LN";
1850 class VST1QLNWBPseudo<ValueType Ty, PatFrag StoreOp, SDNode ExtractOp>
1851 : VSTQLNWBPseudo<IIC_VST1lnu> {
1852 let Pattern = [(set GPR:$wb, (StoreOp (ExtractOp (Ty QPR:$src), imm:$lane),
1853 addrmode6:$addr, am6offset:$offset))];
1856 def VST1LNd8_UPD : VST1LNWB<0b0000, {?,?,?,0}, "8", v8i8, post_truncsti8,
1858 let Inst{7-5} = lane{2-0};
1860 def VST1LNd16_UPD : VST1LNWB<0b0100, {?,?,0,?}, "16", v4i16, post_truncsti16,
1862 let Inst{7-6} = lane{1-0};
1863 let Inst{4} = Rn{5};
1865 def VST1LNd32_UPD : VST1LNWB<0b1000, {?,0,?,?}, "32", v2i32, post_store,
1867 let Inst{7} = lane{0};
1868 let Inst{5-4} = Rn{5-4};
1871 def VST1LNq8Pseudo_UPD : VST1QLNWBPseudo<v16i8, post_truncsti8, NEONvgetlaneu>;
1872 def VST1LNq16Pseudo_UPD : VST1QLNWBPseudo<v8i16, post_truncsti16,NEONvgetlaneu>;
1873 def VST1LNq32Pseudo_UPD : VST1QLNWBPseudo<v4i32, post_store, extractelt>;
1875 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in {
1877 // VST2LN : Vector Store (single 2-element structure from one lane)
1878 class VST2LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1879 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1880 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, nohash_imm:$lane),
1881 IIC_VST2ln, "vst2", Dt, "\\{$Vd[$lane], $src2[$lane]\\}, $Rn",
1884 let Inst{4} = Rn{4};
1885 let DecoderMethod = "DecodeVST2LN";
1888 def VST2LNd8 : VST2LN<0b0001, {?,?,?,?}, "8"> {
1889 let Inst{7-5} = lane{2-0};
1891 def VST2LNd16 : VST2LN<0b0101, {?,?,0,?}, "16"> {
1892 let Inst{7-6} = lane{1-0};
1894 def VST2LNd32 : VST2LN<0b1001, {?,0,0,?}, "32"> {
1895 let Inst{7} = lane{0};
1898 def VST2LNd8Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1899 def VST2LNd16Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1900 def VST2LNd32Pseudo : VSTQLNPseudo<IIC_VST2ln>;
1902 // ...with double-spaced registers:
1903 def VST2LNq16 : VST2LN<0b0101, {?,?,1,?}, "16"> {
1904 let Inst{7-6} = lane{1-0};
1905 let Inst{4} = Rn{4};
1907 def VST2LNq32 : VST2LN<0b1001, {?,1,0,?}, "32"> {
1908 let Inst{7} = lane{0};
1909 let Inst{4} = Rn{4};
1912 def VST2LNq16Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1913 def VST2LNq32Pseudo : VSTQQLNPseudo<IIC_VST2ln>;
1915 // ...with address register writeback:
1916 class VST2LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1917 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1918 (ins addrmode6:$Rn, am6offset:$Rm,
1919 DPR:$Vd, DPR:$src2, nohash_imm:$lane), IIC_VST2lnu, "vst2", Dt,
1920 "\\{$Vd[$lane], $src2[$lane]\\}, $Rn$Rm",
1921 "$Rn.addr = $wb", []> {
1922 let Inst{4} = Rn{4};
1923 let DecoderMethod = "DecodeVST2LN";
1926 def VST2LNd8_UPD : VST2LNWB<0b0001, {?,?,?,?}, "8"> {
1927 let Inst{7-5} = lane{2-0};
1929 def VST2LNd16_UPD : VST2LNWB<0b0101, {?,?,0,?}, "16"> {
1930 let Inst{7-6} = lane{1-0};
1932 def VST2LNd32_UPD : VST2LNWB<0b1001, {?,0,0,?}, "32"> {
1933 let Inst{7} = lane{0};
1936 def VST2LNd8Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1937 def VST2LNd16Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1938 def VST2LNd32Pseudo_UPD : VSTQLNWBPseudo<IIC_VST2lnu>;
1940 def VST2LNq16_UPD : VST2LNWB<0b0101, {?,?,1,?}, "16"> {
1941 let Inst{7-6} = lane{1-0};
1943 def VST2LNq32_UPD : VST2LNWB<0b1001, {?,1,0,?}, "32"> {
1944 let Inst{7} = lane{0};
1947 def VST2LNq16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1948 def VST2LNq32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST2lnu>;
1950 // VST3LN : Vector Store (single 3-element structure from one lane)
1951 class VST3LN<bits<4> op11_8, bits<4> op7_4, string Dt>
1952 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
1953 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3,
1954 nohash_imm:$lane), IIC_VST3ln, "vst3", Dt,
1955 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn", "", []> {
1957 let DecoderMethod = "DecodeVST3LN";
1960 def VST3LNd8 : VST3LN<0b0010, {?,?,?,0}, "8"> {
1961 let Inst{7-5} = lane{2-0};
1963 def VST3LNd16 : VST3LN<0b0110, {?,?,0,0}, "16"> {
1964 let Inst{7-6} = lane{1-0};
1966 def VST3LNd32 : VST3LN<0b1010, {?,0,0,0}, "32"> {
1967 let Inst{7} = lane{0};
1970 def VST3LNd8Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1971 def VST3LNd16Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1972 def VST3LNd32Pseudo : VSTQQLNPseudo<IIC_VST3ln>;
1974 // ...with double-spaced registers:
1975 def VST3LNq16 : VST3LN<0b0110, {?,?,1,0}, "16"> {
1976 let Inst{7-6} = lane{1-0};
1978 def VST3LNq32 : VST3LN<0b1010, {?,1,0,0}, "32"> {
1979 let Inst{7} = lane{0};
1982 def VST3LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1983 def VST3LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST3ln>;
1985 // ...with address register writeback:
1986 class VST3LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
1987 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
1988 (ins addrmode6:$Rn, am6offset:$Rm,
1989 DPR:$Vd, DPR:$src2, DPR:$src3, nohash_imm:$lane),
1990 IIC_VST3lnu, "vst3", Dt,
1991 "\\{$Vd[$lane], $src2[$lane], $src3[$lane]\\}, $Rn$Rm",
1992 "$Rn.addr = $wb", []> {
1993 let DecoderMethod = "DecodeVST3LN";
1996 def VST3LNd8_UPD : VST3LNWB<0b0010, {?,?,?,0}, "8"> {
1997 let Inst{7-5} = lane{2-0};
1999 def VST3LNd16_UPD : VST3LNWB<0b0110, {?,?,0,0}, "16"> {
2000 let Inst{7-6} = lane{1-0};
2002 def VST3LNd32_UPD : VST3LNWB<0b1010, {?,0,0,0}, "32"> {
2003 let Inst{7} = lane{0};
2006 def VST3LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2007 def VST3LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2008 def VST3LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST3lnu>;
2010 def VST3LNq16_UPD : VST3LNWB<0b0110, {?,?,1,0}, "16"> {
2011 let Inst{7-6} = lane{1-0};
2013 def VST3LNq32_UPD : VST3LNWB<0b1010, {?,1,0,0}, "32"> {
2014 let Inst{7} = lane{0};
2017 def VST3LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2018 def VST3LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST3lnu>;
2020 // VST4LN : Vector Store (single 4-element structure from one lane)
2021 class VST4LN<bits<4> op11_8, bits<4> op7_4, string Dt>
2022 : NLdStLn<1, 0b00, op11_8, op7_4, (outs),
2023 (ins addrmode6:$Rn, DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4,
2024 nohash_imm:$lane), IIC_VST4ln, "vst4", Dt,
2025 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn",
2028 let Inst{4} = Rn{4};
2029 let DecoderMethod = "DecodeVST4LN";
2032 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
2033 let Inst{7-5} = lane{2-0};
2035 def VST4LNd16 : VST4LN<0b0111, {?,?,0,?}, "16"> {
2036 let Inst{7-6} = lane{1-0};
2038 def VST4LNd32 : VST4LN<0b1011, {?,0,?,?}, "32"> {
2039 let Inst{7} = lane{0};
2040 let Inst{5} = Rn{5};
2043 def VST4LNd8Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2044 def VST4LNd16Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2045 def VST4LNd32Pseudo : VSTQQLNPseudo<IIC_VST4ln>;
2047 // ...with double-spaced registers:
2048 def VST4LNq16 : VST4LN<0b0111, {?,?,1,?}, "16"> {
2049 let Inst{7-6} = lane{1-0};
2051 def VST4LNq32 : VST4LN<0b1011, {?,1,?,?}, "32"> {
2052 let Inst{7} = lane{0};
2053 let Inst{5} = Rn{5};
2056 def VST4LNq16Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2057 def VST4LNq32Pseudo : VSTQQQQLNPseudo<IIC_VST4ln>;
2059 // ...with address register writeback:
2060 class VST4LNWB<bits<4> op11_8, bits<4> op7_4, string Dt>
2061 : NLdStLn<1, 0b00, op11_8, op7_4, (outs GPR:$wb),
2062 (ins addrmode6:$Rn, am6offset:$Rm,
2063 DPR:$Vd, DPR:$src2, DPR:$src3, DPR:$src4, nohash_imm:$lane),
2064 IIC_VST4lnu, "vst4", Dt,
2065 "\\{$Vd[$lane], $src2[$lane], $src3[$lane], $src4[$lane]\\}, $Rn$Rm",
2066 "$Rn.addr = $wb", []> {
2067 let Inst{4} = Rn{4};
2068 let DecoderMethod = "DecodeVST4LN";
2071 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
2072 let Inst{7-5} = lane{2-0};
2074 def VST4LNd16_UPD : VST4LNWB<0b0111, {?,?,0,?}, "16"> {
2075 let Inst{7-6} = lane{1-0};
2077 def VST4LNd32_UPD : VST4LNWB<0b1011, {?,0,?,?}, "32"> {
2078 let Inst{7} = lane{0};
2079 let Inst{5} = Rn{5};
2082 def VST4LNd8Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2083 def VST4LNd16Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2084 def VST4LNd32Pseudo_UPD : VSTQQLNWBPseudo<IIC_VST4lnu>;
2086 def VST4LNq16_UPD : VST4LNWB<0b0111, {?,?,1,?}, "16"> {
2087 let Inst{7-6} = lane{1-0};
2089 def VST4LNq32_UPD : VST4LNWB<0b1011, {?,1,?,?}, "32"> {
2090 let Inst{7} = lane{0};
2091 let Inst{5} = Rn{5};
2094 def VST4LNq16Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2095 def VST4LNq32Pseudo_UPD : VSTQQQQLNWBPseudo<IIC_VST4lnu>;
2097 } // mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1
2100 //===----------------------------------------------------------------------===//
2101 // NEON pattern fragments
2102 //===----------------------------------------------------------------------===//
2104 // Extract D sub-registers of Q registers.
2105 def DSubReg_i8_reg : SDNodeXForm<imm, [{
2106 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2107 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/8, MVT::i32);
2109 def DSubReg_i16_reg : SDNodeXForm<imm, [{
2110 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2111 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/4, MVT::i32);
2113 def DSubReg_i32_reg : SDNodeXForm<imm, [{
2114 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2115 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue()/2, MVT::i32);
2117 def DSubReg_f64_reg : SDNodeXForm<imm, [{
2118 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
2119 return CurDAG->getTargetConstant(ARM::dsub_0 + N->getZExtValue(), MVT::i32);
2122 // Extract S sub-registers of Q/D registers.
2123 def SSubReg_f32_reg : SDNodeXForm<imm, [{
2124 assert(ARM::ssub_3 == ARM::ssub_0+3 && "Unexpected subreg numbering");
2125 return CurDAG->getTargetConstant(ARM::ssub_0 + N->getZExtValue(), MVT::i32);
2128 // Translate lane numbers from Q registers to D subregs.
2129 def SubReg_i8_lane : SDNodeXForm<imm, [{
2130 return CurDAG->getTargetConstant(N->getZExtValue() & 7, MVT::i32);
2132 def SubReg_i16_lane : SDNodeXForm<imm, [{
2133 return CurDAG->getTargetConstant(N->getZExtValue() & 3, MVT::i32);
2135 def SubReg_i32_lane : SDNodeXForm<imm, [{
2136 return CurDAG->getTargetConstant(N->getZExtValue() & 1, MVT::i32);
2139 //===----------------------------------------------------------------------===//
2140 // Instruction Classes
2141 //===----------------------------------------------------------------------===//
2143 // Basic 2-register operations: double- and quad-register.
2144 class N2VD<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2145 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2146 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2147 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2148 (ins DPR:$Vm), IIC_VUNAD, OpcodeStr, Dt,"$Vd, $Vm", "",
2149 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm))))]>;
2150 class N2VQ<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2151 bits<2> op17_16, bits<5> op11_7, bit op4, string OpcodeStr,
2152 string Dt, ValueType ResTy, ValueType OpTy, SDNode OpNode>
2153 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2154 (ins QPR:$Vm), IIC_VUNAQ, OpcodeStr, Dt,"$Vd, $Vm", "",
2155 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm))))]>;
2157 // Basic 2-register intrinsics, both double- and quad-register.
2158 class N2VDInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2159 bits<2> op17_16, bits<5> op11_7, bit op4,
2160 InstrItinClass itin, string OpcodeStr, string Dt,
2161 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2162 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2163 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2164 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2165 class N2VQInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2166 bits<2> op17_16, bits<5> op11_7, bit op4,
2167 InstrItinClass itin, string OpcodeStr, string Dt,
2168 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2169 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2170 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2171 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2173 // Narrow 2-register operations.
2174 class N2VN<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2175 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2176 InstrItinClass itin, string OpcodeStr, string Dt,
2177 ValueType TyD, ValueType TyQ, SDNode OpNode>
2178 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2179 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2180 [(set DPR:$Vd, (TyD (OpNode (TyQ QPR:$Vm))))]>;
2182 // Narrow 2-register intrinsics.
2183 class N2VNInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2184 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2185 InstrItinClass itin, string OpcodeStr, string Dt,
2186 ValueType TyD, ValueType TyQ, Intrinsic IntOp>
2187 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs DPR:$Vd),
2188 (ins QPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2189 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vm))))]>;
2191 // Long 2-register operations (currently only used for VMOVL).
2192 class N2VL<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2193 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2194 InstrItinClass itin, string OpcodeStr, string Dt,
2195 ValueType TyQ, ValueType TyD, SDNode OpNode>
2196 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2197 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2198 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vm))))]>;
2200 // Long 2-register intrinsics.
2201 class N2VLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2202 bits<2> op17_16, bits<5> op11_7, bit op6, bit op4,
2203 InstrItinClass itin, string OpcodeStr, string Dt,
2204 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2205 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, op6, op4, (outs QPR:$Vd),
2206 (ins DPR:$Vm), itin, OpcodeStr, Dt, "$Vd, $Vm", "",
2207 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vm))))]>;
2209 // 2-register shuffles (VTRN/VZIP/VUZP), both double- and quad-register.
2210 class N2VDShuffle<bits<2> op19_18, bits<5> op11_7, string OpcodeStr, string Dt>
2211 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 0, 0, (outs DPR:$Vd, DPR:$Vm),
2212 (ins DPR:$src1, DPR:$src2), IIC_VPERMD,
2213 OpcodeStr, Dt, "$Vd, $Vm",
2214 "$src1 = $Vd, $src2 = $Vm", []>;
2215 class N2VQShuffle<bits<2> op19_18, bits<5> op11_7,
2216 InstrItinClass itin, string OpcodeStr, string Dt>
2217 : N2V<0b11, 0b11, op19_18, 0b10, op11_7, 1, 0, (outs QPR:$Vd, QPR:$Vm),
2218 (ins QPR:$src1, QPR:$src2), itin, OpcodeStr, Dt, "$Vd, $Vm",
2219 "$src1 = $Vd, $src2 = $Vm", []>;
2221 // Basic 3-register operations: double- and quad-register.
2222 class N3VD<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2223 InstrItinClass itin, string OpcodeStr, string Dt,
2224 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2225 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2226 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2227 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2228 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2229 let isCommutable = Commutable;
2231 // Same as N3VD but no data type.
2232 class N3VDX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2233 InstrItinClass itin, string OpcodeStr,
2234 ValueType ResTy, ValueType OpTy,
2235 SDNode OpNode, bit Commutable>
2236 : N3VX<op24, op23, op21_20, op11_8, 0, op4,
2237 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2238 OpcodeStr, "$Vd, $Vn, $Vm", "",
2239 [(set DPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>{
2240 let isCommutable = Commutable;
2243 class N3VDSL<bits<2> op21_20, bits<4> op11_8,
2244 InstrItinClass itin, string OpcodeStr, string Dt,
2245 ValueType Ty, SDNode ShOp>
2246 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2247 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2248 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2250 (Ty (ShOp (Ty DPR:$Vn),
2251 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),imm:$lane)))))]> {
2252 let isCommutable = 0;
2254 class N3VDSL16<bits<2> op21_20, bits<4> op11_8,
2255 string OpcodeStr, string Dt, ValueType Ty, SDNode ShOp>
2256 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2257 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2258 NVMulSLFrm, IIC_VMULi16D, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane","",
2260 (Ty (ShOp (Ty DPR:$Vn),
2261 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2262 let isCommutable = 0;
2265 class N3VQ<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2266 InstrItinClass itin, string OpcodeStr, string Dt,
2267 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2268 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2269 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2270 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2271 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2272 let isCommutable = Commutable;
2274 class N3VQX<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2275 InstrItinClass itin, string OpcodeStr,
2276 ValueType ResTy, ValueType OpTy, SDNode OpNode, bit Commutable>
2277 : N3VX<op24, op23, op21_20, op11_8, 1, op4,
2278 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2279 OpcodeStr, "$Vd, $Vn, $Vm", "",
2280 [(set QPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>{
2281 let isCommutable = Commutable;
2283 class N3VQSL<bits<2> op21_20, bits<4> op11_8,
2284 InstrItinClass itin, string OpcodeStr, string Dt,
2285 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2286 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2287 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2288 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2289 [(set (ResTy QPR:$Vd),
2290 (ResTy (ShOp (ResTy QPR:$Vn),
2291 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2293 let isCommutable = 0;
2295 class N3VQSL16<bits<2> op21_20, bits<4> op11_8, string OpcodeStr, string Dt,
2296 ValueType ResTy, ValueType OpTy, SDNode ShOp>
2297 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2298 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2299 NVMulSLFrm, IIC_VMULi16Q, OpcodeStr, Dt,"$Vd, $Vn, $Vm$lane", "",
2300 [(set (ResTy QPR:$Vd),
2301 (ResTy (ShOp (ResTy QPR:$Vn),
2302 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2304 let isCommutable = 0;
2307 // Basic 3-register intrinsics, both double- and quad-register.
2308 class N3VDInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2309 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2310 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2311 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2312 (outs DPR:$Vd), (ins DPR:$Vn, DPR:$Vm), f, itin,
2313 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2314 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]> {
2315 let isCommutable = Commutable;
2317 class N3VDIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2318 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2319 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2320 (outs DPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2321 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2323 (Ty (IntOp (Ty DPR:$Vn),
2324 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2326 let isCommutable = 0;
2328 class N3VDIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2329 string OpcodeStr, string Dt, ValueType Ty, Intrinsic IntOp>
2330 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2331 (outs DPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2332 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2334 (Ty (IntOp (Ty DPR:$Vn),
2335 (Ty (NEONvduplane (Ty DPR_8:$Vm), imm:$lane)))))]> {
2336 let isCommutable = 0;
2338 class N3VDIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2339 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2340 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2341 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2342 (outs DPR:$Vd), (ins DPR:$Vm, DPR:$Vn), f, itin,
2343 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2344 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (OpTy DPR:$Vn))))]> {
2345 let isCommutable = 0;
2348 class N3VQInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2349 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2350 ValueType ResTy, ValueType OpTy, Intrinsic IntOp, bit Commutable>
2351 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2352 (outs QPR:$Vd), (ins QPR:$Vn, QPR:$Vm), f, itin,
2353 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2354 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]> {
2355 let isCommutable = Commutable;
2357 class N3VQIntSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2358 string OpcodeStr, string Dt,
2359 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2360 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2361 (outs QPR:$Vd), (ins QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2362 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2363 [(set (ResTy QPR:$Vd),
2364 (ResTy (IntOp (ResTy QPR:$Vn),
2365 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2367 let isCommutable = 0;
2369 class N3VQIntSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2370 string OpcodeStr, string Dt,
2371 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2372 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2373 (outs QPR:$Vd), (ins QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2374 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2375 [(set (ResTy QPR:$Vd),
2376 (ResTy (IntOp (ResTy QPR:$Vn),
2377 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2379 let isCommutable = 0;
2381 class N3VQIntSh<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2382 Format f, InstrItinClass itin, string OpcodeStr, string Dt,
2383 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2384 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2385 (outs QPR:$Vd), (ins QPR:$Vm, QPR:$Vn), f, itin,
2386 OpcodeStr, Dt, "$Vd, $Vm, $Vn", "",
2387 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (OpTy QPR:$Vn))))]> {
2388 let isCommutable = 0;
2391 // Multiply-Add/Sub operations: double- and quad-register.
2392 class N3VDMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2393 InstrItinClass itin, string OpcodeStr, string Dt,
2394 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator OpNode>
2395 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2396 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2397 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2398 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2399 (Ty (MulOp DPR:$Vn, DPR:$Vm)))))]>;
2401 class N3VDMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2402 string OpcodeStr, string Dt,
2403 ValueType Ty, SDPatternOperator MulOp, SDPatternOperator ShOp>
2404 : N3VLane32<0, 1, op21_20, op11_8, 1, 0,
2406 (ins DPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2408 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2410 (Ty (ShOp (Ty DPR:$src1),
2412 (Ty (NEONvduplane (Ty DPR_VFP2:$Vm),
2414 class N3VDMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2415 string OpcodeStr, string Dt,
2416 ValueType Ty, SDNode MulOp, SDNode ShOp>
2417 : N3VLane16<0, 1, op21_20, op11_8, 1, 0,
2419 (ins DPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2421 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2423 (Ty (ShOp (Ty DPR:$src1),
2425 (Ty (NEONvduplane (Ty DPR_8:$Vm),
2428 class N3VQMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2429 InstrItinClass itin, string OpcodeStr, string Dt, ValueType Ty,
2430 SDPatternOperator MulOp, SDPatternOperator OpNode>
2431 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2432 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2433 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2434 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2435 (Ty (MulOp QPR:$Vn, QPR:$Vm)))))]>;
2436 class N3VQMulOpSL<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2437 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2438 SDPatternOperator MulOp, SDPatternOperator ShOp>
2439 : N3VLane32<1, 1, op21_20, op11_8, 1, 0,
2441 (ins QPR:$src1, QPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2443 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2444 [(set (ResTy QPR:$Vd),
2445 (ResTy (ShOp (ResTy QPR:$src1),
2446 (ResTy (MulOp QPR:$Vn,
2447 (ResTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2449 class N3VQMulOpSL16<bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2450 string OpcodeStr, string Dt,
2451 ValueType ResTy, ValueType OpTy,
2452 SDNode MulOp, SDNode ShOp>
2453 : N3VLane16<1, 1, op21_20, op11_8, 1, 0,
2455 (ins QPR:$src1, QPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2457 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2458 [(set (ResTy QPR:$Vd),
2459 (ResTy (ShOp (ResTy QPR:$src1),
2460 (ResTy (MulOp QPR:$Vn,
2461 (ResTy (NEONvduplane (OpTy DPR_8:$Vm),
2464 // Neon Intrinsic-Op instructions (VABA): double- and quad-register.
2465 class N3VDIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2466 InstrItinClass itin, string OpcodeStr, string Dt,
2467 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2468 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2469 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2470 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2471 [(set DPR:$Vd, (Ty (OpNode DPR:$src1,
2472 (Ty (IntOp (Ty DPR:$Vn), (Ty DPR:$Vm))))))]>;
2473 class N3VQIntOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2474 InstrItinClass itin, string OpcodeStr, string Dt,
2475 ValueType Ty, Intrinsic IntOp, SDNode OpNode>
2476 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2477 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2478 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2479 [(set QPR:$Vd, (Ty (OpNode QPR:$src1,
2480 (Ty (IntOp (Ty QPR:$Vn), (Ty QPR:$Vm))))))]>;
2482 // Neon 3-argument intrinsics, both double- and quad-register.
2483 // The destination register is also used as the first source operand register.
2484 class N3VDInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2485 InstrItinClass itin, string OpcodeStr, string Dt,
2486 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2487 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2488 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2489 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2490 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$src1),
2491 (OpTy DPR:$Vn), (OpTy DPR:$Vm))))]>;
2492 class N3VQInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2493 InstrItinClass itin, string OpcodeStr, string Dt,
2494 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2495 : N3V<op24, op23, op21_20, op11_8, 1, op4,
2496 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm), N3RegFrm, itin,
2497 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2498 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$src1),
2499 (OpTy QPR:$Vn), (OpTy QPR:$Vm))))]>;
2501 // Long Multiply-Add/Sub operations.
2502 class N3VLMulOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2503 InstrItinClass itin, string OpcodeStr, string Dt,
2504 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2505 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2506 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2507 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2508 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2509 (TyQ (MulOp (TyD DPR:$Vn),
2510 (TyD DPR:$Vm)))))]>;
2511 class N3VLMulOpSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2512 InstrItinClass itin, string OpcodeStr, string Dt,
2513 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2514 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2515 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2517 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2519 (OpNode (TyQ QPR:$src1),
2520 (TyQ (MulOp (TyD DPR:$Vn),
2521 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),
2523 class N3VLMulOpSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2524 InstrItinClass itin, string OpcodeStr, string Dt,
2525 ValueType TyQ, ValueType TyD, SDNode MulOp, SDNode OpNode>
2526 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0, (outs QPR:$Vd),
2527 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2529 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2531 (OpNode (TyQ QPR:$src1),
2532 (TyQ (MulOp (TyD DPR:$Vn),
2533 (TyD (NEONvduplane (TyD DPR_8:$Vm),
2536 // Long Intrinsic-Op vector operations with explicit extend (VABAL).
2537 class N3VLIntExtOp<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2538 InstrItinClass itin, string OpcodeStr, string Dt,
2539 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2541 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2542 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2543 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2544 [(set QPR:$Vd, (OpNode (TyQ QPR:$src1),
2545 (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2546 (TyD DPR:$Vm)))))))]>;
2548 // Neon Long 3-argument intrinsic. The destination register is
2549 // a quad-register and is also used as the first source operand register.
2550 class N3VLInt3<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2551 InstrItinClass itin, string OpcodeStr, string Dt,
2552 ValueType TyQ, ValueType TyD, Intrinsic IntOp>
2553 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2554 (outs QPR:$Vd), (ins QPR:$src1, DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2555 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "$src1 = $Vd",
2557 (TyQ (IntOp (TyQ QPR:$src1), (TyD DPR:$Vn), (TyD DPR:$Vm))))]>;
2558 class N3VLInt3SL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2559 string OpcodeStr, string Dt,
2560 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2561 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2563 (ins QPR:$src1, DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2565 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2566 [(set (ResTy QPR:$Vd),
2567 (ResTy (IntOp (ResTy QPR:$src1),
2569 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2571 class N3VLInt3SL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2572 InstrItinClass itin, string OpcodeStr, string Dt,
2573 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2574 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2576 (ins QPR:$src1, DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2578 OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "$src1 = $Vd",
2579 [(set (ResTy QPR:$Vd),
2580 (ResTy (IntOp (ResTy QPR:$src1),
2582 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2585 // Narrowing 3-register intrinsics.
2586 class N3VNInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2587 string OpcodeStr, string Dt, ValueType TyD, ValueType TyQ,
2588 Intrinsic IntOp, bit Commutable>
2589 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2590 (outs DPR:$Vd), (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINi4D,
2591 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2592 [(set DPR:$Vd, (TyD (IntOp (TyQ QPR:$Vn), (TyQ QPR:$Vm))))]> {
2593 let isCommutable = Commutable;
2596 // Long 3-register operations.
2597 class N3VL<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2598 InstrItinClass itin, string OpcodeStr, string Dt,
2599 ValueType TyQ, ValueType TyD, SDNode OpNode, bit Commutable>
2600 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2601 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2602 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2603 [(set QPR:$Vd, (TyQ (OpNode (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2604 let isCommutable = Commutable;
2606 class N3VLSL<bit op24, bits<2> op21_20, bits<4> op11_8,
2607 InstrItinClass itin, string OpcodeStr, string Dt,
2608 ValueType TyQ, ValueType TyD, SDNode OpNode>
2609 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2610 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2611 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2613 (TyQ (OpNode (TyD DPR:$Vn),
2614 (TyD (NEONvduplane (TyD DPR_VFP2:$Vm),imm:$lane)))))]>;
2615 class N3VLSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2616 InstrItinClass itin, string OpcodeStr, string Dt,
2617 ValueType TyQ, ValueType TyD, SDNode OpNode>
2618 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2619 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2620 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2622 (TyQ (OpNode (TyD DPR:$Vn),
2623 (TyD (NEONvduplane (TyD DPR_8:$Vm), imm:$lane)))))]>;
2625 // Long 3-register operations with explicitly extended operands.
2626 class N3VLExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2627 InstrItinClass itin, string OpcodeStr, string Dt,
2628 ValueType TyQ, ValueType TyD, SDNode OpNode, SDNode ExtOp,
2630 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2631 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2632 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2633 [(set QPR:$Vd, (OpNode (TyQ (ExtOp (TyD DPR:$Vn))),
2634 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2635 let isCommutable = Commutable;
2638 // Long 3-register intrinsics with explicit extend (VABDL).
2639 class N3VLIntExt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2640 InstrItinClass itin, string OpcodeStr, string Dt,
2641 ValueType TyQ, ValueType TyD, Intrinsic IntOp, SDNode ExtOp,
2643 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2644 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2645 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2646 [(set QPR:$Vd, (TyQ (ExtOp (TyD (IntOp (TyD DPR:$Vn),
2647 (TyD DPR:$Vm))))))]> {
2648 let isCommutable = Commutable;
2651 // Long 3-register intrinsics.
2652 class N3VLInt<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2653 InstrItinClass itin, string OpcodeStr, string Dt,
2654 ValueType TyQ, ValueType TyD, Intrinsic IntOp, bit Commutable>
2655 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2656 (outs QPR:$Vd), (ins DPR:$Vn, DPR:$Vm), N3RegFrm, itin,
2657 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2658 [(set QPR:$Vd, (TyQ (IntOp (TyD DPR:$Vn), (TyD DPR:$Vm))))]> {
2659 let isCommutable = Commutable;
2661 class N3VLIntSL<bit op24, bits<2> op21_20, bits<4> op11_8, InstrItinClass itin,
2662 string OpcodeStr, string Dt,
2663 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2664 : N3VLane32<op24, 1, op21_20, op11_8, 1, 0,
2665 (outs QPR:$Vd), (ins DPR:$Vn, DPR_VFP2:$Vm, VectorIndex32:$lane),
2666 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2667 [(set (ResTy QPR:$Vd),
2668 (ResTy (IntOp (OpTy DPR:$Vn),
2669 (OpTy (NEONvduplane (OpTy DPR_VFP2:$Vm),
2671 class N3VLIntSL16<bit op24, bits<2> op21_20, bits<4> op11_8,
2672 InstrItinClass itin, string OpcodeStr, string Dt,
2673 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2674 : N3VLane16<op24, 1, op21_20, op11_8, 1, 0,
2675 (outs QPR:$Vd), (ins DPR:$Vn, DPR_8:$Vm, VectorIndex16:$lane),
2676 NVMulSLFrm, itin, OpcodeStr, Dt, "$Vd, $Vn, $Vm$lane", "",
2677 [(set (ResTy QPR:$Vd),
2678 (ResTy (IntOp (OpTy DPR:$Vn),
2679 (OpTy (NEONvduplane (OpTy DPR_8:$Vm),
2682 // Wide 3-register operations.
2683 class N3VW<bit op24, bit op23, bits<2> op21_20, bits<4> op11_8, bit op4,
2684 string OpcodeStr, string Dt, ValueType TyQ, ValueType TyD,
2685 SDNode OpNode, SDNode ExtOp, bit Commutable>
2686 : N3V<op24, op23, op21_20, op11_8, 0, op4,
2687 (outs QPR:$Vd), (ins QPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VSUBiD,
2688 OpcodeStr, Dt, "$Vd, $Vn, $Vm", "",
2689 [(set QPR:$Vd, (OpNode (TyQ QPR:$Vn),
2690 (TyQ (ExtOp (TyD DPR:$Vm)))))]> {
2691 let isCommutable = Commutable;
2694 // Pairwise long 2-register intrinsics, both double- and quad-register.
2695 class N2VDPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2696 bits<2> op17_16, bits<5> op11_7, bit op4,
2697 string OpcodeStr, string Dt,
2698 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2699 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4, (outs DPR:$Vd),
2700 (ins DPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2701 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm))))]>;
2702 class N2VQPLInt<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2703 bits<2> op17_16, bits<5> op11_7, bit op4,
2704 string OpcodeStr, string Dt,
2705 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2706 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4, (outs QPR:$Vd),
2707 (ins QPR:$Vm), IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
2708 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm))))]>;
2710 // Pairwise long 2-register accumulate intrinsics,
2711 // both double- and quad-register.
2712 // The destination register is also used as the first source operand register.
2713 class N2VDPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2714 bits<2> op17_16, bits<5> op11_7, bit op4,
2715 string OpcodeStr, string Dt,
2716 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2717 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 0, op4,
2718 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vm), IIC_VPALiD,
2719 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2720 [(set DPR:$Vd, (ResTy (IntOp (ResTy DPR:$src1), (OpTy DPR:$Vm))))]>;
2721 class N2VQPLInt2<bits<2> op24_23, bits<2> op21_20, bits<2> op19_18,
2722 bits<2> op17_16, bits<5> op11_7, bit op4,
2723 string OpcodeStr, string Dt,
2724 ValueType ResTy, ValueType OpTy, Intrinsic IntOp>
2725 : N2V<op24_23, op21_20, op19_18, op17_16, op11_7, 1, op4,
2726 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vm), IIC_VPALiQ,
2727 OpcodeStr, Dt, "$Vd, $Vm", "$src1 = $Vd",
2728 [(set QPR:$Vd, (ResTy (IntOp (ResTy QPR:$src1), (OpTy QPR:$Vm))))]>;
2730 // Shift by immediate,
2731 // both double- and quad-register.
2732 class N2VDSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2733 Format f, InstrItinClass itin, Operand ImmTy,
2734 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2735 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2736 (outs DPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), f, itin,
2737 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2738 [(set DPR:$Vd, (Ty (OpNode (Ty DPR:$Vm), (i32 imm:$SIMM))))]>;
2739 class N2VQSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2740 Format f, InstrItinClass itin, Operand ImmTy,
2741 string OpcodeStr, string Dt, ValueType Ty, SDNode OpNode>
2742 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2743 (outs QPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), f, itin,
2744 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2745 [(set QPR:$Vd, (Ty (OpNode (Ty QPR:$Vm), (i32 imm:$SIMM))))]>;
2747 // Long shift by immediate.
2748 class N2VLSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2749 string OpcodeStr, string Dt,
2750 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2751 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2752 (outs QPR:$Vd), (ins DPR:$Vm, ImmTy:$SIMM), N2RegVShLFrm,
2753 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2754 [(set QPR:$Vd, (ResTy (OpNode (OpTy DPR:$Vm),
2755 (i32 imm:$SIMM))))]>;
2757 // Narrow shift by immediate.
2758 class N2VNSh<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6, bit op4,
2759 InstrItinClass itin, string OpcodeStr, string Dt,
2760 ValueType ResTy, ValueType OpTy, Operand ImmTy, SDNode OpNode>
2761 : N2VImm<op24, op23, op11_8, op7, op6, op4,
2762 (outs DPR:$Vd), (ins QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, itin,
2763 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2764 [(set DPR:$Vd, (ResTy (OpNode (OpTy QPR:$Vm),
2765 (i32 imm:$SIMM))))]>;
2767 // Shift right by immediate and accumulate,
2768 // both double- and quad-register.
2769 class N2VDShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2770 Operand ImmTy, string OpcodeStr, string Dt,
2771 ValueType Ty, SDNode ShOp>
2772 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2773 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2774 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2775 [(set DPR:$Vd, (Ty (add DPR:$src1,
2776 (Ty (ShOp DPR:$Vm, (i32 imm:$SIMM))))))]>;
2777 class N2VQShAdd<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2778 Operand ImmTy, string OpcodeStr, string Dt,
2779 ValueType Ty, SDNode ShOp>
2780 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2781 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), N2RegVShRFrm, IIC_VPALiD,
2782 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2783 [(set QPR:$Vd, (Ty (add QPR:$src1,
2784 (Ty (ShOp QPR:$Vm, (i32 imm:$SIMM))))))]>;
2786 // Shift by immediate and insert,
2787 // both double- and quad-register.
2788 class N2VDShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2789 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2790 ValueType Ty,SDNode ShOp>
2791 : N2VImm<op24, op23, op11_8, op7, 0, op4, (outs DPR:$Vd),
2792 (ins DPR:$src1, DPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiD,
2793 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2794 [(set DPR:$Vd, (Ty (ShOp DPR:$src1, DPR:$Vm, (i32 imm:$SIMM))))]>;
2795 class N2VQShIns<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2796 Operand ImmTy, Format f, string OpcodeStr, string Dt,
2797 ValueType Ty,SDNode ShOp>
2798 : N2VImm<op24, op23, op11_8, op7, 1, op4, (outs QPR:$Vd),
2799 (ins QPR:$src1, QPR:$Vm, ImmTy:$SIMM), f, IIC_VSHLiQ,
2800 OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "$src1 = $Vd",
2801 [(set QPR:$Vd, (Ty (ShOp QPR:$src1, QPR:$Vm, (i32 imm:$SIMM))))]>;
2803 // Convert, with fractional bits immediate,
2804 // both double- and quad-register.
2805 class N2VCvtD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2806 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2808 : N2VImm<op24, op23, op11_8, op7, 0, op4,
2809 (outs DPR:$Vd), (ins DPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2810 IIC_VUNAD, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2811 [(set DPR:$Vd, (ResTy (IntOp (OpTy DPR:$Vm), (i32 imm:$SIMM))))]>;
2812 class N2VCvtQ<bit op24, bit op23, bits<4> op11_8, bit op7, bit op4,
2813 string OpcodeStr, string Dt, ValueType ResTy, ValueType OpTy,
2815 : N2VImm<op24, op23, op11_8, op7, 1, op4,
2816 (outs QPR:$Vd), (ins QPR:$Vm, neon_vcvt_imm32:$SIMM), NVCVTFrm,
2817 IIC_VUNAQ, OpcodeStr, Dt, "$Vd, $Vm, $SIMM", "",
2818 [(set QPR:$Vd, (ResTy (IntOp (OpTy QPR:$Vm), (i32 imm:$SIMM))))]>;
2820 //===----------------------------------------------------------------------===//
2822 //===----------------------------------------------------------------------===//
2824 // Abbreviations used in multiclass suffixes:
2825 // Q = quarter int (8 bit) elements
2826 // H = half int (16 bit) elements
2827 // S = single int (32 bit) elements
2828 // D = double int (64 bit) elements
2830 // Neon 2-register vector operations and intrinsics.
2832 // Neon 2-register comparisons.
2833 // source operand element sizes of 8, 16 and 32 bits:
2834 multiclass N2V_QHS_cmp<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2835 bits<5> op11_7, bit op4, string opc, string Dt,
2836 string asm, SDNode OpNode> {
2837 // 64-bit vector types.
2838 def v8i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 0, op4,
2839 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2840 opc, !strconcat(Dt, "8"), asm, "",
2841 [(set DPR:$Vd, (v8i8 (OpNode (v8i8 DPR:$Vm))))]>;
2842 def v4i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 0, op4,
2843 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2844 opc, !strconcat(Dt, "16"), asm, "",
2845 [(set DPR:$Vd, (v4i16 (OpNode (v4i16 DPR:$Vm))))]>;
2846 def v2i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2847 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2848 opc, !strconcat(Dt, "32"), asm, "",
2849 [(set DPR:$Vd, (v2i32 (OpNode (v2i32 DPR:$Vm))))]>;
2850 def v2f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 0, op4,
2851 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
2852 opc, "f32", asm, "",
2853 [(set DPR:$Vd, (v2i32 (OpNode (v2f32 DPR:$Vm))))]> {
2854 let Inst{10} = 1; // overwrite F = 1
2857 // 128-bit vector types.
2858 def v16i8 : N2V<op24_23, op21_20, 0b00, op17_16, op11_7, 1, op4,
2859 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2860 opc, !strconcat(Dt, "8"), asm, "",
2861 [(set QPR:$Vd, (v16i8 (OpNode (v16i8 QPR:$Vm))))]>;
2862 def v8i16 : N2V<op24_23, op21_20, 0b01, op17_16, op11_7, 1, op4,
2863 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2864 opc, !strconcat(Dt, "16"), asm, "",
2865 [(set QPR:$Vd, (v8i16 (OpNode (v8i16 QPR:$Vm))))]>;
2866 def v4i32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2867 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2868 opc, !strconcat(Dt, "32"), asm, "",
2869 [(set QPR:$Vd, (v4i32 (OpNode (v4i32 QPR:$Vm))))]>;
2870 def v4f32 : N2V<op24_23, op21_20, 0b10, op17_16, op11_7, 1, op4,
2871 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
2872 opc, "f32", asm, "",
2873 [(set QPR:$Vd, (v4i32 (OpNode (v4f32 QPR:$Vm))))]> {
2874 let Inst{10} = 1; // overwrite F = 1
2879 // Neon 2-register vector intrinsics,
2880 // element sizes of 8, 16 and 32 bits:
2881 multiclass N2VInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2882 bits<5> op11_7, bit op4,
2883 InstrItinClass itinD, InstrItinClass itinQ,
2884 string OpcodeStr, string Dt, Intrinsic IntOp> {
2885 // 64-bit vector types.
2886 def v8i8 : N2VDInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2887 itinD, OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
2888 def v4i16 : N2VDInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2889 itinD, OpcodeStr, !strconcat(Dt, "16"),v4i16,v4i16,IntOp>;
2890 def v2i32 : N2VDInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2891 itinD, OpcodeStr, !strconcat(Dt, "32"),v2i32,v2i32,IntOp>;
2893 // 128-bit vector types.
2894 def v16i8 : N2VQInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
2895 itinQ, OpcodeStr, !strconcat(Dt, "8"), v16i8,v16i8,IntOp>;
2896 def v8i16 : N2VQInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
2897 itinQ, OpcodeStr, !strconcat(Dt, "16"),v8i16,v8i16,IntOp>;
2898 def v4i32 : N2VQInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
2899 itinQ, OpcodeStr, !strconcat(Dt, "32"),v4i32,v4i32,IntOp>;
2903 // Neon Narrowing 2-register vector operations,
2904 // source operand element sizes of 16, 32 and 64 bits:
2905 multiclass N2VN_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2906 bits<5> op11_7, bit op6, bit op4,
2907 InstrItinClass itin, string OpcodeStr, string Dt,
2909 def v8i8 : N2VN<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2910 itin, OpcodeStr, !strconcat(Dt, "16"),
2911 v8i8, v8i16, OpNode>;
2912 def v4i16 : N2VN<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2913 itin, OpcodeStr, !strconcat(Dt, "32"),
2914 v4i16, v4i32, OpNode>;
2915 def v2i32 : N2VN<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2916 itin, OpcodeStr, !strconcat(Dt, "64"),
2917 v2i32, v2i64, OpNode>;
2920 // Neon Narrowing 2-register vector intrinsics,
2921 // source operand element sizes of 16, 32 and 64 bits:
2922 multiclass N2VNInt_HSD<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
2923 bits<5> op11_7, bit op6, bit op4,
2924 InstrItinClass itin, string OpcodeStr, string Dt,
2926 def v8i8 : N2VNInt<op24_23, op21_20, 0b00, op17_16, op11_7, op6, op4,
2927 itin, OpcodeStr, !strconcat(Dt, "16"),
2928 v8i8, v8i16, IntOp>;
2929 def v4i16 : N2VNInt<op24_23, op21_20, 0b01, op17_16, op11_7, op6, op4,
2930 itin, OpcodeStr, !strconcat(Dt, "32"),
2931 v4i16, v4i32, IntOp>;
2932 def v2i32 : N2VNInt<op24_23, op21_20, 0b10, op17_16, op11_7, op6, op4,
2933 itin, OpcodeStr, !strconcat(Dt, "64"),
2934 v2i32, v2i64, IntOp>;
2938 // Neon Lengthening 2-register vector intrinsic (currently specific to VMOVL).
2939 // source operand element sizes of 16, 32 and 64 bits:
2940 multiclass N2VL_QHS<bits<2> op24_23, bits<5> op11_7, bit op6, bit op4,
2941 string OpcodeStr, string Dt, SDNode OpNode> {
2942 def v8i16 : N2VL<op24_23, 0b00, 0b10, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2943 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, OpNode>;
2944 def v4i32 : N2VL<op24_23, 0b01, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2945 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
2946 def v2i64 : N2VL<op24_23, 0b10, 0b00, 0b00, op11_7, op6, op4, IIC_VQUNAiD,
2947 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
2951 // Neon 3-register vector operations.
2953 // First with only element sizes of 8, 16 and 32 bits:
2954 multiclass N3V_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
2955 InstrItinClass itinD16, InstrItinClass itinD32,
2956 InstrItinClass itinQ16, InstrItinClass itinQ32,
2957 string OpcodeStr, string Dt,
2958 SDNode OpNode, bit Commutable = 0> {
2959 // 64-bit vector types.
2960 def v8i8 : N3VD<op24, op23, 0b00, op11_8, op4, itinD16,
2961 OpcodeStr, !strconcat(Dt, "8"),
2962 v8i8, v8i8, OpNode, Commutable>;
2963 def v4i16 : N3VD<op24, op23, 0b01, op11_8, op4, itinD16,
2964 OpcodeStr, !strconcat(Dt, "16"),
2965 v4i16, v4i16, OpNode, Commutable>;
2966 def v2i32 : N3VD<op24, op23, 0b10, op11_8, op4, itinD32,
2967 OpcodeStr, !strconcat(Dt, "32"),
2968 v2i32, v2i32, OpNode, Commutable>;
2970 // 128-bit vector types.
2971 def v16i8 : N3VQ<op24, op23, 0b00, op11_8, op4, itinQ16,
2972 OpcodeStr, !strconcat(Dt, "8"),
2973 v16i8, v16i8, OpNode, Commutable>;
2974 def v8i16 : N3VQ<op24, op23, 0b01, op11_8, op4, itinQ16,
2975 OpcodeStr, !strconcat(Dt, "16"),
2976 v8i16, v8i16, OpNode, Commutable>;
2977 def v4i32 : N3VQ<op24, op23, 0b10, op11_8, op4, itinQ32,
2978 OpcodeStr, !strconcat(Dt, "32"),
2979 v4i32, v4i32, OpNode, Commutable>;
2982 multiclass N3VSL_HS<bits<4> op11_8, string OpcodeStr, SDNode ShOp> {
2983 def v4i16 : N3VDSL16<0b01, op11_8, OpcodeStr, "i16", v4i16, ShOp>;
2984 def v2i32 : N3VDSL<0b10, op11_8, IIC_VMULi32D, OpcodeStr, "i32", v2i32, ShOp>;
2985 def v8i16 : N3VQSL16<0b01, op11_8, OpcodeStr, "i16", v8i16, v4i16, ShOp>;
2986 def v4i32 : N3VQSL<0b10, op11_8, IIC_VMULi32Q, OpcodeStr, "i32",
2987 v4i32, v2i32, ShOp>;
2990 // ....then also with element size 64 bits:
2991 multiclass N3V_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
2992 InstrItinClass itinD, InstrItinClass itinQ,
2993 string OpcodeStr, string Dt,
2994 SDNode OpNode, bit Commutable = 0>
2995 : N3V_QHS<op24, op23, op11_8, op4, itinD, itinD, itinQ, itinQ,
2996 OpcodeStr, Dt, OpNode, Commutable> {
2997 def v1i64 : N3VD<op24, op23, 0b11, op11_8, op4, itinD,
2998 OpcodeStr, !strconcat(Dt, "64"),
2999 v1i64, v1i64, OpNode, Commutable>;
3000 def v2i64 : N3VQ<op24, op23, 0b11, op11_8, op4, itinQ,
3001 OpcodeStr, !strconcat(Dt, "64"),
3002 v2i64, v2i64, OpNode, Commutable>;
3006 // Neon 3-register vector intrinsics.
3008 // First with only element sizes of 16 and 32 bits:
3009 multiclass N3VInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3010 InstrItinClass itinD16, InstrItinClass itinD32,
3011 InstrItinClass itinQ16, InstrItinClass itinQ32,
3012 string OpcodeStr, string Dt,
3013 Intrinsic IntOp, bit Commutable = 0> {
3014 // 64-bit vector types.
3015 def v4i16 : N3VDInt<op24, op23, 0b01, op11_8, op4, f, itinD16,
3016 OpcodeStr, !strconcat(Dt, "16"),
3017 v4i16, v4i16, IntOp, Commutable>;
3018 def v2i32 : N3VDInt<op24, op23, 0b10, op11_8, op4, f, itinD32,
3019 OpcodeStr, !strconcat(Dt, "32"),
3020 v2i32, v2i32, IntOp, Commutable>;
3022 // 128-bit vector types.
3023 def v8i16 : N3VQInt<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3024 OpcodeStr, !strconcat(Dt, "16"),
3025 v8i16, v8i16, IntOp, Commutable>;
3026 def v4i32 : N3VQInt<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3027 OpcodeStr, !strconcat(Dt, "32"),
3028 v4i32, v4i32, IntOp, Commutable>;
3030 multiclass N3VInt_HSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3031 InstrItinClass itinD16, InstrItinClass itinD32,
3032 InstrItinClass itinQ16, InstrItinClass itinQ32,
3033 string OpcodeStr, string Dt,
3035 // 64-bit vector types.
3036 def v4i16 : N3VDIntSh<op24, op23, 0b01, op11_8, op4, f, itinD16,
3037 OpcodeStr, !strconcat(Dt, "16"),
3038 v4i16, v4i16, IntOp>;
3039 def v2i32 : N3VDIntSh<op24, op23, 0b10, op11_8, op4, f, itinD32,
3040 OpcodeStr, !strconcat(Dt, "32"),
3041 v2i32, v2i32, IntOp>;
3043 // 128-bit vector types.
3044 def v8i16 : N3VQIntSh<op24, op23, 0b01, op11_8, op4, f, itinQ16,
3045 OpcodeStr, !strconcat(Dt, "16"),
3046 v8i16, v8i16, IntOp>;
3047 def v4i32 : N3VQIntSh<op24, op23, 0b10, op11_8, op4, f, itinQ32,
3048 OpcodeStr, !strconcat(Dt, "32"),
3049 v4i32, v4i32, IntOp>;
3052 multiclass N3VIntSL_HS<bits<4> op11_8,
3053 InstrItinClass itinD16, InstrItinClass itinD32,
3054 InstrItinClass itinQ16, InstrItinClass itinQ32,
3055 string OpcodeStr, string Dt, Intrinsic IntOp> {
3056 def v4i16 : N3VDIntSL16<0b01, op11_8, itinD16,
3057 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp>;
3058 def v2i32 : N3VDIntSL<0b10, op11_8, itinD32,
3059 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp>;
3060 def v8i16 : N3VQIntSL16<0b01, op11_8, itinQ16,
3061 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16, IntOp>;
3062 def v4i32 : N3VQIntSL<0b10, op11_8, itinQ32,
3063 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32, IntOp>;
3066 // ....then also with element size of 8 bits:
3067 multiclass N3VInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3068 InstrItinClass itinD16, InstrItinClass itinD32,
3069 InstrItinClass itinQ16, InstrItinClass itinQ32,
3070 string OpcodeStr, string Dt,
3071 Intrinsic IntOp, bit Commutable = 0>
3072 : N3VInt_HS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3073 OpcodeStr, Dt, IntOp, Commutable> {
3074 def v8i8 : N3VDInt<op24, op23, 0b00, op11_8, op4, f, itinD16,
3075 OpcodeStr, !strconcat(Dt, "8"),
3076 v8i8, v8i8, IntOp, Commutable>;
3077 def v16i8 : N3VQInt<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3078 OpcodeStr, !strconcat(Dt, "8"),
3079 v16i8, v16i8, IntOp, Commutable>;
3081 multiclass N3VInt_QHSSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3082 InstrItinClass itinD16, InstrItinClass itinD32,
3083 InstrItinClass itinQ16, InstrItinClass itinQ32,
3084 string OpcodeStr, string Dt,
3086 : N3VInt_HSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3087 OpcodeStr, Dt, IntOp> {
3088 def v8i8 : N3VDIntSh<op24, op23, 0b00, op11_8, op4, f, itinD16,
3089 OpcodeStr, !strconcat(Dt, "8"),
3091 def v16i8 : N3VQIntSh<op24, op23, 0b00, op11_8, op4, f, itinQ16,
3092 OpcodeStr, !strconcat(Dt, "8"),
3093 v16i8, v16i8, IntOp>;
3097 // ....then also with element size of 64 bits:
3098 multiclass N3VInt_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3099 InstrItinClass itinD16, InstrItinClass itinD32,
3100 InstrItinClass itinQ16, InstrItinClass itinQ32,
3101 string OpcodeStr, string Dt,
3102 Intrinsic IntOp, bit Commutable = 0>
3103 : N3VInt_QHS<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3104 OpcodeStr, Dt, IntOp, Commutable> {
3105 def v1i64 : N3VDInt<op24, op23, 0b11, op11_8, op4, f, itinD32,
3106 OpcodeStr, !strconcat(Dt, "64"),
3107 v1i64, v1i64, IntOp, Commutable>;
3108 def v2i64 : N3VQInt<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3109 OpcodeStr, !strconcat(Dt, "64"),
3110 v2i64, v2i64, IntOp, Commutable>;
3112 multiclass N3VInt_QHSDSh<bit op24, bit op23, bits<4> op11_8, bit op4, Format f,
3113 InstrItinClass itinD16, InstrItinClass itinD32,
3114 InstrItinClass itinQ16, InstrItinClass itinQ32,
3115 string OpcodeStr, string Dt,
3117 : N3VInt_QHSSh<op24, op23, op11_8, op4, f, itinD16, itinD32, itinQ16, itinQ32,
3118 OpcodeStr, Dt, IntOp> {
3119 def v1i64 : N3VDIntSh<op24, op23, 0b11, op11_8, op4, f, itinD32,
3120 OpcodeStr, !strconcat(Dt, "64"),
3121 v1i64, v1i64, IntOp>;
3122 def v2i64 : N3VQIntSh<op24, op23, 0b11, op11_8, op4, f, itinQ32,
3123 OpcodeStr, !strconcat(Dt, "64"),
3124 v2i64, v2i64, IntOp>;
3127 // Neon Narrowing 3-register vector intrinsics,
3128 // source operand element sizes of 16, 32 and 64 bits:
3129 multiclass N3VNInt_HSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3130 string OpcodeStr, string Dt,
3131 Intrinsic IntOp, bit Commutable = 0> {
3132 def v8i8 : N3VNInt<op24, op23, 0b00, op11_8, op4,
3133 OpcodeStr, !strconcat(Dt, "16"),
3134 v8i8, v8i16, IntOp, Commutable>;
3135 def v4i16 : N3VNInt<op24, op23, 0b01, op11_8, op4,
3136 OpcodeStr, !strconcat(Dt, "32"),
3137 v4i16, v4i32, IntOp, Commutable>;
3138 def v2i32 : N3VNInt<op24, op23, 0b10, op11_8, op4,
3139 OpcodeStr, !strconcat(Dt, "64"),
3140 v2i32, v2i64, IntOp, Commutable>;
3144 // Neon Long 3-register vector operations.
3146 multiclass N3VL_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3147 InstrItinClass itin16, InstrItinClass itin32,
3148 string OpcodeStr, string Dt,
3149 SDNode OpNode, bit Commutable = 0> {
3150 def v8i16 : N3VL<op24, op23, 0b00, op11_8, op4, itin16,
3151 OpcodeStr, !strconcat(Dt, "8"),
3152 v8i16, v8i8, OpNode, Commutable>;
3153 def v4i32 : N3VL<op24, op23, 0b01, op11_8, op4, itin16,
3154 OpcodeStr, !strconcat(Dt, "16"),
3155 v4i32, v4i16, OpNode, Commutable>;
3156 def v2i64 : N3VL<op24, op23, 0b10, op11_8, op4, itin32,
3157 OpcodeStr, !strconcat(Dt, "32"),
3158 v2i64, v2i32, OpNode, Commutable>;
3161 multiclass N3VLSL_HS<bit op24, bits<4> op11_8,
3162 InstrItinClass itin, string OpcodeStr, string Dt,
3164 def v4i16 : N3VLSL16<op24, 0b01, op11_8, itin, OpcodeStr,
3165 !strconcat(Dt, "16"), v4i32, v4i16, OpNode>;
3166 def v2i32 : N3VLSL<op24, 0b10, op11_8, itin, OpcodeStr,
3167 !strconcat(Dt, "32"), v2i64, v2i32, OpNode>;
3170 multiclass N3VLExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3171 InstrItinClass itin16, InstrItinClass itin32,
3172 string OpcodeStr, string Dt,
3173 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3174 def v8i16 : N3VLExt<op24, op23, 0b00, op11_8, op4, itin16,
3175 OpcodeStr, !strconcat(Dt, "8"),
3176 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3177 def v4i32 : N3VLExt<op24, op23, 0b01, op11_8, op4, itin16,
3178 OpcodeStr, !strconcat(Dt, "16"),
3179 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3180 def v2i64 : N3VLExt<op24, op23, 0b10, op11_8, op4, itin32,
3181 OpcodeStr, !strconcat(Dt, "32"),
3182 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3185 // Neon Long 3-register vector intrinsics.
3187 // First with only element sizes of 16 and 32 bits:
3188 multiclass N3VLInt_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3189 InstrItinClass itin16, InstrItinClass itin32,
3190 string OpcodeStr, string Dt,
3191 Intrinsic IntOp, bit Commutable = 0> {
3192 def v4i32 : N3VLInt<op24, op23, 0b01, op11_8, op4, itin16,
3193 OpcodeStr, !strconcat(Dt, "16"),
3194 v4i32, v4i16, IntOp, Commutable>;
3195 def v2i64 : N3VLInt<op24, op23, 0b10, op11_8, op4, itin32,
3196 OpcodeStr, !strconcat(Dt, "32"),
3197 v2i64, v2i32, IntOp, Commutable>;
3200 multiclass N3VLIntSL_HS<bit op24, bits<4> op11_8,
3201 InstrItinClass itin, string OpcodeStr, string Dt,
3203 def v4i16 : N3VLIntSL16<op24, 0b01, op11_8, itin,
3204 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3205 def v2i32 : N3VLIntSL<op24, 0b10, op11_8, itin,
3206 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3209 // ....then also with element size of 8 bits:
3210 multiclass N3VLInt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3211 InstrItinClass itin16, InstrItinClass itin32,
3212 string OpcodeStr, string Dt,
3213 Intrinsic IntOp, bit Commutable = 0>
3214 : N3VLInt_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt,
3215 IntOp, Commutable> {
3216 def v8i16 : N3VLInt<op24, op23, 0b00, op11_8, op4, itin16,
3217 OpcodeStr, !strconcat(Dt, "8"),
3218 v8i16, v8i8, IntOp, Commutable>;
3221 // ....with explicit extend (VABDL).
3222 multiclass N3VLIntExt_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3223 InstrItinClass itin, string OpcodeStr, string Dt,
3224 Intrinsic IntOp, SDNode ExtOp, bit Commutable = 0> {
3225 def v8i16 : N3VLIntExt<op24, op23, 0b00, op11_8, op4, itin,
3226 OpcodeStr, !strconcat(Dt, "8"),
3227 v8i16, v8i8, IntOp, ExtOp, Commutable>;
3228 def v4i32 : N3VLIntExt<op24, op23, 0b01, op11_8, op4, itin,
3229 OpcodeStr, !strconcat(Dt, "16"),
3230 v4i32, v4i16, IntOp, ExtOp, Commutable>;
3231 def v2i64 : N3VLIntExt<op24, op23, 0b10, op11_8, op4, itin,
3232 OpcodeStr, !strconcat(Dt, "32"),
3233 v2i64, v2i32, IntOp, ExtOp, Commutable>;
3237 // Neon Wide 3-register vector intrinsics,
3238 // source operand element sizes of 8, 16 and 32 bits:
3239 multiclass N3VW_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3240 string OpcodeStr, string Dt,
3241 SDNode OpNode, SDNode ExtOp, bit Commutable = 0> {
3242 def v8i16 : N3VW<op24, op23, 0b00, op11_8, op4,
3243 OpcodeStr, !strconcat(Dt, "8"),
3244 v8i16, v8i8, OpNode, ExtOp, Commutable>;
3245 def v4i32 : N3VW<op24, op23, 0b01, op11_8, op4,
3246 OpcodeStr, !strconcat(Dt, "16"),
3247 v4i32, v4i16, OpNode, ExtOp, Commutable>;
3248 def v2i64 : N3VW<op24, op23, 0b10, op11_8, op4,
3249 OpcodeStr, !strconcat(Dt, "32"),
3250 v2i64, v2i32, OpNode, ExtOp, Commutable>;
3254 // Neon Multiply-Op vector operations,
3255 // element sizes of 8, 16 and 32 bits:
3256 multiclass N3VMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3257 InstrItinClass itinD16, InstrItinClass itinD32,
3258 InstrItinClass itinQ16, InstrItinClass itinQ32,
3259 string OpcodeStr, string Dt, SDNode OpNode> {
3260 // 64-bit vector types.
3261 def v8i8 : N3VDMulOp<op24, op23, 0b00, op11_8, op4, itinD16,
3262 OpcodeStr, !strconcat(Dt, "8"), v8i8, mul, OpNode>;
3263 def v4i16 : N3VDMulOp<op24, op23, 0b01, op11_8, op4, itinD16,
3264 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, OpNode>;
3265 def v2i32 : N3VDMulOp<op24, op23, 0b10, op11_8, op4, itinD32,
3266 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, OpNode>;
3268 // 128-bit vector types.
3269 def v16i8 : N3VQMulOp<op24, op23, 0b00, op11_8, op4, itinQ16,
3270 OpcodeStr, !strconcat(Dt, "8"), v16i8, mul, OpNode>;
3271 def v8i16 : N3VQMulOp<op24, op23, 0b01, op11_8, op4, itinQ16,
3272 OpcodeStr, !strconcat(Dt, "16"), v8i16, mul, OpNode>;
3273 def v4i32 : N3VQMulOp<op24, op23, 0b10, op11_8, op4, itinQ32,
3274 OpcodeStr, !strconcat(Dt, "32"), v4i32, mul, OpNode>;
3277 multiclass N3VMulOpSL_HS<bits<4> op11_8,
3278 InstrItinClass itinD16, InstrItinClass itinD32,
3279 InstrItinClass itinQ16, InstrItinClass itinQ32,
3280 string OpcodeStr, string Dt, SDNode ShOp> {
3281 def v4i16 : N3VDMulOpSL16<0b01, op11_8, itinD16,
3282 OpcodeStr, !strconcat(Dt, "16"), v4i16, mul, ShOp>;
3283 def v2i32 : N3VDMulOpSL<0b10, op11_8, itinD32,
3284 OpcodeStr, !strconcat(Dt, "32"), v2i32, mul, ShOp>;
3285 def v8i16 : N3VQMulOpSL16<0b01, op11_8, itinQ16,
3286 OpcodeStr, !strconcat(Dt, "16"), v8i16, v4i16,
3288 def v4i32 : N3VQMulOpSL<0b10, op11_8, itinQ32,
3289 OpcodeStr, !strconcat(Dt, "32"), v4i32, v2i32,
3293 // Neon Intrinsic-Op vector operations,
3294 // element sizes of 8, 16 and 32 bits:
3295 multiclass N3VIntOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3296 InstrItinClass itinD, InstrItinClass itinQ,
3297 string OpcodeStr, string Dt, Intrinsic IntOp,
3299 // 64-bit vector types.
3300 def v8i8 : N3VDIntOp<op24, op23, 0b00, op11_8, op4, itinD,
3301 OpcodeStr, !strconcat(Dt, "8"), v8i8, IntOp, OpNode>;
3302 def v4i16 : N3VDIntOp<op24, op23, 0b01, op11_8, op4, itinD,
3303 OpcodeStr, !strconcat(Dt, "16"), v4i16, IntOp, OpNode>;
3304 def v2i32 : N3VDIntOp<op24, op23, 0b10, op11_8, op4, itinD,
3305 OpcodeStr, !strconcat(Dt, "32"), v2i32, IntOp, OpNode>;
3307 // 128-bit vector types.
3308 def v16i8 : N3VQIntOp<op24, op23, 0b00, op11_8, op4, itinQ,
3309 OpcodeStr, !strconcat(Dt, "8"), v16i8, IntOp, OpNode>;
3310 def v8i16 : N3VQIntOp<op24, op23, 0b01, op11_8, op4, itinQ,
3311 OpcodeStr, !strconcat(Dt, "16"), v8i16, IntOp, OpNode>;
3312 def v4i32 : N3VQIntOp<op24, op23, 0b10, op11_8, op4, itinQ,
3313 OpcodeStr, !strconcat(Dt, "32"), v4i32, IntOp, OpNode>;
3316 // Neon 3-argument intrinsics,
3317 // element sizes of 8, 16 and 32 bits:
3318 multiclass N3VInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3319 InstrItinClass itinD, InstrItinClass itinQ,
3320 string OpcodeStr, string Dt, Intrinsic IntOp> {
3321 // 64-bit vector types.
3322 def v8i8 : N3VDInt3<op24, op23, 0b00, op11_8, op4, itinD,
3323 OpcodeStr, !strconcat(Dt, "8"), v8i8, v8i8, IntOp>;
3324 def v4i16 : N3VDInt3<op24, op23, 0b01, op11_8, op4, itinD,
3325 OpcodeStr, !strconcat(Dt, "16"), v4i16, v4i16, IntOp>;
3326 def v2i32 : N3VDInt3<op24, op23, 0b10, op11_8, op4, itinD,
3327 OpcodeStr, !strconcat(Dt, "32"), v2i32, v2i32, IntOp>;
3329 // 128-bit vector types.
3330 def v16i8 : N3VQInt3<op24, op23, 0b00, op11_8, op4, itinQ,
3331 OpcodeStr, !strconcat(Dt, "8"), v16i8, v16i8, IntOp>;
3332 def v8i16 : N3VQInt3<op24, op23, 0b01, op11_8, op4, itinQ,
3333 OpcodeStr, !strconcat(Dt, "16"), v8i16, v8i16, IntOp>;
3334 def v4i32 : N3VQInt3<op24, op23, 0b10, op11_8, op4, itinQ,
3335 OpcodeStr, !strconcat(Dt, "32"), v4i32, v4i32, IntOp>;
3339 // Neon Long Multiply-Op vector operations,
3340 // element sizes of 8, 16 and 32 bits:
3341 multiclass N3VLMulOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3342 InstrItinClass itin16, InstrItinClass itin32,
3343 string OpcodeStr, string Dt, SDNode MulOp,
3345 def v8i16 : N3VLMulOp<op24, op23, 0b00, op11_8, op4, itin16, OpcodeStr,
3346 !strconcat(Dt, "8"), v8i16, v8i8, MulOp, OpNode>;
3347 def v4i32 : N3VLMulOp<op24, op23, 0b01, op11_8, op4, itin16, OpcodeStr,
3348 !strconcat(Dt, "16"), v4i32, v4i16, MulOp, OpNode>;
3349 def v2i64 : N3VLMulOp<op24, op23, 0b10, op11_8, op4, itin32, OpcodeStr,
3350 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3353 multiclass N3VLMulOpSL_HS<bit op24, bits<4> op11_8, string OpcodeStr,
3354 string Dt, SDNode MulOp, SDNode OpNode> {
3355 def v4i16 : N3VLMulOpSL16<op24, 0b01, op11_8, IIC_VMACi16D, OpcodeStr,
3356 !strconcat(Dt,"16"), v4i32, v4i16, MulOp, OpNode>;
3357 def v2i32 : N3VLMulOpSL<op24, 0b10, op11_8, IIC_VMACi32D, OpcodeStr,
3358 !strconcat(Dt, "32"), v2i64, v2i32, MulOp, OpNode>;
3362 // Neon Long 3-argument intrinsics.
3364 // First with only element sizes of 16 and 32 bits:
3365 multiclass N3VLInt3_HS<bit op24, bit op23, bits<4> op11_8, bit op4,
3366 InstrItinClass itin16, InstrItinClass itin32,
3367 string OpcodeStr, string Dt, Intrinsic IntOp> {
3368 def v4i32 : N3VLInt3<op24, op23, 0b01, op11_8, op4, itin16,
3369 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, IntOp>;
3370 def v2i64 : N3VLInt3<op24, op23, 0b10, op11_8, op4, itin32,
3371 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3374 multiclass N3VLInt3SL_HS<bit op24, bits<4> op11_8,
3375 string OpcodeStr, string Dt, Intrinsic IntOp> {
3376 def v4i16 : N3VLInt3SL16<op24, 0b01, op11_8, IIC_VMACi16D,
3377 OpcodeStr, !strconcat(Dt,"16"), v4i32, v4i16, IntOp>;
3378 def v2i32 : N3VLInt3SL<op24, 0b10, op11_8, IIC_VMACi32D,
3379 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, IntOp>;
3382 // ....then also with element size of 8 bits:
3383 multiclass N3VLInt3_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3384 InstrItinClass itin16, InstrItinClass itin32,
3385 string OpcodeStr, string Dt, Intrinsic IntOp>
3386 : N3VLInt3_HS<op24, op23, op11_8, op4, itin16, itin32, OpcodeStr, Dt, IntOp> {
3387 def v8i16 : N3VLInt3<op24, op23, 0b00, op11_8, op4, itin16,
3388 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, IntOp>;
3391 // ....with explicit extend (VABAL).
3392 multiclass N3VLIntExtOp_QHS<bit op24, bit op23, bits<4> op11_8, bit op4,
3393 InstrItinClass itin, string OpcodeStr, string Dt,
3394 Intrinsic IntOp, SDNode ExtOp, SDNode OpNode> {
3395 def v8i16 : N3VLIntExtOp<op24, op23, 0b00, op11_8, op4, itin,
3396 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8,
3397 IntOp, ExtOp, OpNode>;
3398 def v4i32 : N3VLIntExtOp<op24, op23, 0b01, op11_8, op4, itin,
3399 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16,
3400 IntOp, ExtOp, OpNode>;
3401 def v2i64 : N3VLIntExtOp<op24, op23, 0b10, op11_8, op4, itin,
3402 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32,
3403 IntOp, ExtOp, OpNode>;
3407 // Neon Pairwise long 2-register intrinsics,
3408 // element sizes of 8, 16 and 32 bits:
3409 multiclass N2VPLInt_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3410 bits<5> op11_7, bit op4,
3411 string OpcodeStr, string Dt, Intrinsic IntOp> {
3412 // 64-bit vector types.
3413 def v8i8 : N2VDPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3414 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3415 def v4i16 : N2VDPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3416 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3417 def v2i32 : N2VDPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3418 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3420 // 128-bit vector types.
3421 def v16i8 : N2VQPLInt<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3422 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3423 def v8i16 : N2VQPLInt<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3424 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3425 def v4i32 : N2VQPLInt<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3426 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3430 // Neon Pairwise long 2-register accumulate intrinsics,
3431 // element sizes of 8, 16 and 32 bits:
3432 multiclass N2VPLInt2_QHS<bits<2> op24_23, bits<2> op21_20, bits<2> op17_16,
3433 bits<5> op11_7, bit op4,
3434 string OpcodeStr, string Dt, Intrinsic IntOp> {
3435 // 64-bit vector types.
3436 def v8i8 : N2VDPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3437 OpcodeStr, !strconcat(Dt, "8"), v4i16, v8i8, IntOp>;
3438 def v4i16 : N2VDPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3439 OpcodeStr, !strconcat(Dt, "16"), v2i32, v4i16, IntOp>;
3440 def v2i32 : N2VDPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3441 OpcodeStr, !strconcat(Dt, "32"), v1i64, v2i32, IntOp>;
3443 // 128-bit vector types.
3444 def v16i8 : N2VQPLInt2<op24_23, op21_20, 0b00, op17_16, op11_7, op4,
3445 OpcodeStr, !strconcat(Dt, "8"), v8i16, v16i8, IntOp>;
3446 def v8i16 : N2VQPLInt2<op24_23, op21_20, 0b01, op17_16, op11_7, op4,
3447 OpcodeStr, !strconcat(Dt, "16"), v4i32, v8i16, IntOp>;
3448 def v4i32 : N2VQPLInt2<op24_23, op21_20, 0b10, op17_16, op11_7, op4,
3449 OpcodeStr, !strconcat(Dt, "32"), v2i64, v4i32, IntOp>;
3453 // Neon 2-register vector shift by immediate,
3454 // with f of either N2RegVShLFrm or N2RegVShRFrm
3455 // element sizes of 8, 16, 32 and 64 bits:
3456 multiclass N2VShL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3457 InstrItinClass itin, string OpcodeStr, string Dt,
3459 // 64-bit vector types.
3460 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3461 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3462 let Inst{21-19} = 0b001; // imm6 = 001xxx
3464 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3465 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3466 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3468 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3469 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3470 let Inst{21} = 0b1; // imm6 = 1xxxxx
3472 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3473 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3476 // 128-bit vector types.
3477 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3478 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3479 let Inst{21-19} = 0b001; // imm6 = 001xxx
3481 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3482 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3483 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3485 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShLFrm, itin, i32imm,
3486 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3487 let Inst{21} = 0b1; // imm6 = 1xxxxx
3489 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShLFrm, itin, i32imm,
3490 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3493 multiclass N2VShR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3494 InstrItinClass itin, string OpcodeStr, string Dt,
3496 // 64-bit vector types.
3497 def v8i8 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3498 OpcodeStr, !strconcat(Dt, "8"), v8i8, OpNode> {
3499 let Inst{21-19} = 0b001; // imm6 = 001xxx
3501 def v4i16 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3502 OpcodeStr, !strconcat(Dt, "16"), v4i16, OpNode> {
3503 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3505 def v2i32 : N2VDSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3506 OpcodeStr, !strconcat(Dt, "32"), v2i32, OpNode> {
3507 let Inst{21} = 0b1; // imm6 = 1xxxxx
3509 def v1i64 : N2VDSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3510 OpcodeStr, !strconcat(Dt, "64"), v1i64, OpNode>;
3513 // 128-bit vector types.
3514 def v16i8 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm8,
3515 OpcodeStr, !strconcat(Dt, "8"), v16i8, OpNode> {
3516 let Inst{21-19} = 0b001; // imm6 = 001xxx
3518 def v8i16 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm16,
3519 OpcodeStr, !strconcat(Dt, "16"), v8i16, OpNode> {
3520 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3522 def v4i32 : N2VQSh<op24, op23, op11_8, 0, op4, N2RegVShRFrm, itin, shr_imm32,
3523 OpcodeStr, !strconcat(Dt, "32"), v4i32, OpNode> {
3524 let Inst{21} = 0b1; // imm6 = 1xxxxx
3526 def v2i64 : N2VQSh<op24, op23, op11_8, 1, op4, N2RegVShRFrm, itin, shr_imm64,
3527 OpcodeStr, !strconcat(Dt, "64"), v2i64, OpNode>;
3531 // Neon Shift-Accumulate vector operations,
3532 // element sizes of 8, 16, 32 and 64 bits:
3533 multiclass N2VShAdd_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3534 string OpcodeStr, string Dt, SDNode ShOp> {
3535 // 64-bit vector types.
3536 def v8i8 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3537 OpcodeStr, !strconcat(Dt, "8"), v8i8, ShOp> {
3538 let Inst{21-19} = 0b001; // imm6 = 001xxx
3540 def v4i16 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3541 OpcodeStr, !strconcat(Dt, "16"), v4i16, ShOp> {
3542 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3544 def v2i32 : N2VDShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3545 OpcodeStr, !strconcat(Dt, "32"), v2i32, ShOp> {
3546 let Inst{21} = 0b1; // imm6 = 1xxxxx
3548 def v1i64 : N2VDShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3549 OpcodeStr, !strconcat(Dt, "64"), v1i64, ShOp>;
3552 // 128-bit vector types.
3553 def v16i8 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm8,
3554 OpcodeStr, !strconcat(Dt, "8"), v16i8, ShOp> {
3555 let Inst{21-19} = 0b001; // imm6 = 001xxx
3557 def v8i16 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm16,
3558 OpcodeStr, !strconcat(Dt, "16"), v8i16, ShOp> {
3559 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3561 def v4i32 : N2VQShAdd<op24, op23, op11_8, 0, op4, shr_imm32,
3562 OpcodeStr, !strconcat(Dt, "32"), v4i32, ShOp> {
3563 let Inst{21} = 0b1; // imm6 = 1xxxxx
3565 def v2i64 : N2VQShAdd<op24, op23, op11_8, 1, op4, shr_imm64,
3566 OpcodeStr, !strconcat(Dt, "64"), v2i64, ShOp>;
3570 // Neon Shift-Insert vector operations,
3571 // with f of either N2RegVShLFrm or N2RegVShRFrm
3572 // element sizes of 8, 16, 32 and 64 bits:
3573 multiclass N2VShInsL_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3575 // 64-bit vector types.
3576 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3577 N2RegVShLFrm, OpcodeStr, "8", v8i8, NEONvsli> {
3578 let Inst{21-19} = 0b001; // imm6 = 001xxx
3580 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3581 N2RegVShLFrm, OpcodeStr, "16", v4i16, NEONvsli> {
3582 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3584 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, i32imm,
3585 N2RegVShLFrm, OpcodeStr, "32", v2i32, NEONvsli> {
3586 let Inst{21} = 0b1; // imm6 = 1xxxxx
3588 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, i32imm,
3589 N2RegVShLFrm, OpcodeStr, "64", v1i64, NEONvsli>;
3592 // 128-bit vector types.
3593 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3594 N2RegVShLFrm, OpcodeStr, "8", v16i8, NEONvsli> {
3595 let Inst{21-19} = 0b001; // imm6 = 001xxx
3597 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3598 N2RegVShLFrm, OpcodeStr, "16", v8i16, NEONvsli> {
3599 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3601 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, i32imm,
3602 N2RegVShLFrm, OpcodeStr, "32", v4i32, NEONvsli> {
3603 let Inst{21} = 0b1; // imm6 = 1xxxxx
3605 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, i32imm,
3606 N2RegVShLFrm, OpcodeStr, "64", v2i64, NEONvsli>;
3609 multiclass N2VShInsR_QHSD<bit op24, bit op23, bits<4> op11_8, bit op4,
3611 // 64-bit vector types.
3612 def v8i8 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3613 N2RegVShRFrm, OpcodeStr, "8", v8i8, NEONvsri> {
3614 let Inst{21-19} = 0b001; // imm6 = 001xxx
3616 def v4i16 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3617 N2RegVShRFrm, OpcodeStr, "16", v4i16, NEONvsri> {
3618 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3620 def v2i32 : N2VDShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3621 N2RegVShRFrm, OpcodeStr, "32", v2i32, NEONvsri> {
3622 let Inst{21} = 0b1; // imm6 = 1xxxxx
3624 def v1i64 : N2VDShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3625 N2RegVShRFrm, OpcodeStr, "64", v1i64, NEONvsri>;
3628 // 128-bit vector types.
3629 def v16i8 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm8,
3630 N2RegVShRFrm, OpcodeStr, "8", v16i8, NEONvsri> {
3631 let Inst{21-19} = 0b001; // imm6 = 001xxx
3633 def v8i16 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm16,
3634 N2RegVShRFrm, OpcodeStr, "16", v8i16, NEONvsri> {
3635 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3637 def v4i32 : N2VQShIns<op24, op23, op11_8, 0, op4, shr_imm32,
3638 N2RegVShRFrm, OpcodeStr, "32", v4i32, NEONvsri> {
3639 let Inst{21} = 0b1; // imm6 = 1xxxxx
3641 def v2i64 : N2VQShIns<op24, op23, op11_8, 1, op4, shr_imm64,
3642 N2RegVShRFrm, OpcodeStr, "64", v2i64, NEONvsri>;
3646 // Neon Shift Long operations,
3647 // element sizes of 8, 16, 32 bits:
3648 multiclass N2VLSh_QHS<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3649 bit op4, string OpcodeStr, string Dt, SDNode OpNode> {
3650 def v8i16 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3651 OpcodeStr, !strconcat(Dt, "8"), v8i16, v8i8, imm1_7, OpNode> {
3652 let Inst{21-19} = 0b001; // imm6 = 001xxx
3654 def v4i32 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3655 OpcodeStr, !strconcat(Dt, "16"), v4i32, v4i16, imm1_15, OpNode> {
3656 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3658 def v2i64 : N2VLSh<op24, op23, op11_8, op7, op6, op4,
3659 OpcodeStr, !strconcat(Dt, "32"), v2i64, v2i32, imm1_31, OpNode> {
3660 let Inst{21} = 0b1; // imm6 = 1xxxxx
3664 // Neon Shift Narrow operations,
3665 // element sizes of 16, 32, 64 bits:
3666 multiclass N2VNSh_HSD<bit op24, bit op23, bits<4> op11_8, bit op7, bit op6,
3667 bit op4, InstrItinClass itin, string OpcodeStr, string Dt,
3669 def v8i8 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3670 OpcodeStr, !strconcat(Dt, "16"),
3671 v8i8, v8i16, shr_imm8, OpNode> {
3672 let Inst{21-19} = 0b001; // imm6 = 001xxx
3674 def v4i16 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3675 OpcodeStr, !strconcat(Dt, "32"),
3676 v4i16, v4i32, shr_imm16, OpNode> {
3677 let Inst{21-20} = 0b01; // imm6 = 01xxxx
3679 def v2i32 : N2VNSh<op24, op23, op11_8, op7, op6, op4, itin,
3680 OpcodeStr, !strconcat(Dt, "64"),
3681 v2i32, v2i64, shr_imm32, OpNode> {
3682 let Inst{21} = 0b1; // imm6 = 1xxxxx
3686 //===----------------------------------------------------------------------===//
3687 // Instruction Definitions.
3688 //===----------------------------------------------------------------------===//
3690 // Vector Add Operations.
3692 // VADD : Vector Add (integer and floating-point)
3693 defm VADD : N3V_QHSD<0, 0, 0b1000, 0, IIC_VBINiD, IIC_VBINiQ, "vadd", "i",
3695 def VADDfd : N3VD<0, 0, 0b00, 0b1101, 0, IIC_VBIND, "vadd", "f32",
3696 v2f32, v2f32, fadd, 1>;
3697 def VADDfq : N3VQ<0, 0, 0b00, 0b1101, 0, IIC_VBINQ, "vadd", "f32",
3698 v4f32, v4f32, fadd, 1>;
3699 // VADDL : Vector Add Long (Q = D + D)
3700 defm VADDLs : N3VLExt_QHS<0,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3701 "vaddl", "s", add, sext, 1>;
3702 defm VADDLu : N3VLExt_QHS<1,1,0b0000,0, IIC_VSHLiD, IIC_VSHLiD,
3703 "vaddl", "u", add, zext, 1>;
3704 // VADDW : Vector Add Wide (Q = Q + D)
3705 defm VADDWs : N3VW_QHS<0,1,0b0001,0, "vaddw", "s", add, sext, 0>;
3706 defm VADDWu : N3VW_QHS<1,1,0b0001,0, "vaddw", "u", add, zext, 0>;
3707 // VHADD : Vector Halving Add
3708 defm VHADDs : N3VInt_QHS<0, 0, 0b0000, 0, N3RegFrm,
3709 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3710 "vhadd", "s", int_arm_neon_vhadds, 1>;
3711 defm VHADDu : N3VInt_QHS<1, 0, 0b0000, 0, N3RegFrm,
3712 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3713 "vhadd", "u", int_arm_neon_vhaddu, 1>;
3714 // VRHADD : Vector Rounding Halving Add
3715 defm VRHADDs : N3VInt_QHS<0, 0, 0b0001, 0, N3RegFrm,
3716 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3717 "vrhadd", "s", int_arm_neon_vrhadds, 1>;
3718 defm VRHADDu : N3VInt_QHS<1, 0, 0b0001, 0, N3RegFrm,
3719 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3720 "vrhadd", "u", int_arm_neon_vrhaddu, 1>;
3721 // VQADD : Vector Saturating Add
3722 defm VQADDs : N3VInt_QHSD<0, 0, 0b0000, 1, N3RegFrm,
3723 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3724 "vqadd", "s", int_arm_neon_vqadds, 1>;
3725 defm VQADDu : N3VInt_QHSD<1, 0, 0b0000, 1, N3RegFrm,
3726 IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q, IIC_VBINi4Q,
3727 "vqadd", "u", int_arm_neon_vqaddu, 1>;
3728 // VADDHN : Vector Add and Narrow Returning High Half (D = Q + Q)
3729 defm VADDHN : N3VNInt_HSD<0,1,0b0100,0, "vaddhn", "i",
3730 int_arm_neon_vaddhn, 1>;
3731 // VRADDHN : Vector Rounding Add and Narrow Returning High Half (D = Q + Q)
3732 defm VRADDHN : N3VNInt_HSD<1,1,0b0100,0, "vraddhn", "i",
3733 int_arm_neon_vraddhn, 1>;
3735 // Vector Multiply Operations.
3737 // VMUL : Vector Multiply (integer, polynomial and floating-point)
3738 defm VMUL : N3V_QHS<0, 0, 0b1001, 1, IIC_VMULi16D, IIC_VMULi32D,
3739 IIC_VMULi16Q, IIC_VMULi32Q, "vmul", "i", mul, 1>;
3740 def VMULpd : N3VDInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16D, "vmul",
3741 "p8", v8i8, v8i8, int_arm_neon_vmulp, 1>;
3742 def VMULpq : N3VQInt<1, 0, 0b00, 0b1001, 1, N3RegFrm, IIC_VMULi16Q, "vmul",
3743 "p8", v16i8, v16i8, int_arm_neon_vmulp, 1>;
3744 def VMULfd : N3VD<1, 0, 0b00, 0b1101, 1, IIC_VFMULD, "vmul", "f32",
3745 v2f32, v2f32, fmul, 1>;
3746 def VMULfq : N3VQ<1, 0, 0b00, 0b1101, 1, IIC_VFMULQ, "vmul", "f32",
3747 v4f32, v4f32, fmul, 1>;
3748 defm VMULsl : N3VSL_HS<0b1000, "vmul", mul>;
3749 def VMULslfd : N3VDSL<0b10, 0b1001, IIC_VBIND, "vmul", "f32", v2f32, fmul>;
3750 def VMULslfq : N3VQSL<0b10, 0b1001, IIC_VBINQ, "vmul", "f32", v4f32,
3753 def : Pat<(v8i16 (mul (v8i16 QPR:$src1),
3754 (v8i16 (NEONvduplane (v8i16 QPR:$src2), imm:$lane)))),
3755 (v8i16 (VMULslv8i16 (v8i16 QPR:$src1),
3756 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3757 (DSubReg_i16_reg imm:$lane))),
3758 (SubReg_i16_lane imm:$lane)))>;
3759 def : Pat<(v4i32 (mul (v4i32 QPR:$src1),
3760 (v4i32 (NEONvduplane (v4i32 QPR:$src2), imm:$lane)))),
3761 (v4i32 (VMULslv4i32 (v4i32 QPR:$src1),
3762 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3763 (DSubReg_i32_reg imm:$lane))),
3764 (SubReg_i32_lane imm:$lane)))>;
3765 def : Pat<(v4f32 (fmul (v4f32 QPR:$src1),
3766 (v4f32 (NEONvduplane (v4f32 QPR:$src2), imm:$lane)))),
3767 (v4f32 (VMULslfq (v4f32 QPR:$src1),
3768 (v2f32 (EXTRACT_SUBREG QPR:$src2,
3769 (DSubReg_i32_reg imm:$lane))),
3770 (SubReg_i32_lane imm:$lane)))>;
3772 // VQDMULH : Vector Saturating Doubling Multiply Returning High Half
3773 defm VQDMULH : N3VInt_HS<0, 0, 0b1011, 0, N3RegFrm, IIC_VMULi16D, IIC_VMULi32D,
3774 IIC_VMULi16Q, IIC_VMULi32Q,
3775 "vqdmulh", "s", int_arm_neon_vqdmulh, 1>;
3776 defm VQDMULHsl: N3VIntSL_HS<0b1100, IIC_VMULi16D, IIC_VMULi32D,
3777 IIC_VMULi16Q, IIC_VMULi32Q,
3778 "vqdmulh", "s", int_arm_neon_vqdmulh>;
3779 def : Pat<(v8i16 (int_arm_neon_vqdmulh (v8i16 QPR:$src1),
3780 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3782 (v8i16 (VQDMULHslv8i16 (v8i16 QPR:$src1),
3783 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3784 (DSubReg_i16_reg imm:$lane))),
3785 (SubReg_i16_lane imm:$lane)))>;
3786 def : Pat<(v4i32 (int_arm_neon_vqdmulh (v4i32 QPR:$src1),
3787 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3789 (v4i32 (VQDMULHslv4i32 (v4i32 QPR:$src1),
3790 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3791 (DSubReg_i32_reg imm:$lane))),
3792 (SubReg_i32_lane imm:$lane)))>;
3794 // VQRDMULH : Vector Rounding Saturating Doubling Multiply Returning High Half
3795 defm VQRDMULH : N3VInt_HS<1, 0, 0b1011, 0, N3RegFrm,
3796 IIC_VMULi16D,IIC_VMULi32D,IIC_VMULi16Q,IIC_VMULi32Q,
3797 "vqrdmulh", "s", int_arm_neon_vqrdmulh, 1>;
3798 defm VQRDMULHsl : N3VIntSL_HS<0b1101, IIC_VMULi16D, IIC_VMULi32D,
3799 IIC_VMULi16Q, IIC_VMULi32Q,
3800 "vqrdmulh", "s", int_arm_neon_vqrdmulh>;
3801 def : Pat<(v8i16 (int_arm_neon_vqrdmulh (v8i16 QPR:$src1),
3802 (v8i16 (NEONvduplane (v8i16 QPR:$src2),
3804 (v8i16 (VQRDMULHslv8i16 (v8i16 QPR:$src1),
3805 (v4i16 (EXTRACT_SUBREG QPR:$src2,
3806 (DSubReg_i16_reg imm:$lane))),
3807 (SubReg_i16_lane imm:$lane)))>;
3808 def : Pat<(v4i32 (int_arm_neon_vqrdmulh (v4i32 QPR:$src1),
3809 (v4i32 (NEONvduplane (v4i32 QPR:$src2),
3811 (v4i32 (VQRDMULHslv4i32 (v4i32 QPR:$src1),
3812 (v2i32 (EXTRACT_SUBREG QPR:$src2,
3813 (DSubReg_i32_reg imm:$lane))),
3814 (SubReg_i32_lane imm:$lane)))>;
3816 // VMULL : Vector Multiply Long (integer and polynomial) (Q = D * D)
3817 defm VMULLs : N3VL_QHS<0,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3818 "vmull", "s", NEONvmulls, 1>;
3819 defm VMULLu : N3VL_QHS<1,1,0b1100,0, IIC_VMULi16D, IIC_VMULi32D,
3820 "vmull", "u", NEONvmullu, 1>;
3821 def VMULLp : N3VLInt<0, 1, 0b00, 0b1110, 0, IIC_VMULi16D, "vmull", "p8",
3822 v8i16, v8i8, int_arm_neon_vmullp, 1>;
3823 defm VMULLsls : N3VLSL_HS<0, 0b1010, IIC_VMULi16D, "vmull", "s", NEONvmulls>;
3824 defm VMULLslu : N3VLSL_HS<1, 0b1010, IIC_VMULi16D, "vmull", "u", NEONvmullu>;
3826 // VQDMULL : Vector Saturating Doubling Multiply Long (Q = D * D)
3827 defm VQDMULL : N3VLInt_HS<0,1,0b1101,0, IIC_VMULi16D, IIC_VMULi32D,
3828 "vqdmull", "s", int_arm_neon_vqdmull, 1>;
3829 defm VQDMULLsl: N3VLIntSL_HS<0, 0b1011, IIC_VMULi16D,
3830 "vqdmull", "s", int_arm_neon_vqdmull>;
3832 // Vector Multiply-Accumulate and Multiply-Subtract Operations.
3834 // VMLA : Vector Multiply Accumulate (integer and floating-point)
3835 defm VMLA : N3VMulOp_QHS<0, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3836 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3837 def VMLAfd : N3VDMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACD, "vmla", "f32",
3838 v2f32, fmul_su, fadd_mlx>,
3839 Requires<[HasNEON, UseFPVMLx]>;
3840 def VMLAfq : N3VQMulOp<0, 0, 0b00, 0b1101, 1, IIC_VMACQ, "vmla", "f32",
3841 v4f32, fmul_su, fadd_mlx>,
3842 Requires<[HasNEON, UseFPVMLx]>;
3843 defm VMLAsl : N3VMulOpSL_HS<0b0000, IIC_VMACi16D, IIC_VMACi32D,
3844 IIC_VMACi16Q, IIC_VMACi32Q, "vmla", "i", add>;
3845 def VMLAslfd : N3VDMulOpSL<0b10, 0b0001, IIC_VMACD, "vmla", "f32",
3846 v2f32, fmul_su, fadd_mlx>,
3847 Requires<[HasNEON, UseFPVMLx]>;
3848 def VMLAslfq : N3VQMulOpSL<0b10, 0b0001, IIC_VMACQ, "vmla", "f32",
3849 v4f32, v2f32, fmul_su, fadd_mlx>,
3850 Requires<[HasNEON, UseFPVMLx]>;
3852 def : Pat<(v8i16 (add (v8i16 QPR:$src1),
3853 (mul (v8i16 QPR:$src2),
3854 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3855 (v8i16 (VMLAslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3856 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3857 (DSubReg_i16_reg imm:$lane))),
3858 (SubReg_i16_lane imm:$lane)))>;
3860 def : Pat<(v4i32 (add (v4i32 QPR:$src1),
3861 (mul (v4i32 QPR:$src2),
3862 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3863 (v4i32 (VMLAslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3864 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3865 (DSubReg_i32_reg imm:$lane))),
3866 (SubReg_i32_lane imm:$lane)))>;
3868 def : Pat<(v4f32 (fadd_mlx (v4f32 QPR:$src1),
3869 (fmul_su (v4f32 QPR:$src2),
3870 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3871 (v4f32 (VMLAslfq (v4f32 QPR:$src1),
3873 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3874 (DSubReg_i32_reg imm:$lane))),
3875 (SubReg_i32_lane imm:$lane)))>,
3876 Requires<[HasNEON, UseFPVMLx]>;
3878 // VMLAL : Vector Multiply Accumulate Long (Q += D * D)
3879 defm VMLALs : N3VLMulOp_QHS<0,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3880 "vmlal", "s", NEONvmulls, add>;
3881 defm VMLALu : N3VLMulOp_QHS<1,1,0b1000,0, IIC_VMACi16D, IIC_VMACi32D,
3882 "vmlal", "u", NEONvmullu, add>;
3884 defm VMLALsls : N3VLMulOpSL_HS<0, 0b0010, "vmlal", "s", NEONvmulls, add>;
3885 defm VMLALslu : N3VLMulOpSL_HS<1, 0b0010, "vmlal", "u", NEONvmullu, add>;
3887 // VQDMLAL : Vector Saturating Doubling Multiply Accumulate Long (Q += D * D)
3888 defm VQDMLAL : N3VLInt3_HS<0, 1, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3889 "vqdmlal", "s", int_arm_neon_vqdmlal>;
3890 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3892 // VMLS : Vector Multiply Subtract (integer and floating-point)
3893 defm VMLS : N3VMulOp_QHS<1, 0, 0b1001, 0, IIC_VMACi16D, IIC_VMACi32D,
3894 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3895 def VMLSfd : N3VDMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACD, "vmls", "f32",
3896 v2f32, fmul_su, fsub_mlx>,
3897 Requires<[HasNEON, UseFPVMLx]>;
3898 def VMLSfq : N3VQMulOp<0, 0, 0b10, 0b1101, 1, IIC_VMACQ, "vmls", "f32",
3899 v4f32, fmul_su, fsub_mlx>,
3900 Requires<[HasNEON, UseFPVMLx]>;
3901 defm VMLSsl : N3VMulOpSL_HS<0b0100, IIC_VMACi16D, IIC_VMACi32D,
3902 IIC_VMACi16Q, IIC_VMACi32Q, "vmls", "i", sub>;
3903 def VMLSslfd : N3VDMulOpSL<0b10, 0b0101, IIC_VMACD, "vmls", "f32",
3904 v2f32, fmul_su, fsub_mlx>,
3905 Requires<[HasNEON, UseFPVMLx]>;
3906 def VMLSslfq : N3VQMulOpSL<0b10, 0b0101, IIC_VMACQ, "vmls", "f32",
3907 v4f32, v2f32, fmul_su, fsub_mlx>,
3908 Requires<[HasNEON, UseFPVMLx]>;
3910 def : Pat<(v8i16 (sub (v8i16 QPR:$src1),
3911 (mul (v8i16 QPR:$src2),
3912 (v8i16 (NEONvduplane (v8i16 QPR:$src3), imm:$lane))))),
3913 (v8i16 (VMLSslv8i16 (v8i16 QPR:$src1), (v8i16 QPR:$src2),
3914 (v4i16 (EXTRACT_SUBREG QPR:$src3,
3915 (DSubReg_i16_reg imm:$lane))),
3916 (SubReg_i16_lane imm:$lane)))>;
3918 def : Pat<(v4i32 (sub (v4i32 QPR:$src1),
3919 (mul (v4i32 QPR:$src2),
3920 (v4i32 (NEONvduplane (v4i32 QPR:$src3), imm:$lane))))),
3921 (v4i32 (VMLSslv4i32 (v4i32 QPR:$src1), (v4i32 QPR:$src2),
3922 (v2i32 (EXTRACT_SUBREG QPR:$src3,
3923 (DSubReg_i32_reg imm:$lane))),
3924 (SubReg_i32_lane imm:$lane)))>;
3926 def : Pat<(v4f32 (fsub_mlx (v4f32 QPR:$src1),
3927 (fmul_su (v4f32 QPR:$src2),
3928 (v4f32 (NEONvduplane (v4f32 QPR:$src3), imm:$lane))))),
3929 (v4f32 (VMLSslfq (v4f32 QPR:$src1), (v4f32 QPR:$src2),
3930 (v2f32 (EXTRACT_SUBREG QPR:$src3,
3931 (DSubReg_i32_reg imm:$lane))),
3932 (SubReg_i32_lane imm:$lane)))>,
3933 Requires<[HasNEON, UseFPVMLx]>;
3935 // VMLSL : Vector Multiply Subtract Long (Q -= D * D)
3936 defm VMLSLs : N3VLMulOp_QHS<0,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3937 "vmlsl", "s", NEONvmulls, sub>;
3938 defm VMLSLu : N3VLMulOp_QHS<1,1,0b1010,0, IIC_VMACi16D, IIC_VMACi32D,
3939 "vmlsl", "u", NEONvmullu, sub>;
3941 defm VMLSLsls : N3VLMulOpSL_HS<0, 0b0110, "vmlsl", "s", NEONvmulls, sub>;
3942 defm VMLSLslu : N3VLMulOpSL_HS<1, 0b0110, "vmlsl", "u", NEONvmullu, sub>;
3944 // VQDMLSL : Vector Saturating Doubling Multiply Subtract Long (Q -= D * D)
3945 defm VQDMLSL : N3VLInt3_HS<0, 1, 0b1011, 0, IIC_VMACi16D, IIC_VMACi32D,
3946 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3947 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3949 // Vector Subtract Operations.
3951 // VSUB : Vector Subtract (integer and floating-point)
3952 defm VSUB : N3V_QHSD<1, 0, 0b1000, 0, IIC_VSUBiD, IIC_VSUBiQ,
3953 "vsub", "i", sub, 0>;
3954 def VSUBfd : N3VD<0, 0, 0b10, 0b1101, 0, IIC_VBIND, "vsub", "f32",
3955 v2f32, v2f32, fsub, 0>;
3956 def VSUBfq : N3VQ<0, 0, 0b10, 0b1101, 0, IIC_VBINQ, "vsub", "f32",
3957 v4f32, v4f32, fsub, 0>;
3958 // VSUBL : Vector Subtract Long (Q = D - D)
3959 defm VSUBLs : N3VLExt_QHS<0,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3960 "vsubl", "s", sub, sext, 0>;
3961 defm VSUBLu : N3VLExt_QHS<1,1,0b0010,0, IIC_VSHLiD, IIC_VSHLiD,
3962 "vsubl", "u", sub, zext, 0>;
3963 // VSUBW : Vector Subtract Wide (Q = Q - D)
3964 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
3965 defm VSUBWu : N3VW_QHS<1,1,0b0011,0, "vsubw", "u", sub, zext, 0>;
3966 // VHSUB : Vector Halving Subtract
3967 defm VHSUBs : N3VInt_QHS<0, 0, 0b0010, 0, N3RegFrm,
3968 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3969 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3970 defm VHSUBu : N3VInt_QHS<1, 0, 0b0010, 0, N3RegFrm,
3971 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3972 "vhsub", "u", int_arm_neon_vhsubu, 0>;
3973 // VQSUB : Vector Saturing Subtract
3974 defm VQSUBs : N3VInt_QHSD<0, 0, 0b0010, 1, N3RegFrm,
3975 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3976 "vqsub", "s", int_arm_neon_vqsubs, 0>;
3977 defm VQSUBu : N3VInt_QHSD<1, 0, 0b0010, 1, N3RegFrm,
3978 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
3979 "vqsub", "u", int_arm_neon_vqsubu, 0>;
3980 // VSUBHN : Vector Subtract and Narrow Returning High Half (D = Q - Q)
3981 defm VSUBHN : N3VNInt_HSD<0,1,0b0110,0, "vsubhn", "i",
3982 int_arm_neon_vsubhn, 0>;
3983 // VRSUBHN : Vector Rounding Subtract and Narrow Returning High Half (D=Q-Q)
3984 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
3985 int_arm_neon_vrsubhn, 0>;
3987 // Vector Comparisons.
3989 // VCEQ : Vector Compare Equal
3990 defm VCEQ : N3V_QHS<1, 0, 0b1000, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
3991 IIC_VSUBi4Q, "vceq", "i", NEONvceq, 1>;
3992 def VCEQfd : N3VD<0,0,0b00,0b1110,0, IIC_VBIND, "vceq", "f32", v2i32, v2f32,
3994 def VCEQfq : N3VQ<0,0,0b00,0b1110,0, IIC_VBINQ, "vceq", "f32", v4i32, v4f32,
3997 defm VCEQz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00010, 0, "vceq", "i",
3998 "$Vd, $Vm, #0", NEONvceqz>;
4000 // VCGE : Vector Compare Greater Than or Equal
4001 defm VCGEs : N3V_QHS<0, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4002 IIC_VSUBi4Q, "vcge", "s", NEONvcge, 0>;
4003 defm VCGEu : N3V_QHS<1, 0, 0b0011, 1, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4004 IIC_VSUBi4Q, "vcge", "u", NEONvcgeu, 0>;
4005 def VCGEfd : N3VD<1,0,0b00,0b1110,0, IIC_VBIND, "vcge", "f32", v2i32, v2f32,
4007 def VCGEfq : N3VQ<1,0,0b00,0b1110,0, IIC_VBINQ, "vcge", "f32", v4i32, v4f32,
4010 defm VCGEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00001, 0, "vcge", "s",
4011 "$Vd, $Vm, #0", NEONvcgez>;
4012 defm VCLEz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00011, 0, "vcle", "s",
4013 "$Vd, $Vm, #0", NEONvclez>;
4015 // VCGT : Vector Compare Greater Than
4016 defm VCGTs : N3V_QHS<0, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4017 IIC_VSUBi4Q, "vcgt", "s", NEONvcgt, 0>;
4018 defm VCGTu : N3V_QHS<1, 0, 0b0011, 0, IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q,
4019 IIC_VSUBi4Q, "vcgt", "u", NEONvcgtu, 0>;
4020 def VCGTfd : N3VD<1,0,0b10,0b1110,0, IIC_VBIND, "vcgt", "f32", v2i32, v2f32,
4022 def VCGTfq : N3VQ<1,0,0b10,0b1110,0, IIC_VBINQ, "vcgt", "f32", v4i32, v4f32,
4025 defm VCGTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00000, 0, "vcgt", "s",
4026 "$Vd, $Vm, #0", NEONvcgtz>;
4027 defm VCLTz : N2V_QHS_cmp<0b11, 0b11, 0b01, 0b00100, 0, "vclt", "s",
4028 "$Vd, $Vm, #0", NEONvcltz>;
4030 // VACGE : Vector Absolute Compare Greater Than or Equal (aka VCAGE)
4031 def VACGEd : N3VDInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacge",
4032 "f32", v2i32, v2f32, int_arm_neon_vacged, 0>;
4033 def VACGEq : N3VQInt<1, 0, 0b00, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacge",
4034 "f32", v4i32, v4f32, int_arm_neon_vacgeq, 0>;
4035 // VACGT : Vector Absolute Compare Greater Than (aka VCAGT)
4036 def VACGTd : N3VDInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBIND, "vacgt",
4037 "f32", v2i32, v2f32, int_arm_neon_vacgtd, 0>;
4038 def VACGTq : N3VQInt<1, 0, 0b10, 0b1110, 1, N3RegFrm, IIC_VBINQ, "vacgt",
4039 "f32", v4i32, v4f32, int_arm_neon_vacgtq, 0>;
4040 // VTST : Vector Test Bits
4041 defm VTST : N3V_QHS<0, 0, 0b1000, 1, IIC_VBINi4D, IIC_VBINi4D, IIC_VBINi4Q,
4042 IIC_VBINi4Q, "vtst", "", NEONvtst, 1>;
4044 // Vector Bitwise Operations.
4046 def vnotd : PatFrag<(ops node:$in),
4047 (xor node:$in, (bitconvert (v8i8 NEONimmAllOnesV)))>;
4048 def vnotq : PatFrag<(ops node:$in),
4049 (xor node:$in, (bitconvert (v16i8 NEONimmAllOnesV)))>;
4052 // VAND : Vector Bitwise AND
4053 def VANDd : N3VDX<0, 0, 0b00, 0b0001, 1, IIC_VBINiD, "vand",
4054 v2i32, v2i32, and, 1>;
4055 def VANDq : N3VQX<0, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "vand",
4056 v4i32, v4i32, and, 1>;
4058 // VEOR : Vector Bitwise Exclusive OR
4059 def VEORd : N3VDX<1, 0, 0b00, 0b0001, 1, IIC_VBINiD, "veor",
4060 v2i32, v2i32, xor, 1>;
4061 def VEORq : N3VQX<1, 0, 0b00, 0b0001, 1, IIC_VBINiQ, "veor",
4062 v4i32, v4i32, xor, 1>;
4064 // VORR : Vector Bitwise OR
4065 def VORRd : N3VDX<0, 0, 0b10, 0b0001, 1, IIC_VBINiD, "vorr",
4066 v2i32, v2i32, or, 1>;
4067 def VORRq : N3VQX<0, 0, 0b10, 0b0001, 1, IIC_VBINiQ, "vorr",
4068 v4i32, v4i32, or, 1>;
4070 def VORRiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 0, 1,
4071 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4073 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4075 (v4i16 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4076 let Inst{9} = SIMM{9};
4079 def VORRiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 0, 1,
4080 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4082 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4084 (v2i32 (NEONvorrImm DPR:$src, timm:$SIMM)))]> {
4085 let Inst{10-9} = SIMM{10-9};
4088 def VORRiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 0, 1,
4089 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4091 "vorr", "i16", "$Vd, $SIMM", "$src = $Vd",
4093 (v8i16 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4094 let Inst{9} = SIMM{9};
4097 def VORRiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 0, 1,
4098 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4100 "vorr", "i32", "$Vd, $SIMM", "$src = $Vd",
4102 (v4i32 (NEONvorrImm QPR:$src, timm:$SIMM)))]> {
4103 let Inst{10-9} = SIMM{10-9};
4107 // VBIC : Vector Bitwise Bit Clear (AND NOT)
4108 def VBICd : N3VX<0, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4109 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4110 "vbic", "$Vd, $Vn, $Vm", "",
4111 [(set DPR:$Vd, (v2i32 (and DPR:$Vn,
4112 (vnotd DPR:$Vm))))]>;
4113 def VBICq : N3VX<0, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4114 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4115 "vbic", "$Vd, $Vn, $Vm", "",
4116 [(set QPR:$Vd, (v4i32 (and QPR:$Vn,
4117 (vnotq QPR:$Vm))))]>;
4119 def VBICiv4i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 0, 1, 1,
4120 (outs DPR:$Vd), (ins nImmSplatI16:$SIMM, DPR:$src),
4122 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4124 (v4i16 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4125 let Inst{9} = SIMM{9};
4128 def VBICiv2i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 0, 1, 1,
4129 (outs DPR:$Vd), (ins nImmSplatI32:$SIMM, DPR:$src),
4131 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4133 (v2i32 (NEONvbicImm DPR:$src, timm:$SIMM)))]> {
4134 let Inst{10-9} = SIMM{10-9};
4137 def VBICiv8i16 : N1ModImm<1, 0b000, {1,0,?,1}, 0, 1, 1, 1,
4138 (outs QPR:$Vd), (ins nImmSplatI16:$SIMM, QPR:$src),
4140 "vbic", "i16", "$Vd, $SIMM", "$src = $Vd",
4142 (v8i16 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4143 let Inst{9} = SIMM{9};
4146 def VBICiv4i32 : N1ModImm<1, 0b000, {0,?,?,1}, 0, 1, 1, 1,
4147 (outs QPR:$Vd), (ins nImmSplatI32:$SIMM, QPR:$src),
4149 "vbic", "i32", "$Vd, $SIMM", "$src = $Vd",
4151 (v4i32 (NEONvbicImm QPR:$src, timm:$SIMM)))]> {
4152 let Inst{10-9} = SIMM{10-9};
4155 // VORN : Vector Bitwise OR NOT
4156 def VORNd : N3VX<0, 0, 0b11, 0b0001, 0, 1, (outs DPR:$Vd),
4157 (ins DPR:$Vn, DPR:$Vm), N3RegFrm, IIC_VBINiD,
4158 "vorn", "$Vd, $Vn, $Vm", "",
4159 [(set DPR:$Vd, (v2i32 (or DPR:$Vn,
4160 (vnotd DPR:$Vm))))]>;
4161 def VORNq : N3VX<0, 0, 0b11, 0b0001, 1, 1, (outs QPR:$Vd),
4162 (ins QPR:$Vn, QPR:$Vm), N3RegFrm, IIC_VBINiQ,
4163 "vorn", "$Vd, $Vn, $Vm", "",
4164 [(set QPR:$Vd, (v4i32 (or QPR:$Vn,
4165 (vnotq QPR:$Vm))))]>;
4167 // VMVN : Vector Bitwise NOT (Immediate)
4169 let isReMaterializable = 1 in {
4171 def VMVNv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 1, 1, (outs DPR:$Vd),
4172 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4173 "vmvn", "i16", "$Vd, $SIMM", "",
4174 [(set DPR:$Vd, (v4i16 (NEONvmvnImm timm:$SIMM)))]> {
4175 let Inst{9} = SIMM{9};
4178 def VMVNv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 1, 1, (outs QPR:$Vd),
4179 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4180 "vmvn", "i16", "$Vd, $SIMM", "",
4181 [(set QPR:$Vd, (v8i16 (NEONvmvnImm timm:$SIMM)))]> {
4182 let Inst{9} = SIMM{9};
4185 def VMVNv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 1, 1, (outs DPR:$Vd),
4186 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4187 "vmvn", "i32", "$Vd, $SIMM", "",
4188 [(set DPR:$Vd, (v2i32 (NEONvmvnImm timm:$SIMM)))]> {
4189 let Inst{11-8} = SIMM{11-8};
4192 def VMVNv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 1, 1, (outs QPR:$Vd),
4193 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4194 "vmvn", "i32", "$Vd, $SIMM", "",
4195 [(set QPR:$Vd, (v4i32 (NEONvmvnImm timm:$SIMM)))]> {
4196 let Inst{11-8} = SIMM{11-8};
4200 // VMVN : Vector Bitwise NOT
4201 def VMVNd : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 0, 0,
4202 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VSUBiD,
4203 "vmvn", "$Vd, $Vm", "",
4204 [(set DPR:$Vd, (v2i32 (vnotd DPR:$Vm)))]>;
4205 def VMVNq : N2VX<0b11, 0b11, 0b00, 0b00, 0b01011, 1, 0,
4206 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VSUBiD,
4207 "vmvn", "$Vd, $Vm", "",
4208 [(set QPR:$Vd, (v4i32 (vnotq QPR:$Vm)))]>;
4209 def : Pat<(v2i32 (vnotd DPR:$src)), (VMVNd DPR:$src)>;
4210 def : Pat<(v4i32 (vnotq QPR:$src)), (VMVNq QPR:$src)>;
4212 // VBSL : Vector Bitwise Select
4213 def VBSLd : N3VX<1, 0, 0b01, 0b0001, 0, 1, (outs DPR:$Vd),
4214 (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4215 N3RegFrm, IIC_VCNTiD,
4216 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4218 (v2i32 (NEONvbsl DPR:$src1, DPR:$Vn, DPR:$Vm)))]>;
4220 def : Pat<(v2i32 (or (and DPR:$Vn, DPR:$Vd),
4221 (and DPR:$Vm, (vnotd DPR:$Vd)))),
4222 (VBSLd DPR:$Vd, DPR:$Vn, DPR:$Vm)>;
4224 def VBSLq : N3VX<1, 0, 0b01, 0b0001, 1, 1, (outs QPR:$Vd),
4225 (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4226 N3RegFrm, IIC_VCNTiQ,
4227 "vbsl", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4229 (v4i32 (NEONvbsl QPR:$src1, QPR:$Vn, QPR:$Vm)))]>;
4231 def : Pat<(v4i32 (or (and QPR:$Vn, QPR:$Vd),
4232 (and QPR:$Vm, (vnotq QPR:$Vd)))),
4233 (VBSLq QPR:$Vd, QPR:$Vn, QPR:$Vm)>;
4235 // VBIF : Vector Bitwise Insert if False
4236 // like VBSL but with: "vbif $dst, $src3, $src1", "$src2 = $dst",
4237 // FIXME: This instruction's encoding MAY NOT BE correct.
4238 def VBIFd : N3VX<1, 0, 0b11, 0b0001, 0, 1,
4239 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4240 N3RegFrm, IIC_VBINiD,
4241 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4243 def VBIFq : N3VX<1, 0, 0b11, 0b0001, 1, 1,
4244 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4245 N3RegFrm, IIC_VBINiQ,
4246 "vbif", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4249 // VBIT : Vector Bitwise Insert if True
4250 // like VBSL but with: "vbit $dst, $src2, $src1", "$src3 = $dst",
4251 // FIXME: This instruction's encoding MAY NOT BE correct.
4252 def VBITd : N3VX<1, 0, 0b10, 0b0001, 0, 1,
4253 (outs DPR:$Vd), (ins DPR:$src1, DPR:$Vn, DPR:$Vm),
4254 N3RegFrm, IIC_VBINiD,
4255 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4257 def VBITq : N3VX<1, 0, 0b10, 0b0001, 1, 1,
4258 (outs QPR:$Vd), (ins QPR:$src1, QPR:$Vn, QPR:$Vm),
4259 N3RegFrm, IIC_VBINiQ,
4260 "vbit", "$Vd, $Vn, $Vm", "$src1 = $Vd",
4263 // VBIT/VBIF are not yet implemented. The TwoAddress pass will not go looking
4264 // for equivalent operations with different register constraints; it just
4267 // Vector Absolute Differences.
4269 // VABD : Vector Absolute Difference
4270 defm VABDs : N3VInt_QHS<0, 0, 0b0111, 0, N3RegFrm,
4271 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4272 "vabd", "s", int_arm_neon_vabds, 1>;
4273 defm VABDu : N3VInt_QHS<1, 0, 0b0111, 0, N3RegFrm,
4274 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4275 "vabd", "u", int_arm_neon_vabdu, 1>;
4276 def VABDfd : N3VDInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBIND,
4277 "vabd", "f32", v2f32, v2f32, int_arm_neon_vabds, 1>;
4278 def VABDfq : N3VQInt<1, 0, 0b10, 0b1101, 0, N3RegFrm, IIC_VBINQ,
4279 "vabd", "f32", v4f32, v4f32, int_arm_neon_vabds, 1>;
4281 // VABDL : Vector Absolute Difference Long (Q = | D - D |)
4282 defm VABDLs : N3VLIntExt_QHS<0,1,0b0111,0, IIC_VSUBi4Q,
4283 "vabdl", "s", int_arm_neon_vabds, zext, 1>;
4284 defm VABDLu : N3VLIntExt_QHS<1,1,0b0111,0, IIC_VSUBi4Q,
4285 "vabdl", "u", int_arm_neon_vabdu, zext, 1>;
4287 // VABA : Vector Absolute Difference and Accumulate
4288 defm VABAs : N3VIntOp_QHS<0,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4289 "vaba", "s", int_arm_neon_vabds, add>;
4290 defm VABAu : N3VIntOp_QHS<1,0,0b0111,1, IIC_VABAD, IIC_VABAQ,
4291 "vaba", "u", int_arm_neon_vabdu, add>;
4293 // VABAL : Vector Absolute Difference and Accumulate Long (Q += | D - D |)
4294 defm VABALs : N3VLIntExtOp_QHS<0,1,0b0101,0, IIC_VABAD,
4295 "vabal", "s", int_arm_neon_vabds, zext, add>;
4296 defm VABALu : N3VLIntExtOp_QHS<1,1,0b0101,0, IIC_VABAD,
4297 "vabal", "u", int_arm_neon_vabdu, zext, add>;
4299 // Vector Maximum and Minimum.
4301 // VMAX : Vector Maximum
4302 defm VMAXs : N3VInt_QHS<0, 0, 0b0110, 0, N3RegFrm,
4303 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4304 "vmax", "s", int_arm_neon_vmaxs, 1>;
4305 defm VMAXu : N3VInt_QHS<1, 0, 0b0110, 0, N3RegFrm,
4306 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4307 "vmax", "u", int_arm_neon_vmaxu, 1>;
4308 def VMAXfd : N3VDInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBIND,
4310 v2f32, v2f32, int_arm_neon_vmaxs, 1>;
4311 def VMAXfq : N3VQInt<0, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4313 v4f32, v4f32, int_arm_neon_vmaxs, 1>;
4315 // VMIN : Vector Minimum
4316 defm VMINs : N3VInt_QHS<0, 0, 0b0110, 1, N3RegFrm,
4317 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4318 "vmin", "s", int_arm_neon_vmins, 1>;
4319 defm VMINu : N3VInt_QHS<1, 0, 0b0110, 1, N3RegFrm,
4320 IIC_VSUBi4D, IIC_VSUBi4D, IIC_VSUBi4Q, IIC_VSUBi4Q,
4321 "vmin", "u", int_arm_neon_vminu, 1>;
4322 def VMINfd : N3VDInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBIND,
4324 v2f32, v2f32, int_arm_neon_vmins, 1>;
4325 def VMINfq : N3VQInt<0, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VBINQ,
4327 v4f32, v4f32, int_arm_neon_vmins, 1>;
4329 // Vector Pairwise Operations.
4331 // VPADD : Vector Pairwise Add
4332 def VPADDi8 : N3VDInt<0, 0, 0b00, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4334 v8i8, v8i8, int_arm_neon_vpadd, 0>;
4335 def VPADDi16 : N3VDInt<0, 0, 0b01, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4337 v4i16, v4i16, int_arm_neon_vpadd, 0>;
4338 def VPADDi32 : N3VDInt<0, 0, 0b10, 0b1011, 1, N3RegFrm, IIC_VSHLiD,
4340 v2i32, v2i32, int_arm_neon_vpadd, 0>;
4341 def VPADDf : N3VDInt<1, 0, 0b00, 0b1101, 0, N3RegFrm,
4342 IIC_VPBIND, "vpadd", "f32",
4343 v2f32, v2f32, int_arm_neon_vpadd, 0>;
4345 // VPADDL : Vector Pairwise Add Long
4346 defm VPADDLs : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00100, 0, "vpaddl", "s",
4347 int_arm_neon_vpaddls>;
4348 defm VPADDLu : N2VPLInt_QHS<0b11, 0b11, 0b00, 0b00101, 0, "vpaddl", "u",
4349 int_arm_neon_vpaddlu>;
4351 // VPADAL : Vector Pairwise Add and Accumulate Long
4352 defm VPADALs : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01100, 0, "vpadal", "s",
4353 int_arm_neon_vpadals>;
4354 defm VPADALu : N2VPLInt2_QHS<0b11, 0b11, 0b00, 0b01101, 0, "vpadal", "u",
4355 int_arm_neon_vpadalu>;
4357 // VPMAX : Vector Pairwise Maximum
4358 def VPMAXs8 : N3VDInt<0, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4359 "s8", v8i8, v8i8, int_arm_neon_vpmaxs, 0>;
4360 def VPMAXs16 : N3VDInt<0, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4361 "s16", v4i16, v4i16, int_arm_neon_vpmaxs, 0>;
4362 def VPMAXs32 : N3VDInt<0, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4363 "s32", v2i32, v2i32, int_arm_neon_vpmaxs, 0>;
4364 def VPMAXu8 : N3VDInt<1, 0, 0b00, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4365 "u8", v8i8, v8i8, int_arm_neon_vpmaxu, 0>;
4366 def VPMAXu16 : N3VDInt<1, 0, 0b01, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4367 "u16", v4i16, v4i16, int_arm_neon_vpmaxu, 0>;
4368 def VPMAXu32 : N3VDInt<1, 0, 0b10, 0b1010, 0, N3RegFrm, IIC_VSUBi4D, "vpmax",
4369 "u32", v2i32, v2i32, int_arm_neon_vpmaxu, 0>;
4370 def VPMAXf : N3VDInt<1, 0, 0b00, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmax",
4371 "f32", v2f32, v2f32, int_arm_neon_vpmaxs, 0>;
4373 // VPMIN : Vector Pairwise Minimum
4374 def VPMINs8 : N3VDInt<0, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4375 "s8", v8i8, v8i8, int_arm_neon_vpmins, 0>;
4376 def VPMINs16 : N3VDInt<0, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4377 "s16", v4i16, v4i16, int_arm_neon_vpmins, 0>;
4378 def VPMINs32 : N3VDInt<0, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4379 "s32", v2i32, v2i32, int_arm_neon_vpmins, 0>;
4380 def VPMINu8 : N3VDInt<1, 0, 0b00, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4381 "u8", v8i8, v8i8, int_arm_neon_vpminu, 0>;
4382 def VPMINu16 : N3VDInt<1, 0, 0b01, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4383 "u16", v4i16, v4i16, int_arm_neon_vpminu, 0>;
4384 def VPMINu32 : N3VDInt<1, 0, 0b10, 0b1010, 1, N3RegFrm, IIC_VSUBi4D, "vpmin",
4385 "u32", v2i32, v2i32, int_arm_neon_vpminu, 0>;
4386 def VPMINf : N3VDInt<1, 0, 0b10, 0b1111, 0, N3RegFrm, IIC_VPBIND, "vpmin",
4387 "f32", v2f32, v2f32, int_arm_neon_vpmins, 0>;
4389 // Vector Reciprocal and Reciprocal Square Root Estimate and Step.
4391 // VRECPE : Vector Reciprocal Estimate
4392 def VRECPEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4393 IIC_VUNAD, "vrecpe", "u32",
4394 v2i32, v2i32, int_arm_neon_vrecpe>;
4395 def VRECPEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01000, 0,
4396 IIC_VUNAQ, "vrecpe", "u32",
4397 v4i32, v4i32, int_arm_neon_vrecpe>;
4398 def VRECPEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4399 IIC_VUNAD, "vrecpe", "f32",
4400 v2f32, v2f32, int_arm_neon_vrecpe>;
4401 def VRECPEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01010, 0,
4402 IIC_VUNAQ, "vrecpe", "f32",
4403 v4f32, v4f32, int_arm_neon_vrecpe>;
4405 // VRECPS : Vector Reciprocal Step
4406 def VRECPSfd : N3VDInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4407 IIC_VRECSD, "vrecps", "f32",
4408 v2f32, v2f32, int_arm_neon_vrecps, 1>;
4409 def VRECPSfq : N3VQInt<0, 0, 0b00, 0b1111, 1, N3RegFrm,
4410 IIC_VRECSQ, "vrecps", "f32",
4411 v4f32, v4f32, int_arm_neon_vrecps, 1>;
4413 // VRSQRTE : Vector Reciprocal Square Root Estimate
4414 def VRSQRTEd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4415 IIC_VUNAD, "vrsqrte", "u32",
4416 v2i32, v2i32, int_arm_neon_vrsqrte>;
4417 def VRSQRTEq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01001, 0,
4418 IIC_VUNAQ, "vrsqrte", "u32",
4419 v4i32, v4i32, int_arm_neon_vrsqrte>;
4420 def VRSQRTEfd : N2VDInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4421 IIC_VUNAD, "vrsqrte", "f32",
4422 v2f32, v2f32, int_arm_neon_vrsqrte>;
4423 def VRSQRTEfq : N2VQInt<0b11, 0b11, 0b10, 0b11, 0b01011, 0,
4424 IIC_VUNAQ, "vrsqrte", "f32",
4425 v4f32, v4f32, int_arm_neon_vrsqrte>;
4427 // VRSQRTS : Vector Reciprocal Square Root Step
4428 def VRSQRTSfd : N3VDInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4429 IIC_VRECSD, "vrsqrts", "f32",
4430 v2f32, v2f32, int_arm_neon_vrsqrts, 1>;
4431 def VRSQRTSfq : N3VQInt<0, 0, 0b10, 0b1111, 1, N3RegFrm,
4432 IIC_VRECSQ, "vrsqrts", "f32",
4433 v4f32, v4f32, int_arm_neon_vrsqrts, 1>;
4437 // VSHL : Vector Shift
4438 defm VSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 0, N3RegVShFrm,
4439 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4440 "vshl", "s", int_arm_neon_vshifts>;
4441 defm VSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 0, N3RegVShFrm,
4442 IIC_VSHLiD, IIC_VSHLiD, IIC_VSHLiQ, IIC_VSHLiQ,
4443 "vshl", "u", int_arm_neon_vshiftu>;
4445 // VSHL : Vector Shift Left (Immediate)
4446 defm VSHLi : N2VShL_QHSD<0, 1, 0b0101, 1, IIC_VSHLiD, "vshl", "i", NEONvshl>;
4448 // VSHR : Vector Shift Right (Immediate)
4449 defm VSHRs : N2VShR_QHSD<0, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "s",NEONvshrs>;
4450 defm VSHRu : N2VShR_QHSD<1, 1, 0b0000, 1, IIC_VSHLiD, "vshr", "u",NEONvshru>;
4452 // VSHLL : Vector Shift Left Long
4453 defm VSHLLs : N2VLSh_QHS<0, 1, 0b1010, 0, 0, 1, "vshll", "s", NEONvshlls>;
4454 defm VSHLLu : N2VLSh_QHS<1, 1, 0b1010, 0, 0, 1, "vshll", "u", NEONvshllu>;
4456 // VSHLL : Vector Shift Left Long (with maximum shift count)
4457 class N2VLShMax<bit op24, bit op23, bits<6> op21_16, bits<4> op11_8, bit op7,
4458 bit op6, bit op4, string OpcodeStr, string Dt, ValueType ResTy,
4459 ValueType OpTy, Operand ImmTy, SDNode OpNode>
4460 : N2VLSh<op24, op23, op11_8, op7, op6, op4, OpcodeStr, Dt,
4461 ResTy, OpTy, ImmTy, OpNode> {
4462 let Inst{21-16} = op21_16;
4463 let DecoderMethod = "DecodeVSHLMaxInstruction";
4465 def VSHLLi8 : N2VLShMax<1, 1, 0b110010, 0b0011, 0, 0, 0, "vshll", "i8",
4466 v8i16, v8i8, imm8, NEONvshlli>;
4467 def VSHLLi16 : N2VLShMax<1, 1, 0b110110, 0b0011, 0, 0, 0, "vshll", "i16",
4468 v4i32, v4i16, imm16, NEONvshlli>;
4469 def VSHLLi32 : N2VLShMax<1, 1, 0b111010, 0b0011, 0, 0, 0, "vshll", "i32",
4470 v2i64, v2i32, imm32, NEONvshlli>;
4472 // VSHRN : Vector Shift Right and Narrow
4473 defm VSHRN : N2VNSh_HSD<0,1,0b1000,0,0,1, IIC_VSHLiD, "vshrn", "i",
4476 // VRSHL : Vector Rounding Shift
4477 defm VRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 0, N3RegVShFrm,
4478 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4479 "vrshl", "s", int_arm_neon_vrshifts>;
4480 defm VRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 0, N3RegVShFrm,
4481 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4482 "vrshl", "u", int_arm_neon_vrshiftu>;
4483 // VRSHR : Vector Rounding Shift Right
4484 defm VRSHRs : N2VShR_QHSD<0,1,0b0010,1, IIC_VSHLi4D, "vrshr", "s",NEONvrshrs>;
4485 defm VRSHRu : N2VShR_QHSD<1,1,0b0010,1, IIC_VSHLi4D, "vrshr", "u",NEONvrshru>;
4487 // VRSHRN : Vector Rounding Shift Right and Narrow
4488 defm VRSHRN : N2VNSh_HSD<0, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vrshrn", "i",
4491 // VQSHL : Vector Saturating Shift
4492 defm VQSHLs : N3VInt_QHSDSh<0, 0, 0b0100, 1, N3RegVShFrm,
4493 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4494 "vqshl", "s", int_arm_neon_vqshifts>;
4495 defm VQSHLu : N3VInt_QHSDSh<1, 0, 0b0100, 1, N3RegVShFrm,
4496 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4497 "vqshl", "u", int_arm_neon_vqshiftu>;
4498 // VQSHL : Vector Saturating Shift Left (Immediate)
4499 defm VQSHLsi : N2VShL_QHSD<0,1,0b0111,1, IIC_VSHLi4D, "vqshl", "s",NEONvqshls>;
4500 defm VQSHLui : N2VShL_QHSD<1,1,0b0111,1, IIC_VSHLi4D, "vqshl", "u",NEONvqshlu>;
4502 // VQSHLU : Vector Saturating Shift Left (Immediate, Unsigned)
4503 defm VQSHLsu : N2VShL_QHSD<1,1,0b0110,1, IIC_VSHLi4D,"vqshlu","s",NEONvqshlsu>;
4505 // VQSHRN : Vector Saturating Shift Right and Narrow
4506 defm VQSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "s",
4508 defm VQSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 0, 1, IIC_VSHLi4D, "vqshrn", "u",
4511 // VQSHRUN : Vector Saturating Shift Right and Narrow (Unsigned)
4512 defm VQSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 0, 1, IIC_VSHLi4D, "vqshrun", "s",
4515 // VQRSHL : Vector Saturating Rounding Shift
4516 defm VQRSHLs : N3VInt_QHSDSh<0, 0, 0b0101, 1, N3RegVShFrm,
4517 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4518 "vqrshl", "s", int_arm_neon_vqrshifts>;
4519 defm VQRSHLu : N3VInt_QHSDSh<1, 0, 0b0101, 1, N3RegVShFrm,
4520 IIC_VSHLi4D, IIC_VSHLi4D, IIC_VSHLi4Q, IIC_VSHLi4Q,
4521 "vqrshl", "u", int_arm_neon_vqrshiftu>;
4523 // VQRSHRN : Vector Saturating Rounding Shift Right and Narrow
4524 defm VQRSHRNs : N2VNSh_HSD<0, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "s",
4526 defm VQRSHRNu : N2VNSh_HSD<1, 1, 0b1001, 0, 1, 1, IIC_VSHLi4D, "vqrshrn", "u",
4529 // VQRSHRUN : Vector Saturating Rounding Shift Right and Narrow (Unsigned)
4530 defm VQRSHRUN : N2VNSh_HSD<1, 1, 0b1000, 0, 1, 1, IIC_VSHLi4D, "vqrshrun", "s",
4533 // VSRA : Vector Shift Right and Accumulate
4534 defm VSRAs : N2VShAdd_QHSD<0, 1, 0b0001, 1, "vsra", "s", NEONvshrs>;
4535 defm VSRAu : N2VShAdd_QHSD<1, 1, 0b0001, 1, "vsra", "u", NEONvshru>;
4536 // VRSRA : Vector Rounding Shift Right and Accumulate
4537 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4538 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;
4540 // VSLI : Vector Shift Left and Insert
4541 defm VSLI : N2VShInsL_QHSD<1, 1, 0b0101, 1, "vsli">;
4543 // VSRI : Vector Shift Right and Insert
4544 defm VSRI : N2VShInsR_QHSD<1, 1, 0b0100, 1, "vsri">;
4546 // Vector Absolute and Saturating Absolute.
4548 // VABS : Vector Absolute Value
4549 defm VABS : N2VInt_QHS<0b11, 0b11, 0b01, 0b00110, 0,
4550 IIC_VUNAiD, IIC_VUNAiQ, "vabs", "s",
4552 def VABSfd : N2VDInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4553 IIC_VUNAD, "vabs", "f32",
4554 v2f32, v2f32, int_arm_neon_vabs>;
4555 def VABSfq : N2VQInt<0b11, 0b11, 0b10, 0b01, 0b01110, 0,
4556 IIC_VUNAQ, "vabs", "f32",
4557 v4f32, v4f32, int_arm_neon_vabs>;
4559 // VQABS : Vector Saturating Absolute Value
4560 defm VQABS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01110, 0,
4561 IIC_VQUNAiD, IIC_VQUNAiQ, "vqabs", "s",
4562 int_arm_neon_vqabs>;
4566 def vnegd : PatFrag<(ops node:$in),
4567 (sub (bitconvert (v2i32 NEONimmAllZerosV)), node:$in)>;
4568 def vnegq : PatFrag<(ops node:$in),
4569 (sub (bitconvert (v4i32 NEONimmAllZerosV)), node:$in)>;
4571 class VNEGD<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4572 : N2V<0b11, 0b11, size, 0b01, 0b00111, 0, 0, (outs DPR:$Vd), (ins DPR:$Vm),
4573 IIC_VSHLiD, OpcodeStr, Dt, "$Vd, $Vm", "",
4574 [(set DPR:$Vd, (Ty (vnegd DPR:$Vm)))]>;
4575 class VNEGQ<bits<2> size, string OpcodeStr, string Dt, ValueType Ty>
4576 : N2V<0b11, 0b11, size, 0b01, 0b00111, 1, 0, (outs QPR:$Vd), (ins QPR:$Vm),
4577 IIC_VSHLiQ, OpcodeStr, Dt, "$Vd, $Vm", "",
4578 [(set QPR:$Vd, (Ty (vnegq QPR:$Vm)))]>;
4580 // VNEG : Vector Negate (integer)
4581 def VNEGs8d : VNEGD<0b00, "vneg", "s8", v8i8>;
4582 def VNEGs16d : VNEGD<0b01, "vneg", "s16", v4i16>;
4583 def VNEGs32d : VNEGD<0b10, "vneg", "s32", v2i32>;
4584 def VNEGs8q : VNEGQ<0b00, "vneg", "s8", v16i8>;
4585 def VNEGs16q : VNEGQ<0b01, "vneg", "s16", v8i16>;
4586 def VNEGs32q : VNEGQ<0b10, "vneg", "s32", v4i32>;
4588 // VNEG : Vector Negate (floating-point)
4589 def VNEGfd : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 0, 0,
4590 (outs DPR:$Vd), (ins DPR:$Vm), IIC_VUNAD,
4591 "vneg", "f32", "$Vd, $Vm", "",
4592 [(set DPR:$Vd, (v2f32 (fneg DPR:$Vm)))]>;
4593 def VNEGf32q : N2V<0b11, 0b11, 0b10, 0b01, 0b01111, 1, 0,
4594 (outs QPR:$Vd), (ins QPR:$Vm), IIC_VUNAQ,
4595 "vneg", "f32", "$Vd, $Vm", "",
4596 [(set QPR:$Vd, (v4f32 (fneg QPR:$Vm)))]>;
4598 def : Pat<(v8i8 (vnegd DPR:$src)), (VNEGs8d DPR:$src)>;
4599 def : Pat<(v4i16 (vnegd DPR:$src)), (VNEGs16d DPR:$src)>;
4600 def : Pat<(v2i32 (vnegd DPR:$src)), (VNEGs32d DPR:$src)>;
4601 def : Pat<(v16i8 (vnegq QPR:$src)), (VNEGs8q QPR:$src)>;
4602 def : Pat<(v8i16 (vnegq QPR:$src)), (VNEGs16q QPR:$src)>;
4603 def : Pat<(v4i32 (vnegq QPR:$src)), (VNEGs32q QPR:$src)>;
4605 // VQNEG : Vector Saturating Negate
4606 defm VQNEG : N2VInt_QHS<0b11, 0b11, 0b00, 0b01111, 0,
4607 IIC_VQUNAiD, IIC_VQUNAiQ, "vqneg", "s",
4608 int_arm_neon_vqneg>;
4610 // Vector Bit Counting Operations.
4612 // VCLS : Vector Count Leading Sign Bits
4613 defm VCLS : N2VInt_QHS<0b11, 0b11, 0b00, 0b01000, 0,
4614 IIC_VCNTiD, IIC_VCNTiQ, "vcls", "s",
4616 // VCLZ : Vector Count Leading Zeros
4617 defm VCLZ : N2VInt_QHS<0b11, 0b11, 0b00, 0b01001, 0,
4618 IIC_VCNTiD, IIC_VCNTiQ, "vclz", "i",
4620 // VCNT : Vector Count One Bits
4621 def VCNTd : N2VDInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4622 IIC_VCNTiD, "vcnt", "8",
4623 v8i8, v8i8, int_arm_neon_vcnt>;
4624 def VCNTq : N2VQInt<0b11, 0b11, 0b00, 0b00, 0b01010, 0,
4625 IIC_VCNTiQ, "vcnt", "8",
4626 v16i8, v16i8, int_arm_neon_vcnt>;
4629 def VSWPd : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 0, 0,
4630 (outs DPR:$Vd), (ins DPR:$Vm), NoItinerary,
4631 "vswp", "$Vd, $Vm", "", []>;
4632 def VSWPq : N2VX<0b11, 0b11, 0b00, 0b10, 0b00000, 1, 0,
4633 (outs QPR:$Vd), (ins QPR:$Vm), NoItinerary,
4634 "vswp", "$Vd, $Vm", "", []>;
4636 // Vector Move Operations.
4638 // VMOV : Vector Move (Register)
4639 def : InstAlias<"vmov${p} $Vd, $Vm",
4640 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
4641 def : InstAlias<"vmov${p} $Vd, $Vm",
4642 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
4644 // VMOV : Vector Move (Immediate)
4646 let isReMaterializable = 1 in {
4647 def VMOVv8i8 : N1ModImm<1, 0b000, 0b1110, 0, 0, 0, 1, (outs DPR:$Vd),
4648 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4649 "vmov", "i8", "$Vd, $SIMM", "",
4650 [(set DPR:$Vd, (v8i8 (NEONvmovImm timm:$SIMM)))]>;
4651 def VMOVv16i8 : N1ModImm<1, 0b000, 0b1110, 0, 1, 0, 1, (outs QPR:$Vd),
4652 (ins nImmSplatI8:$SIMM), IIC_VMOVImm,
4653 "vmov", "i8", "$Vd, $SIMM", "",
4654 [(set QPR:$Vd, (v16i8 (NEONvmovImm timm:$SIMM)))]>;
4656 def VMOVv4i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 0, 0, 1, (outs DPR:$Vd),
4657 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4658 "vmov", "i16", "$Vd, $SIMM", "",
4659 [(set DPR:$Vd, (v4i16 (NEONvmovImm timm:$SIMM)))]> {
4660 let Inst{9} = SIMM{9};
4663 def VMOVv8i16 : N1ModImm<1, 0b000, {1,0,?,0}, 0, 1, 0, 1, (outs QPR:$Vd),
4664 (ins nImmSplatI16:$SIMM), IIC_VMOVImm,
4665 "vmov", "i16", "$Vd, $SIMM", "",
4666 [(set QPR:$Vd, (v8i16 (NEONvmovImm timm:$SIMM)))]> {
4667 let Inst{9} = SIMM{9};
4670 def VMOVv2i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 0, 0, 1, (outs DPR:$Vd),
4671 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4672 "vmov", "i32", "$Vd, $SIMM", "",
4673 [(set DPR:$Vd, (v2i32 (NEONvmovImm timm:$SIMM)))]> {
4674 let Inst{11-8} = SIMM{11-8};
4677 def VMOVv4i32 : N1ModImm<1, 0b000, {?,?,?,?}, 0, 1, 0, 1, (outs QPR:$Vd),
4678 (ins nImmVMOVI32:$SIMM), IIC_VMOVImm,
4679 "vmov", "i32", "$Vd, $SIMM", "",
4680 [(set QPR:$Vd, (v4i32 (NEONvmovImm timm:$SIMM)))]> {
4681 let Inst{11-8} = SIMM{11-8};
4684 def VMOVv1i64 : N1ModImm<1, 0b000, 0b1110, 0, 0, 1, 1, (outs DPR:$Vd),
4685 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4686 "vmov", "i64", "$Vd, $SIMM", "",
4687 [(set DPR:$Vd, (v1i64 (NEONvmovImm timm:$SIMM)))]>;
4688 def VMOVv2i64 : N1ModImm<1, 0b000, 0b1110, 0, 1, 1, 1, (outs QPR:$Vd),
4689 (ins nImmSplatI64:$SIMM), IIC_VMOVImm,
4690 "vmov", "i64", "$Vd, $SIMM", "",
4691 [(set QPR:$Vd, (v2i64 (NEONvmovImm timm:$SIMM)))]>;
4693 def VMOVv2f32 : N1ModImm<1, 0b000, 0b1111, 0, 0, 0, 1, (outs DPR:$Vd),
4694 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4695 "vmov", "f32", "$Vd, $SIMM", "",
4696 [(set DPR:$Vd, (v2f32 (NEONvmovFPImm timm:$SIMM)))]>;
4697 def VMOVv4f32 : N1ModImm<1, 0b000, 0b1111, 0, 1, 0, 1, (outs QPR:$Vd),
4698 (ins nImmVMOVF32:$SIMM), IIC_VMOVImm,
4699 "vmov", "f32", "$Vd, $SIMM", "",
4700 [(set QPR:$Vd, (v4f32 (NEONvmovFPImm timm:$SIMM)))]>;
4701 } // isReMaterializable
4703 // VMOV : Vector Get Lane (move scalar to ARM core register)
4705 def VGETLNs8 : NVGetLane<{1,1,1,0,0,1,?,1}, 0b1011, {?,?},
4706 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4707 IIC_VMOVSI, "vmov", "s8", "$R, $V$lane",
4708 [(set GPR:$R, (NEONvgetlanes (v8i8 DPR:$V),
4710 let Inst{21} = lane{2};
4711 let Inst{6-5} = lane{1-0};
4713 def VGETLNs16 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, {?,1},
4714 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4715 IIC_VMOVSI, "vmov", "s16", "$R, $V$lane",
4716 [(set GPR:$R, (NEONvgetlanes (v4i16 DPR:$V),
4718 let Inst{21} = lane{1};
4719 let Inst{6} = lane{0};
4721 def VGETLNu8 : NVGetLane<{1,1,1,0,1,1,?,1}, 0b1011, {?,?},
4722 (outs GPR:$R), (ins DPR:$V, VectorIndex8:$lane),
4723 IIC_VMOVSI, "vmov", "u8", "$R, $V$lane",
4724 [(set GPR:$R, (NEONvgetlaneu (v8i8 DPR:$V),
4726 let Inst{21} = lane{2};
4727 let Inst{6-5} = lane{1-0};
4729 def VGETLNu16 : NVGetLane<{1,1,1,0,1,0,?,1}, 0b1011, {?,1},
4730 (outs GPR:$R), (ins DPR:$V, VectorIndex16:$lane),
4731 IIC_VMOVSI, "vmov", "u16", "$R, $V$lane",
4732 [(set GPR:$R, (NEONvgetlaneu (v4i16 DPR:$V),
4734 let Inst{21} = lane{1};
4735 let Inst{6} = lane{0};
4737 def VGETLNi32 : NVGetLane<{1,1,1,0,0,0,?,1}, 0b1011, 0b00,
4738 (outs GPR:$R), (ins DPR:$V, VectorIndex32:$lane),
4739 IIC_VMOVSI, "vmov", "32", "$R, $V$lane",
4740 [(set GPR:$R, (extractelt (v2i32 DPR:$V),
4742 let Inst{21} = lane{0};
4744 // def VGETLNf32: see FMRDH and FMRDL in ARMInstrVFP.td
4745 def : Pat<(NEONvgetlanes (v16i8 QPR:$src), imm:$lane),
4746 (VGETLNs8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4747 (DSubReg_i8_reg imm:$lane))),
4748 (SubReg_i8_lane imm:$lane))>;
4749 def : Pat<(NEONvgetlanes (v8i16 QPR:$src), imm:$lane),
4750 (VGETLNs16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4751 (DSubReg_i16_reg imm:$lane))),
4752 (SubReg_i16_lane imm:$lane))>;
4753 def : Pat<(NEONvgetlaneu (v16i8 QPR:$src), imm:$lane),
4754 (VGETLNu8 (v8i8 (EXTRACT_SUBREG QPR:$src,
4755 (DSubReg_i8_reg imm:$lane))),
4756 (SubReg_i8_lane imm:$lane))>;
4757 def : Pat<(NEONvgetlaneu (v8i16 QPR:$src), imm:$lane),
4758 (VGETLNu16 (v4i16 (EXTRACT_SUBREG QPR:$src,
4759 (DSubReg_i16_reg imm:$lane))),
4760 (SubReg_i16_lane imm:$lane))>;
4761 def : Pat<(extractelt (v4i32 QPR:$src), imm:$lane),
4762 (VGETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src,
4763 (DSubReg_i32_reg imm:$lane))),
4764 (SubReg_i32_lane imm:$lane))>;
4765 def : Pat<(extractelt (v2f32 DPR:$src1), imm:$src2),
4766 (EXTRACT_SUBREG (v2f32 (COPY_TO_REGCLASS (v2f32 DPR:$src1),DPR_VFP2)),
4767 (SSubReg_f32_reg imm:$src2))>;
4768 def : Pat<(extractelt (v4f32 QPR:$src1), imm:$src2),
4769 (EXTRACT_SUBREG (v4f32 (COPY_TO_REGCLASS (v4f32 QPR:$src1),QPR_VFP2)),
4770 (SSubReg_f32_reg imm:$src2))>;
4771 //def : Pat<(extractelt (v2i64 QPR:$src1), imm:$src2),
4772 // (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4773 def : Pat<(extractelt (v2f64 QPR:$src1), imm:$src2),
4774 (EXTRACT_SUBREG QPR:$src1, (DSubReg_f64_reg imm:$src2))>;
4777 // VMOV : Vector Set Lane (move ARM core register to scalar)
4779 let Constraints = "$src1 = $V" in {
4780 def VSETLNi8 : NVSetLane<{1,1,1,0,0,1,?,0}, 0b1011, {?,?}, (outs DPR:$V),
4781 (ins DPR:$src1, GPR:$R, VectorIndex8:$lane),
4782 IIC_VMOVISL, "vmov", "8", "$V$lane, $R",
4783 [(set DPR:$V, (vector_insert (v8i8 DPR:$src1),
4784 GPR:$R, imm:$lane))]> {
4785 let Inst{21} = lane{2};
4786 let Inst{6-5} = lane{1-0};
4788 def VSETLNi16 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, {?,1}, (outs DPR:$V),
4789 (ins DPR:$src1, GPR:$R, VectorIndex16:$lane),
4790 IIC_VMOVISL, "vmov", "16", "$V$lane, $R",
4791 [(set DPR:$V, (vector_insert (v4i16 DPR:$src1),
4792 GPR:$R, imm:$lane))]> {
4793 let Inst{21} = lane{1};
4794 let Inst{6} = lane{0};
4796 def VSETLNi32 : NVSetLane<{1,1,1,0,0,0,?,0}, 0b1011, 0b00, (outs DPR:$V),
4797 (ins DPR:$src1, GPR:$R, VectorIndex32:$lane),
4798 IIC_VMOVISL, "vmov", "32", "$V$lane, $R",
4799 [(set DPR:$V, (insertelt (v2i32 DPR:$src1),
4800 GPR:$R, imm:$lane))]> {
4801 let Inst{21} = lane{0};
4804 def : Pat<(vector_insert (v16i8 QPR:$src1), GPR:$src2, imm:$lane),
4805 (v16i8 (INSERT_SUBREG QPR:$src1,
4806 (v8i8 (VSETLNi8 (v8i8 (EXTRACT_SUBREG QPR:$src1,
4807 (DSubReg_i8_reg imm:$lane))),
4808 GPR:$src2, (SubReg_i8_lane imm:$lane))),
4809 (DSubReg_i8_reg imm:$lane)))>;
4810 def : Pat<(vector_insert (v8i16 QPR:$src1), GPR:$src2, imm:$lane),
4811 (v8i16 (INSERT_SUBREG QPR:$src1,
4812 (v4i16 (VSETLNi16 (v4i16 (EXTRACT_SUBREG QPR:$src1,
4813 (DSubReg_i16_reg imm:$lane))),
4814 GPR:$src2, (SubReg_i16_lane imm:$lane))),
4815 (DSubReg_i16_reg imm:$lane)))>;
4816 def : Pat<(insertelt (v4i32 QPR:$src1), GPR:$src2, imm:$lane),
4817 (v4i32 (INSERT_SUBREG QPR:$src1,
4818 (v2i32 (VSETLNi32 (v2i32 (EXTRACT_SUBREG QPR:$src1,
4819 (DSubReg_i32_reg imm:$lane))),
4820 GPR:$src2, (SubReg_i32_lane imm:$lane))),
4821 (DSubReg_i32_reg imm:$lane)))>;
4823 def : Pat<(v2f32 (insertelt DPR:$src1, SPR:$src2, imm:$src3)),
4824 (INSERT_SUBREG (v2f32 (COPY_TO_REGCLASS DPR:$src1, DPR_VFP2)),
4825 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4826 def : Pat<(v4f32 (insertelt QPR:$src1, SPR:$src2, imm:$src3)),
4827 (INSERT_SUBREG (v4f32 (COPY_TO_REGCLASS QPR:$src1, QPR_VFP2)),
4828 SPR:$src2, (SSubReg_f32_reg imm:$src3))>;
4830 //def : Pat<(v2i64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4831 // (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4832 def : Pat<(v2f64 (insertelt QPR:$src1, DPR:$src2, imm:$src3)),
4833 (INSERT_SUBREG QPR:$src1, DPR:$src2, (DSubReg_f64_reg imm:$src3))>;
4835 def : Pat<(v2f32 (scalar_to_vector SPR:$src)),
4836 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4837 def : Pat<(v2f64 (scalar_to_vector (f64 DPR:$src))),
4838 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
4839 def : Pat<(v4f32 (scalar_to_vector SPR:$src)),
4840 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
4842 def : Pat<(v8i8 (scalar_to_vector GPR:$src)),
4843 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4844 def : Pat<(v4i16 (scalar_to_vector GPR:$src)),
4845 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4846 def : Pat<(v2i32 (scalar_to_vector GPR:$src)),
4847 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
4849 def : Pat<(v16i8 (scalar_to_vector GPR:$src)),
4850 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
4851 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4853 def : Pat<(v8i16 (scalar_to_vector GPR:$src)),
4854 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
4855 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4857 def : Pat<(v4i32 (scalar_to_vector GPR:$src)),
4858 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
4859 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
4862 // VDUP : Vector Duplicate (from ARM core register to all elements)
4864 class VDUPD<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4865 : NVDup<opcod1, 0b1011, opcod3, (outs DPR:$V), (ins GPR:$R),
4866 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4867 [(set DPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4868 class VDUPQ<bits<8> opcod1, bits<2> opcod3, string Dt, ValueType Ty>
4869 : NVDup<opcod1, 0b1011, opcod3, (outs QPR:$V), (ins GPR:$R),
4870 IIC_VMOVIS, "vdup", Dt, "$V, $R",
4871 [(set QPR:$V, (Ty (NEONvdup (i32 GPR:$R))))]>;
4873 def VDUP8d : VDUPD<0b11101100, 0b00, "8", v8i8>;
4874 def VDUP16d : VDUPD<0b11101000, 0b01, "16", v4i16>;
4875 def VDUP32d : VDUPD<0b11101000, 0b00, "32", v2i32>;
4876 def VDUP8q : VDUPQ<0b11101110, 0b00, "8", v16i8>;
4877 def VDUP16q : VDUPQ<0b11101010, 0b01, "16", v8i16>;
4878 def VDUP32q : VDUPQ<0b11101010, 0b00, "32", v4i32>;
4880 def : Pat<(v2f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32d GPR:$R)>;
4881 def : Pat<(v4f32 (NEONvdup (f32 (bitconvert GPR:$R)))), (VDUP32q GPR:$R)>;
4883 // VDUP : Vector Duplicate Lane (from scalar to all elements)
4885 class VDUPLND<bits<4> op19_16, string OpcodeStr, string Dt,
4886 ValueType Ty, Operand IdxTy>
4887 : NVDupLane<op19_16, 0, (outs DPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4888 IIC_VMOVD, OpcodeStr, Dt, "$Vd, $Vm$lane",
4889 [(set DPR:$Vd, (Ty (NEONvduplane (Ty DPR:$Vm), imm:$lane)))]>;
4891 class VDUPLNQ<bits<4> op19_16, string OpcodeStr, string Dt,
4892 ValueType ResTy, ValueType OpTy, Operand IdxTy>
4893 : NVDupLane<op19_16, 1, (outs QPR:$Vd), (ins DPR:$Vm, IdxTy:$lane),
4894 IIC_VMOVQ, OpcodeStr, Dt, "$Vd, $Vm$lane",
4895 [(set QPR:$Vd, (ResTy (NEONvduplane (OpTy DPR:$Vm),
4896 VectorIndex32:$lane)))]>;
4898 // Inst{19-16} is partially specified depending on the element size.
4900 def VDUPLN8d : VDUPLND<{?,?,?,1}, "vdup", "8", v8i8, VectorIndex8> {
4902 let Inst{19-17} = lane{2-0};
4904 def VDUPLN16d : VDUPLND<{?,?,1,0}, "vdup", "16", v4i16, VectorIndex16> {
4906 let Inst{19-18} = lane{1-0};
4908 def VDUPLN32d : VDUPLND<{?,1,0,0}, "vdup", "32", v2i32, VectorIndex32> {
4910 let Inst{19} = lane{0};
4912 def VDUPLN8q : VDUPLNQ<{?,?,?,1}, "vdup", "8", v16i8, v8i8, VectorIndex8> {
4914 let Inst{19-17} = lane{2-0};
4916 def VDUPLN16q : VDUPLNQ<{?,?,1,0}, "vdup", "16", v8i16, v4i16, VectorIndex16> {
4918 let Inst{19-18} = lane{1-0};
4920 def VDUPLN32q : VDUPLNQ<{?,1,0,0}, "vdup", "32", v4i32, v2i32, VectorIndex32> {
4922 let Inst{19} = lane{0};
4925 def : Pat<(v2f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4926 (VDUPLN32d DPR:$Vm, imm:$lane)>;
4928 def : Pat<(v4f32 (NEONvduplane (v2f32 DPR:$Vm), imm:$lane)),
4929 (VDUPLN32q DPR:$Vm, imm:$lane)>;
4931 def : Pat<(v16i8 (NEONvduplane (v16i8 QPR:$src), imm:$lane)),
4932 (v16i8 (VDUPLN8q (v8i8 (EXTRACT_SUBREG QPR:$src,
4933 (DSubReg_i8_reg imm:$lane))),
4934 (SubReg_i8_lane imm:$lane)))>;
4935 def : Pat<(v8i16 (NEONvduplane (v8i16 QPR:$src), imm:$lane)),
4936 (v8i16 (VDUPLN16q (v4i16 (EXTRACT_SUBREG QPR:$src,
4937 (DSubReg_i16_reg imm:$lane))),
4938 (SubReg_i16_lane imm:$lane)))>;
4939 def : Pat<(v4i32 (NEONvduplane (v4i32 QPR:$src), imm:$lane)),
4940 (v4i32 (VDUPLN32q (v2i32 (EXTRACT_SUBREG QPR:$src,
4941 (DSubReg_i32_reg imm:$lane))),
4942 (SubReg_i32_lane imm:$lane)))>;
4943 def : Pat<(v4f32 (NEONvduplane (v4f32 QPR:$src), imm:$lane)),
4944 (v4f32 (VDUPLN32q (v2f32 (EXTRACT_SUBREG QPR:$src,
4945 (DSubReg_i32_reg imm:$lane))),
4946 (SubReg_i32_lane imm:$lane)))>;
4948 def VDUPfdf : PseudoNeonI<(outs DPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4949 [(set DPR:$dst, (v2f32 (NEONvdup (f32 SPR:$src))))]>;
4950 def VDUPfqf : PseudoNeonI<(outs QPR:$dst), (ins SPR:$src), IIC_VMOVD, "",
4951 [(set QPR:$dst, (v4f32 (NEONvdup (f32 SPR:$src))))]>;
4953 // VMOVN : Vector Narrowing Move
4954 defm VMOVN : N2VN_HSD<0b11,0b11,0b10,0b00100,0,0, IIC_VMOVN,
4955 "vmovn", "i", trunc>;
4956 // VQMOVN : Vector Saturating Narrowing Move
4957 defm VQMOVNs : N2VNInt_HSD<0b11,0b11,0b10,0b00101,0,0, IIC_VQUNAiD,
4958 "vqmovn", "s", int_arm_neon_vqmovns>;
4959 defm VQMOVNu : N2VNInt_HSD<0b11,0b11,0b10,0b00101,1,0, IIC_VQUNAiD,
4960 "vqmovn", "u", int_arm_neon_vqmovnu>;
4961 defm VQMOVNsu : N2VNInt_HSD<0b11,0b11,0b10,0b00100,1,0, IIC_VQUNAiD,
4962 "vqmovun", "s", int_arm_neon_vqmovnsu>;
4963 // VMOVL : Vector Lengthening Move
4964 defm VMOVLs : N2VL_QHS<0b01,0b10100,0,1, "vmovl", "s", sext>;
4965 defm VMOVLu : N2VL_QHS<0b11,0b10100,0,1, "vmovl", "u", zext>;
4967 // Vector Conversions.
4969 // VCVT : Vector Convert Between Floating-Point and Integers
4970 def VCVTf2sd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4971 v2i32, v2f32, fp_to_sint>;
4972 def VCVTf2ud : N2VD<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4973 v2i32, v2f32, fp_to_uint>;
4974 def VCVTs2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4975 v2f32, v2i32, sint_to_fp>;
4976 def VCVTu2fd : N2VD<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4977 v2f32, v2i32, uint_to_fp>;
4979 def VCVTf2sq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01110, 0, "vcvt", "s32.f32",
4980 v4i32, v4f32, fp_to_sint>;
4981 def VCVTf2uq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01111, 0, "vcvt", "u32.f32",
4982 v4i32, v4f32, fp_to_uint>;
4983 def VCVTs2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01100, 0, "vcvt", "f32.s32",
4984 v4f32, v4i32, sint_to_fp>;
4985 def VCVTu2fq : N2VQ<0b11, 0b11, 0b10, 0b11, 0b01101, 0, "vcvt", "f32.u32",
4986 v4f32, v4i32, uint_to_fp>;
4988 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
4989 let DecoderMethod = "DecodeVCVTD" in {
4990 def VCVTf2xsd : N2VCvtD<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
4991 v2i32, v2f32, int_arm_neon_vcvtfp2fxs>;
4992 def VCVTf2xud : N2VCvtD<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
4993 v2i32, v2f32, int_arm_neon_vcvtfp2fxu>;
4994 def VCVTxs2fd : N2VCvtD<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
4995 v2f32, v2i32, int_arm_neon_vcvtfxs2fp>;
4996 def VCVTxu2fd : N2VCvtD<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
4997 v2f32, v2i32, int_arm_neon_vcvtfxu2fp>;
5000 let DecoderMethod = "DecodeVCVTQ" in {
5001 def VCVTf2xsq : N2VCvtQ<0, 1, 0b1111, 0, 1, "vcvt", "s32.f32",
5002 v4i32, v4f32, int_arm_neon_vcvtfp2fxs>;
5003 def VCVTf2xuq : N2VCvtQ<1, 1, 0b1111, 0, 1, "vcvt", "u32.f32",
5004 v4i32, v4f32, int_arm_neon_vcvtfp2fxu>;
5005 def VCVTxs2fq : N2VCvtQ<0, 1, 0b1110, 0, 1, "vcvt", "f32.s32",
5006 v4f32, v4i32, int_arm_neon_vcvtfxs2fp>;
5007 def VCVTxu2fq : N2VCvtQ<1, 1, 0b1110, 0, 1, "vcvt", "f32.u32",
5008 v4f32, v4i32, int_arm_neon_vcvtfxu2fp>;
5011 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
5012 def VCVTf2h : N2VNInt<0b11, 0b11, 0b01, 0b10, 0b01100, 0, 0,
5013 IIC_VUNAQ, "vcvt", "f16.f32",
5014 v4i16, v4f32, int_arm_neon_vcvtfp2hf>,
5015 Requires<[HasNEON, HasFP16]>;
5016 def VCVTh2f : N2VLInt<0b11, 0b11, 0b01, 0b10, 0b01110, 0, 0,
5017 IIC_VUNAQ, "vcvt", "f32.f16",
5018 v4f32, v4i16, int_arm_neon_vcvthf2fp>,
5019 Requires<[HasNEON, HasFP16]>;
5023 // VREV64 : Vector Reverse elements within 64-bit doublewords
5025 class VREV64D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5026 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 0, 0, (outs DPR:$Vd),
5027 (ins DPR:$Vm), IIC_VMOVD,
5028 OpcodeStr, Dt, "$Vd, $Vm", "",
5029 [(set DPR:$Vd, (Ty (NEONvrev64 (Ty DPR:$Vm))))]>;
5030 class VREV64Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5031 : N2V<0b11, 0b11, op19_18, 0b00, 0b00000, 1, 0, (outs QPR:$Vd),
5032 (ins QPR:$Vm), IIC_VMOVQ,
5033 OpcodeStr, Dt, "$Vd, $Vm", "",
5034 [(set QPR:$Vd, (Ty (NEONvrev64 (Ty QPR:$Vm))))]>;
5036 def VREV64d8 : VREV64D<0b00, "vrev64", "8", v8i8>;
5037 def VREV64d16 : VREV64D<0b01, "vrev64", "16", v4i16>;
5038 def VREV64d32 : VREV64D<0b10, "vrev64", "32", v2i32>;
5039 def : Pat<(v2f32 (NEONvrev64 (v2f32 DPR:$Vm))), (VREV64d32 DPR:$Vm)>;
5041 def VREV64q8 : VREV64Q<0b00, "vrev64", "8", v16i8>;
5042 def VREV64q16 : VREV64Q<0b01, "vrev64", "16", v8i16>;
5043 def VREV64q32 : VREV64Q<0b10, "vrev64", "32", v4i32>;
5044 def : Pat<(v4f32 (NEONvrev64 (v4f32 QPR:$Vm))), (VREV64q32 QPR:$Vm)>;
5046 // VREV32 : Vector Reverse elements within 32-bit words
5048 class VREV32D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5049 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 0, 0, (outs DPR:$Vd),
5050 (ins DPR:$Vm), IIC_VMOVD,
5051 OpcodeStr, Dt, "$Vd, $Vm", "",
5052 [(set DPR:$Vd, (Ty (NEONvrev32 (Ty DPR:$Vm))))]>;
5053 class VREV32Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5054 : N2V<0b11, 0b11, op19_18, 0b00, 0b00001, 1, 0, (outs QPR:$Vd),
5055 (ins QPR:$Vm), IIC_VMOVQ,
5056 OpcodeStr, Dt, "$Vd, $Vm", "",
5057 [(set QPR:$Vd, (Ty (NEONvrev32 (Ty QPR:$Vm))))]>;
5059 def VREV32d8 : VREV32D<0b00, "vrev32", "8", v8i8>;
5060 def VREV32d16 : VREV32D<0b01, "vrev32", "16", v4i16>;
5062 def VREV32q8 : VREV32Q<0b00, "vrev32", "8", v16i8>;
5063 def VREV32q16 : VREV32Q<0b01, "vrev32", "16", v8i16>;
5065 // VREV16 : Vector Reverse elements within 16-bit halfwords
5067 class VREV16D<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5068 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 0, 0, (outs DPR:$Vd),
5069 (ins DPR:$Vm), IIC_VMOVD,
5070 OpcodeStr, Dt, "$Vd, $Vm", "",
5071 [(set DPR:$Vd, (Ty (NEONvrev16 (Ty DPR:$Vm))))]>;
5072 class VREV16Q<bits<2> op19_18, string OpcodeStr, string Dt, ValueType Ty>
5073 : N2V<0b11, 0b11, op19_18, 0b00, 0b00010, 1, 0, (outs QPR:$Vd),
5074 (ins QPR:$Vm), IIC_VMOVQ,
5075 OpcodeStr, Dt, "$Vd, $Vm", "",
5076 [(set QPR:$Vd, (Ty (NEONvrev16 (Ty QPR:$Vm))))]>;
5078 def VREV16d8 : VREV16D<0b00, "vrev16", "8", v8i8>;
5079 def VREV16q8 : VREV16Q<0b00, "vrev16", "8", v16i8>;
5081 // Other Vector Shuffles.
5083 // Aligned extractions: really just dropping registers
5085 class AlignedVEXTq<ValueType DestTy, ValueType SrcTy, SDNodeXForm LaneCVT>
5086 : Pat<(DestTy (vector_extract_subvec (SrcTy QPR:$src), (i32 imm:$start))),
5087 (EXTRACT_SUBREG (SrcTy QPR:$src), (LaneCVT imm:$start))>;
5089 def : AlignedVEXTq<v8i8, v16i8, DSubReg_i8_reg>;
5091 def : AlignedVEXTq<v4i16, v8i16, DSubReg_i16_reg>;
5093 def : AlignedVEXTq<v2i32, v4i32, DSubReg_i32_reg>;
5095 def : AlignedVEXTq<v1i64, v2i64, DSubReg_f64_reg>;
5097 def : AlignedVEXTq<v2f32, v4f32, DSubReg_i32_reg>;
5100 // VEXT : Vector Extract
5102 class VEXTd<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5103 : N3V<0,1,0b11,{?,?,?,?},0,0, (outs DPR:$Vd),
5104 (ins DPR:$Vn, DPR:$Vm, immTy:$index), NVExtFrm,
5105 IIC_VEXTD, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5106 [(set DPR:$Vd, (Ty (NEONvext (Ty DPR:$Vn),
5107 (Ty DPR:$Vm), imm:$index)))]> {
5109 let Inst{11-8} = index{3-0};
5112 class VEXTq<string OpcodeStr, string Dt, ValueType Ty, Operand immTy>
5113 : N3V<0,1,0b11,{?,?,?,?},1,0, (outs QPR:$Vd),
5114 (ins QPR:$Vn, QPR:$Vm, imm0_15:$index), NVExtFrm,
5115 IIC_VEXTQ, OpcodeStr, Dt, "$Vd, $Vn, $Vm, $index", "",
5116 [(set QPR:$Vd, (Ty (NEONvext (Ty QPR:$Vn),
5117 (Ty QPR:$Vm), imm:$index)))]> {
5119 let Inst{11-8} = index{3-0};
5122 def VEXTd8 : VEXTd<"vext", "8", v8i8, imm0_7> {
5123 let Inst{11-8} = index{3-0};
5125 def VEXTd16 : VEXTd<"vext", "16", v4i16, imm0_3> {
5126 let Inst{11-9} = index{2-0};
5129 def VEXTd32 : VEXTd<"vext", "32", v2i32, imm0_1> {
5130 let Inst{11-10} = index{1-0};
5131 let Inst{9-8} = 0b00;
5133 def : Pat<(v2f32 (NEONvext (v2f32 DPR:$Vn),
5136 (VEXTd32 DPR:$Vn, DPR:$Vm, imm:$index)>;
5138 def VEXTq8 : VEXTq<"vext", "8", v16i8, imm0_15> {
5139 let Inst{11-8} = index{3-0};
5141 def VEXTq16 : VEXTq<"vext", "16", v8i16, imm0_7> {
5142 let Inst{11-9} = index{2-0};
5145 def VEXTq32 : VEXTq<"vext", "32", v4i32, imm0_3> {
5146 let Inst{11-10} = index{1-0};
5147 let Inst{9-8} = 0b00;
5149 def VEXTq64 : VEXTq<"vext", "64", v2i64, imm0_1> {
5150 let Inst{11} = index{0};
5151 let Inst{10-8} = 0b000;
5153 def : Pat<(v4f32 (NEONvext (v4f32 QPR:$Vn),
5156 (VEXTq32 QPR:$Vn, QPR:$Vm, imm:$index)>;
5158 // VTRN : Vector Transpose
5160 def VTRNd8 : N2VDShuffle<0b00, 0b00001, "vtrn", "8">;
5161 def VTRNd16 : N2VDShuffle<0b01, 0b00001, "vtrn", "16">;
5162 def VTRNd32 : N2VDShuffle<0b10, 0b00001, "vtrn", "32">;
5164 def VTRNq8 : N2VQShuffle<0b00, 0b00001, IIC_VPERMQ, "vtrn", "8">;
5165 def VTRNq16 : N2VQShuffle<0b01, 0b00001, IIC_VPERMQ, "vtrn", "16">;
5166 def VTRNq32 : N2VQShuffle<0b10, 0b00001, IIC_VPERMQ, "vtrn", "32">;
5168 // VUZP : Vector Unzip (Deinterleave)
5170 def VUZPd8 : N2VDShuffle<0b00, 0b00010, "vuzp", "8">;
5171 def VUZPd16 : N2VDShuffle<0b01, 0b00010, "vuzp", "16">;
5172 def VUZPd32 : N2VDShuffle<0b10, 0b00010, "vuzp", "32">;
5174 def VUZPq8 : N2VQShuffle<0b00, 0b00010, IIC_VPERMQ3, "vuzp", "8">;
5175 def VUZPq16 : N2VQShuffle<0b01, 0b00010, IIC_VPERMQ3, "vuzp", "16">;
5176 def VUZPq32 : N2VQShuffle<0b10, 0b00010, IIC_VPERMQ3, "vuzp", "32">;
5178 // VZIP : Vector Zip (Interleave)
5180 def VZIPd8 : N2VDShuffle<0b00, 0b00011, "vzip", "8">;
5181 def VZIPd16 : N2VDShuffle<0b01, 0b00011, "vzip", "16">;
5182 def VZIPd32 : N2VDShuffle<0b10, 0b00011, "vzip", "32">;
5184 def VZIPq8 : N2VQShuffle<0b00, 0b00011, IIC_VPERMQ3, "vzip", "8">;
5185 def VZIPq16 : N2VQShuffle<0b01, 0b00011, IIC_VPERMQ3, "vzip", "16">;
5186 def VZIPq32 : N2VQShuffle<0b10, 0b00011, IIC_VPERMQ3, "vzip", "32">;
5188 // Vector Table Lookup and Table Extension.
5190 // VTBL : Vector Table Lookup
5191 let DecoderMethod = "DecodeTBLInstruction" in {
5193 : N3V<1,1,0b11,0b1000,0,0, (outs DPR:$Vd),
5194 (ins VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB1,
5195 "vtbl", "8", "$Vd, $Vn, $Vm", "",
5196 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbl1 VecListOneD:$Vn, DPR:$Vm)))]>;
5197 let hasExtraSrcRegAllocReq = 1 in {
5199 : N3V<1,1,0b11,0b1001,0,0, (outs DPR:$Vd),
5200 (ins VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB2,
5201 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5203 : N3V<1,1,0b11,0b1010,0,0, (outs DPR:$Vd),
5204 (ins VecListThreeD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTB3,
5205 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5207 : N3V<1,1,0b11,0b1011,0,0, (outs DPR:$Vd),
5208 (ins VecListFourD:$Vn, DPR:$Vm),
5210 "vtbl", "8", "$Vd, $Vn, $Vm", "", []>;
5211 } // hasExtraSrcRegAllocReq = 1
5214 : PseudoNeonI<(outs DPR:$dst), (ins QPR:$tbl, DPR:$src), IIC_VTB2, "", []>;
5216 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB3, "", []>;
5218 : PseudoNeonI<(outs DPR:$dst), (ins QQPR:$tbl, DPR:$src), IIC_VTB4, "", []>;
5220 // VTBX : Vector Table Extension
5222 : N3V<1,1,0b11,0b1000,1,0, (outs DPR:$Vd),
5223 (ins DPR:$orig, VecListOneD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX1,
5224 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd",
5225 [(set DPR:$Vd, (v8i8 (int_arm_neon_vtbx1
5226 DPR:$orig, VecListOneD:$Vn, DPR:$Vm)))]>;
5227 let hasExtraSrcRegAllocReq = 1 in {
5229 : N3V<1,1,0b11,0b1001,1,0, (outs DPR:$Vd),
5230 (ins DPR:$orig, VecListTwoD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX2,
5231 "vtbx", "8", "$Vd, $Vn, $Vm", "$orig = $Vd", []>;
5233 : N3V<1,1,0b11,0b1010,1,0, (outs DPR:$Vd),
5234 (ins DPR:$orig, VecListThreeD:$Vn, DPR:$Vm),
5235 NVTBLFrm, IIC_VTBX3,
5236 "vtbx", "8", "$Vd, $Vn, $Vm",
5239 : N3V<1,1,0b11,0b1011,1,0, (outs DPR:$Vd),
5240 (ins DPR:$orig, VecListFourD:$Vn, DPR:$Vm), NVTBLFrm, IIC_VTBX4,
5241 "vtbx", "8", "$Vd, $Vn, $Vm",
5243 } // hasExtraSrcRegAllocReq = 1
5246 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QPR:$tbl, DPR:$src),
5247 IIC_VTBX2, "$orig = $dst", []>;
5249 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5250 IIC_VTBX3, "$orig = $dst", []>;
5252 : PseudoNeonI<(outs DPR:$dst), (ins DPR:$orig, QQPR:$tbl, DPR:$src),
5253 IIC_VTBX4, "$orig = $dst", []>;
5254 } // DecoderMethod = "DecodeTBLInstruction"
5256 //===----------------------------------------------------------------------===//
5257 // NEON instructions for single-precision FP math
5258 //===----------------------------------------------------------------------===//
5260 class N2VSPat<SDNode OpNode, NeonI Inst>
5261 : NEONFPPat<(f32 (OpNode SPR:$a)),
5263 (v2f32 (COPY_TO_REGCLASS (Inst
5265 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5266 SPR:$a, ssub_0)), DPR_VFP2)), ssub_0)>;
5268 class N3VSPat<SDNode OpNode, NeonI Inst>
5269 : NEONFPPat<(f32 (OpNode SPR:$a, SPR:$b)),
5271 (v2f32 (COPY_TO_REGCLASS (Inst
5273 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5276 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5277 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5279 class N3VSMulOpPat<SDNode MulNode, SDNode OpNode, NeonI Inst>
5280 : NEONFPPat<(f32 (OpNode SPR:$acc, (f32 (MulNode SPR:$a, SPR:$b)))),
5282 (v2f32 (COPY_TO_REGCLASS (Inst
5284 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5287 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5290 (v2f32 (COPY_TO_REGCLASS (v2f32 (IMPLICIT_DEF)), DPR_VFP2)),
5291 SPR:$b, ssub_0)), DPR_VFP2)), ssub_0)>;
5293 def : N3VSPat<fadd, VADDfd>;
5294 def : N3VSPat<fsub, VSUBfd>;
5295 def : N3VSPat<fmul, VMULfd>;
5296 def : N3VSMulOpPat<fmul, fadd, VMLAfd>,
5297 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5298 def : N3VSMulOpPat<fmul, fsub, VMLSfd>,
5299 Requires<[HasNEON, UseNEONForFP, UseFPVMLx]>;
5300 def : N2VSPat<fabs, VABSfd>;
5301 def : N2VSPat<fneg, VNEGfd>;
5302 def : N3VSPat<NEONfmax, VMAXfd>;
5303 def : N3VSPat<NEONfmin, VMINfd>;
5304 def : N2VSPat<arm_ftosi, VCVTf2sd>;
5305 def : N2VSPat<arm_ftoui, VCVTf2ud>;
5306 def : N2VSPat<arm_sitof, VCVTs2fd>;
5307 def : N2VSPat<arm_uitof, VCVTu2fd>;
5309 //===----------------------------------------------------------------------===//
5310 // Non-Instruction Patterns
5311 //===----------------------------------------------------------------------===//
5314 def : Pat<(v1i64 (bitconvert (v2i32 DPR:$src))), (v1i64 DPR:$src)>;
5315 def : Pat<(v1i64 (bitconvert (v4i16 DPR:$src))), (v1i64 DPR:$src)>;
5316 def : Pat<(v1i64 (bitconvert (v8i8 DPR:$src))), (v1i64 DPR:$src)>;
5317 def : Pat<(v1i64 (bitconvert (f64 DPR:$src))), (v1i64 DPR:$src)>;
5318 def : Pat<(v1i64 (bitconvert (v2f32 DPR:$src))), (v1i64 DPR:$src)>;
5319 def : Pat<(v2i32 (bitconvert (v1i64 DPR:$src))), (v2i32 DPR:$src)>;
5320 def : Pat<(v2i32 (bitconvert (v4i16 DPR:$src))), (v2i32 DPR:$src)>;
5321 def : Pat<(v2i32 (bitconvert (v8i8 DPR:$src))), (v2i32 DPR:$src)>;
5322 def : Pat<(v2i32 (bitconvert (f64 DPR:$src))), (v2i32 DPR:$src)>;
5323 def : Pat<(v2i32 (bitconvert (v2f32 DPR:$src))), (v2i32 DPR:$src)>;
5324 def : Pat<(v4i16 (bitconvert (v1i64 DPR:$src))), (v4i16 DPR:$src)>;
5325 def : Pat<(v4i16 (bitconvert (v2i32 DPR:$src))), (v4i16 DPR:$src)>;
5326 def : Pat<(v4i16 (bitconvert (v8i8 DPR:$src))), (v4i16 DPR:$src)>;
5327 def : Pat<(v4i16 (bitconvert (f64 DPR:$src))), (v4i16 DPR:$src)>;
5328 def : Pat<(v4i16 (bitconvert (v2f32 DPR:$src))), (v4i16 DPR:$src)>;
5329 def : Pat<(v8i8 (bitconvert (v1i64 DPR:$src))), (v8i8 DPR:$src)>;
5330 def : Pat<(v8i8 (bitconvert (v2i32 DPR:$src))), (v8i8 DPR:$src)>;
5331 def : Pat<(v8i8 (bitconvert (v4i16 DPR:$src))), (v8i8 DPR:$src)>;
5332 def : Pat<(v8i8 (bitconvert (f64 DPR:$src))), (v8i8 DPR:$src)>;
5333 def : Pat<(v8i8 (bitconvert (v2f32 DPR:$src))), (v8i8 DPR:$src)>;
5334 def : Pat<(f64 (bitconvert (v1i64 DPR:$src))), (f64 DPR:$src)>;
5335 def : Pat<(f64 (bitconvert (v2i32 DPR:$src))), (f64 DPR:$src)>;
5336 def : Pat<(f64 (bitconvert (v4i16 DPR:$src))), (f64 DPR:$src)>;
5337 def : Pat<(f64 (bitconvert (v8i8 DPR:$src))), (f64 DPR:$src)>;
5338 def : Pat<(f64 (bitconvert (v2f32 DPR:$src))), (f64 DPR:$src)>;
5339 def : Pat<(v2f32 (bitconvert (f64 DPR:$src))), (v2f32 DPR:$src)>;
5340 def : Pat<(v2f32 (bitconvert (v1i64 DPR:$src))), (v2f32 DPR:$src)>;
5341 def : Pat<(v2f32 (bitconvert (v2i32 DPR:$src))), (v2f32 DPR:$src)>;
5342 def : Pat<(v2f32 (bitconvert (v4i16 DPR:$src))), (v2f32 DPR:$src)>;
5343 def : Pat<(v2f32 (bitconvert (v8i8 DPR:$src))), (v2f32 DPR:$src)>;
5345 def : Pat<(v2i64 (bitconvert (v4i32 QPR:$src))), (v2i64 QPR:$src)>;
5346 def : Pat<(v2i64 (bitconvert (v8i16 QPR:$src))), (v2i64 QPR:$src)>;
5347 def : Pat<(v2i64 (bitconvert (v16i8 QPR:$src))), (v2i64 QPR:$src)>;
5348 def : Pat<(v2i64 (bitconvert (v2f64 QPR:$src))), (v2i64 QPR:$src)>;
5349 def : Pat<(v2i64 (bitconvert (v4f32 QPR:$src))), (v2i64 QPR:$src)>;
5350 def : Pat<(v4i32 (bitconvert (v2i64 QPR:$src))), (v4i32 QPR:$src)>;
5351 def : Pat<(v4i32 (bitconvert (v8i16 QPR:$src))), (v4i32 QPR:$src)>;
5352 def : Pat<(v4i32 (bitconvert (v16i8 QPR:$src))), (v4i32 QPR:$src)>;
5353 def : Pat<(v4i32 (bitconvert (v2f64 QPR:$src))), (v4i32 QPR:$src)>;
5354 def : Pat<(v4i32 (bitconvert (v4f32 QPR:$src))), (v4i32 QPR:$src)>;
5355 def : Pat<(v8i16 (bitconvert (v2i64 QPR:$src))), (v8i16 QPR:$src)>;
5356 def : Pat<(v8i16 (bitconvert (v4i32 QPR:$src))), (v8i16 QPR:$src)>;
5357 def : Pat<(v8i16 (bitconvert (v16i8 QPR:$src))), (v8i16 QPR:$src)>;
5358 def : Pat<(v8i16 (bitconvert (v2f64 QPR:$src))), (v8i16 QPR:$src)>;
5359 def : Pat<(v8i16 (bitconvert (v4f32 QPR:$src))), (v8i16 QPR:$src)>;
5360 def : Pat<(v16i8 (bitconvert (v2i64 QPR:$src))), (v16i8 QPR:$src)>;
5361 def : Pat<(v16i8 (bitconvert (v4i32 QPR:$src))), (v16i8 QPR:$src)>;
5362 def : Pat<(v16i8 (bitconvert (v8i16 QPR:$src))), (v16i8 QPR:$src)>;
5363 def : Pat<(v16i8 (bitconvert (v2f64 QPR:$src))), (v16i8 QPR:$src)>;
5364 def : Pat<(v16i8 (bitconvert (v4f32 QPR:$src))), (v16i8 QPR:$src)>;
5365 def : Pat<(v4f32 (bitconvert (v2i64 QPR:$src))), (v4f32 QPR:$src)>;
5366 def : Pat<(v4f32 (bitconvert (v4i32 QPR:$src))), (v4f32 QPR:$src)>;
5367 def : Pat<(v4f32 (bitconvert (v8i16 QPR:$src))), (v4f32 QPR:$src)>;
5368 def : Pat<(v4f32 (bitconvert (v16i8 QPR:$src))), (v4f32 QPR:$src)>;
5369 def : Pat<(v4f32 (bitconvert (v2f64 QPR:$src))), (v4f32 QPR:$src)>;
5370 def : Pat<(v2f64 (bitconvert (v2i64 QPR:$src))), (v2f64 QPR:$src)>;
5371 def : Pat<(v2f64 (bitconvert (v4i32 QPR:$src))), (v2f64 QPR:$src)>;
5372 def : Pat<(v2f64 (bitconvert (v8i16 QPR:$src))), (v2f64 QPR:$src)>;
5373 def : Pat<(v2f64 (bitconvert (v16i8 QPR:$src))), (v2f64 QPR:$src)>;
5374 def : Pat<(v2f64 (bitconvert (v4f32 QPR:$src))), (v2f64 QPR:$src)>;
5377 //===----------------------------------------------------------------------===//
5378 // Assembler aliases
5381 def : VFP2InstAlias<"fmdhr${p} $Dd, $Rn",
5382 (VSETLNi32 DPR:$Dd, GPR:$Rn, 1, pred:$p)>;
5383 def : VFP2InstAlias<"fmdlr${p} $Dd, $Rn",
5384 (VSETLNi32 DPR:$Dd, GPR:$Rn, 0, pred:$p)>;
5387 // VADD two-operand aliases.
5388 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5389 (VADDv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5390 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5391 (VADDv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5392 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5393 (VADDv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5394 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5395 (VADDv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5397 def : NEONInstAlias<"vadd${p}.i8 $Vdn, $Vm",
5398 (VADDv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5399 def : NEONInstAlias<"vadd${p}.i16 $Vdn, $Vm",
5400 (VADDv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5401 def : NEONInstAlias<"vadd${p}.i32 $Vdn, $Vm",
5402 (VADDv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5403 def : NEONInstAlias<"vadd${p}.i64 $Vdn, $Vm",
5404 (VADDv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5406 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5407 (VADDfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5408 def : NEONInstAlias<"vadd${p}.f32 $Vdn, $Vm",
5409 (VADDfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5411 // VSUB two-operand aliases.
5412 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5413 (VSUBv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5414 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5415 (VSUBv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5416 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5417 (VSUBv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5418 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5419 (VSUBv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5421 def : NEONInstAlias<"vsub${p}.i8 $Vdn, $Vm",
5422 (VSUBv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5423 def : NEONInstAlias<"vsub${p}.i16 $Vdn, $Vm",
5424 (VSUBv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5425 def : NEONInstAlias<"vsub${p}.i32 $Vdn, $Vm",
5426 (VSUBv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5427 def : NEONInstAlias<"vsub${p}.i64 $Vdn, $Vm",
5428 (VSUBv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5430 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5431 (VSUBfd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5432 def : NEONInstAlias<"vsub${p}.f32 $Vdn, $Vm",
5433 (VSUBfq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5435 // VADDW two-operand aliases.
5436 def : NEONInstAlias<"vaddw${p}.s8 $Vdn, $Vm",
5437 (VADDWsv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5438 def : NEONInstAlias<"vaddw${p}.s16 $Vdn, $Vm",
5439 (VADDWsv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5440 def : NEONInstAlias<"vaddw${p}.s32 $Vdn, $Vm",
5441 (VADDWsv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5442 def : NEONInstAlias<"vaddw${p}.u8 $Vdn, $Vm",
5443 (VADDWuv8i16 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5444 def : NEONInstAlias<"vaddw${p}.u16 $Vdn, $Vm",
5445 (VADDWuv4i32 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5446 def : NEONInstAlias<"vaddw${p}.u32 $Vdn, $Vm",
5447 (VADDWuv2i64 QPR:$Vdn, QPR:$Vdn, DPR:$Vm, pred:$p)>;
5449 // VAND/VBIC/VEOR/VORR accept but do not require a type suffix.
5450 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5451 (VANDd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5452 defm : VFPDTAnyInstAlias<"vand${p}", "$Vd, $Vn, $Vm",
5453 (VANDq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5454 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5455 (VBICd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5456 defm : VFPDTAnyInstAlias<"vbic${p}", "$Vd, $Vn, $Vm",
5457 (VBICq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5458 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5459 (VEORd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5460 defm : VFPDTAnyInstAlias<"veor${p}", "$Vd, $Vn, $Vm",
5461 (VEORq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5462 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5463 (VORRd DPR:$Vd, DPR:$Vn, DPR:$Vm, pred:$p)>;
5464 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vd, $Vn, $Vm",
5465 (VORRq QPR:$Vd, QPR:$Vn, QPR:$Vm, pred:$p)>;
5466 // ... two-operand aliases
5467 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5468 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5469 def : NEONInstAlias<"vand${p} $Vdn, $Vm",
5470 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5471 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5472 (VBICd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5473 def : NEONInstAlias<"vbic${p} $Vdn, $Vm",
5474 (VBICq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5475 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5476 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5477 def : NEONInstAlias<"veor${p} $Vdn, $Vm",
5478 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5479 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5480 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5481 def : NEONInstAlias<"vorr${p} $Vdn, $Vm",
5482 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5484 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5485 (VANDd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5486 defm : VFPDTAnyInstAlias<"vand${p}", "$Vdn, $Vm",
5487 (VANDq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5488 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5489 (VEORd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5490 defm : VFPDTAnyInstAlias<"veor${p}", "$Vdn, $Vm",
5491 (VEORq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5492 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5493 (VORRd DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5494 defm : VFPDTAnyInstAlias<"vorr${p}", "$Vdn, $Vm",
5495 (VORRq QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5497 // VMUL two-operand aliases.
5498 def : NEONInstAlias<"vmul${p}.p8 $Qdn, $Qm",
5499 (VMULpq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5500 def : NEONInstAlias<"vmul${p}.i8 $Qdn, $Qm",
5501 (VMULv16i8 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5502 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Qm",
5503 (VMULv8i16 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5504 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Qm",
5505 (VMULv4i32 QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5507 def : NEONInstAlias<"vmul${p}.p8 $Ddn, $Dm",
5508 (VMULpd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5509 def : NEONInstAlias<"vmul${p}.i8 $Ddn, $Dm",
5510 (VMULv8i8 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5511 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm",
5512 (VMULv4i16 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5513 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm",
5514 (VMULv2i32 DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5516 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Qm",
5517 (VMULfq QPR:$Qdn, QPR:$Qdn, QPR:$Qm, pred:$p)>;
5518 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm",
5519 (VMULfd DPR:$Ddn, DPR:$Ddn, DPR:$Dm, pred:$p)>;
5521 def : NEONInstAlias<"vmul${p}.i16 $Ddn, $Dm$lane",
5522 (VMULslv4i16 DPR:$Ddn, DPR:$Ddn, DPR_8:$Dm,
5523 VectorIndex16:$lane, pred:$p)>;
5524 def : NEONInstAlias<"vmul${p}.i16 $Qdn, $Dm$lane",
5525 (VMULslv8i16 QPR:$Qdn, QPR:$Qdn, DPR_8:$Dm,
5526 VectorIndex16:$lane, pred:$p)>;
5528 def : NEONInstAlias<"vmul${p}.i32 $Ddn, $Dm$lane",
5529 (VMULslv2i32 DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5530 VectorIndex32:$lane, pred:$p)>;
5531 def : NEONInstAlias<"vmul${p}.i32 $Qdn, $Dm$lane",
5532 (VMULslv4i32 QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5533 VectorIndex32:$lane, pred:$p)>;
5535 def : NEONInstAlias<"vmul${p}.f32 $Ddn, $Dm$lane",
5536 (VMULslfd DPR:$Ddn, DPR:$Ddn, DPR_VFP2:$Dm,
5537 VectorIndex32:$lane, pred:$p)>;
5538 def : NEONInstAlias<"vmul${p}.f32 $Qdn, $Dm$lane",
5539 (VMULslfq QPR:$Qdn, QPR:$Qdn, DPR_VFP2:$Dm,
5540 VectorIndex32:$lane, pred:$p)>;
5542 // VQADD (register) two-operand aliases.
5543 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5544 (VQADDsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5545 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5546 (VQADDsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5547 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5548 (VQADDsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5549 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5550 (VQADDsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5551 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5552 (VQADDuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5553 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5554 (VQADDuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5555 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5556 (VQADDuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5557 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5558 (VQADDuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5560 def : NEONInstAlias<"vqadd${p}.s8 $Vdn, $Vm",
5561 (VQADDsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5562 def : NEONInstAlias<"vqadd${p}.s16 $Vdn, $Vm",
5563 (VQADDsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5564 def : NEONInstAlias<"vqadd${p}.s32 $Vdn, $Vm",
5565 (VQADDsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5566 def : NEONInstAlias<"vqadd${p}.s64 $Vdn, $Vm",
5567 (VQADDsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5568 def : NEONInstAlias<"vqadd${p}.u8 $Vdn, $Vm",
5569 (VQADDuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5570 def : NEONInstAlias<"vqadd${p}.u16 $Vdn, $Vm",
5571 (VQADDuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5572 def : NEONInstAlias<"vqadd${p}.u32 $Vdn, $Vm",
5573 (VQADDuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5574 def : NEONInstAlias<"vqadd${p}.u64 $Vdn, $Vm",
5575 (VQADDuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5577 // VSHL (immediate) two-operand aliases.
5578 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5579 (VSHLiv8i8 DPR:$Vdn, DPR:$Vdn, imm0_7:$imm, pred:$p)>;
5580 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5581 (VSHLiv4i16 DPR:$Vdn, DPR:$Vdn, imm0_15:$imm, pred:$p)>;
5582 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5583 (VSHLiv2i32 DPR:$Vdn, DPR:$Vdn, imm0_31:$imm, pred:$p)>;
5584 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5585 (VSHLiv1i64 DPR:$Vdn, DPR:$Vdn, imm0_63:$imm, pred:$p)>;
5587 def : NEONInstAlias<"vshl${p}.i8 $Vdn, $imm",
5588 (VSHLiv16i8 QPR:$Vdn, QPR:$Vdn, imm0_7:$imm, pred:$p)>;
5589 def : NEONInstAlias<"vshl${p}.i16 $Vdn, $imm",
5590 (VSHLiv8i16 QPR:$Vdn, QPR:$Vdn, imm0_15:$imm, pred:$p)>;
5591 def : NEONInstAlias<"vshl${p}.i32 $Vdn, $imm",
5592 (VSHLiv4i32 QPR:$Vdn, QPR:$Vdn, imm0_31:$imm, pred:$p)>;
5593 def : NEONInstAlias<"vshl${p}.i64 $Vdn, $imm",
5594 (VSHLiv2i64 QPR:$Vdn, QPR:$Vdn, imm0_63:$imm, pred:$p)>;
5596 // VSHL (register) two-operand aliases.
5597 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5598 (VSHLsv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5599 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5600 (VSHLsv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5601 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5602 (VSHLsv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5603 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5604 (VSHLsv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5605 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5606 (VSHLuv8i8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5607 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5608 (VSHLuv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5609 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5610 (VSHLuv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5611 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5612 (VSHLuv1i64 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5614 def : NEONInstAlias<"vshl${p}.s8 $Vdn, $Vm",
5615 (VSHLsv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5616 def : NEONInstAlias<"vshl${p}.s16 $Vdn, $Vm",
5617 (VSHLsv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5618 def : NEONInstAlias<"vshl${p}.s32 $Vdn, $Vm",
5619 (VSHLsv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5620 def : NEONInstAlias<"vshl${p}.s64 $Vdn, $Vm",
5621 (VSHLsv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5622 def : NEONInstAlias<"vshl${p}.u8 $Vdn, $Vm",
5623 (VSHLuv16i8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5624 def : NEONInstAlias<"vshl${p}.u16 $Vdn, $Vm",
5625 (VSHLuv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5626 def : NEONInstAlias<"vshl${p}.u32 $Vdn, $Vm",
5627 (VSHLuv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5628 def : NEONInstAlias<"vshl${p}.u64 $Vdn, $Vm",
5629 (VSHLuv2i64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5631 // VSHL (immediate) two-operand aliases.
5632 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5633 (VSHRsv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5634 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5635 (VSHRsv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5636 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5637 (VSHRsv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5638 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5639 (VSHRsv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5641 def : NEONInstAlias<"vshr${p}.s8 $Vdn, $imm",
5642 (VSHRsv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5643 def : NEONInstAlias<"vshr${p}.s16 $Vdn, $imm",
5644 (VSHRsv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5645 def : NEONInstAlias<"vshr${p}.s32 $Vdn, $imm",
5646 (VSHRsv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5647 def : NEONInstAlias<"vshr${p}.s64 $Vdn, $imm",
5648 (VSHRsv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5650 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5651 (VSHRuv8i8 DPR:$Vdn, DPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5652 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5653 (VSHRuv4i16 DPR:$Vdn, DPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5654 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5655 (VSHRuv2i32 DPR:$Vdn, DPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5656 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5657 (VSHRuv1i64 DPR:$Vdn, DPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5659 def : NEONInstAlias<"vshr${p}.u8 $Vdn, $imm",
5660 (VSHRuv16i8 QPR:$Vdn, QPR:$Vdn, shr_imm8:$imm, pred:$p)>;
5661 def : NEONInstAlias<"vshr${p}.u16 $Vdn, $imm",
5662 (VSHRuv8i16 QPR:$Vdn, QPR:$Vdn, shr_imm16:$imm, pred:$p)>;
5663 def : NEONInstAlias<"vshr${p}.u32 $Vdn, $imm",
5664 (VSHRuv4i32 QPR:$Vdn, QPR:$Vdn, shr_imm32:$imm, pred:$p)>;
5665 def : NEONInstAlias<"vshr${p}.u64 $Vdn, $imm",
5666 (VSHRuv2i64 QPR:$Vdn, QPR:$Vdn, shr_imm64:$imm, pred:$p)>;
5668 // VLD1 single-lane pseudo-instructions. These need special handling for
5669 // the lane index that an InstAlias can't handle, so we use these instead.
5670 defm VLD1LNdAsm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr",
5671 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5672 defm VLD1LNdAsm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr",
5673 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5674 defm VLD1LNdAsm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr",
5675 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5677 defm VLD1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr!",
5678 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5679 defm VLD1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr!",
5680 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5681 defm VLD1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr!",
5682 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5683 defm VLD1LNdWB_register_Asm :
5684 NEONDT8AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5685 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5686 rGPR:$Rm, pred:$p)>;
5687 defm VLD1LNdWB_register_Asm :
5688 NEONDT16AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5689 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5690 rGPR:$Rm, pred:$p)>;
5691 defm VLD1LNdWB_register_Asm :
5692 NEONDT32AsmPseudoInst<"vld1${p}", "$list, $addr, $Rm",
5693 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5694 rGPR:$Rm, pred:$p)>;
5697 // VST1 single-lane pseudo-instructions. These need special handling for
5698 // the lane index that an InstAlias can't handle, so we use these instead.
5699 defm VST1LNdAsm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr",
5700 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5701 defm VST1LNdAsm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr",
5702 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5703 defm VST1LNdAsm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr",
5704 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5706 defm VST1LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr!",
5707 (ins VecListOneDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5708 defm VST1LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr!",
5709 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5710 defm VST1LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr!",
5711 (ins VecListOneDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5712 defm VST1LNdWB_register_Asm :
5713 NEONDT8AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5714 (ins VecListOneDByteIndexed:$list, addrmode6:$addr,
5715 rGPR:$Rm, pred:$p)>;
5716 defm VST1LNdWB_register_Asm :
5717 NEONDT16AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5718 (ins VecListOneDHWordIndexed:$list, addrmode6:$addr,
5719 rGPR:$Rm, pred:$p)>;
5720 defm VST1LNdWB_register_Asm :
5721 NEONDT32AsmPseudoInst<"vst1${p}", "$list, $addr, $Rm",
5722 (ins VecListOneDWordIndexed:$list, addrmode6:$addr,
5723 rGPR:$Rm, pred:$p)>;
5725 // VLD2 single-lane pseudo-instructions. These need special handling for
5726 // the lane index that an InstAlias can't handle, so we use these instead.
5727 defm VLD2LNdAsm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr",
5728 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5729 defm VLD2LNdAsm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr",
5730 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5731 defm VLD2LNdAsm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr",
5732 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5734 defm VLD2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr!",
5735 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5736 defm VLD2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr!",
5737 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5738 defm VLD2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr!",
5739 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5740 defm VLD2LNdWB_register_Asm :
5741 NEONDT8AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5742 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5743 rGPR:$Rm, pred:$p)>;
5744 defm VLD2LNdWB_register_Asm :
5745 NEONDT16AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5746 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5747 rGPR:$Rm, pred:$p)>;
5748 defm VLD2LNdWB_register_Asm :
5749 NEONDT32AsmPseudoInst<"vld2${p}", "$list, $addr, $Rm",
5750 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5751 rGPR:$Rm, pred:$p)>;
5754 // VST2 single-lane pseudo-instructions. These need special handling for
5755 // the lane index that an InstAlias can't handle, so we use these instead.
5756 defm VST2LNdAsm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr",
5757 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5758 defm VST2LNdAsm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr",
5759 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5760 defm VST2LNdAsm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr",
5761 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5763 defm VST2LNdWB_fixed_Asm : NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr!",
5764 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr, pred:$p)>;
5765 defm VST2LNdWB_fixed_Asm : NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr!",
5766 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5767 defm VST2LNdWB_fixed_Asm : NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr!",
5768 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr, pred:$p)>;
5769 defm VST2LNdWB_register_Asm :
5770 NEONDT8AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5771 (ins VecListTwoDByteIndexed:$list, addrmode6:$addr,
5772 rGPR:$Rm, pred:$p)>;
5773 defm VST2LNdWB_register_Asm :
5774 NEONDT16AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5775 (ins VecListTwoDHWordIndexed:$list, addrmode6:$addr,
5776 rGPR:$Rm, pred:$p)>;
5777 defm VST2LNdWB_register_Asm :
5778 NEONDT32AsmPseudoInst<"vst2${p}", "$list, $addr, $Rm",
5779 (ins VecListTwoDWordIndexed:$list, addrmode6:$addr,
5780 rGPR:$Rm, pred:$p)>;
5782 // VMOV takes an optional datatype suffix
5783 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5784 (VORRd DPR:$Vd, DPR:$Vm, DPR:$Vm, pred:$p)>;
5785 defm : VFPDTAnyInstAlias<"vmov${p}", "$Vd, $Vm",
5786 (VORRq QPR:$Vd, QPR:$Vm, QPR:$Vm, pred:$p)>;
5788 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5789 // D-register versions.
5790 def : NEONInstAlias<"vcle${p}.s8 $Dd, $Dn, $Dm",
5791 (VCGEsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5792 def : NEONInstAlias<"vcle${p}.s16 $Dd, $Dn, $Dm",
5793 (VCGEsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5794 def : NEONInstAlias<"vcle${p}.s32 $Dd, $Dn, $Dm",
5795 (VCGEsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5796 def : NEONInstAlias<"vcle${p}.u8 $Dd, $Dn, $Dm",
5797 (VCGEuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5798 def : NEONInstAlias<"vcle${p}.u16 $Dd, $Dn, $Dm",
5799 (VCGEuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5800 def : NEONInstAlias<"vcle${p}.u32 $Dd, $Dn, $Dm",
5801 (VCGEuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5802 def : NEONInstAlias<"vcle${p}.f32 $Dd, $Dn, $Dm",
5803 (VCGEfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5804 // Q-register versions.
5805 def : NEONInstAlias<"vcle${p}.s8 $Qd, $Qn, $Qm",
5806 (VCGEsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5807 def : NEONInstAlias<"vcle${p}.s16 $Qd, $Qn, $Qm",
5808 (VCGEsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5809 def : NEONInstAlias<"vcle${p}.s32 $Qd, $Qn, $Qm",
5810 (VCGEsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5811 def : NEONInstAlias<"vcle${p}.u8 $Qd, $Qn, $Qm",
5812 (VCGEuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5813 def : NEONInstAlias<"vcle${p}.u16 $Qd, $Qn, $Qm",
5814 (VCGEuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5815 def : NEONInstAlias<"vcle${p}.u32 $Qd, $Qn, $Qm",
5816 (VCGEuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5817 def : NEONInstAlias<"vcle${p}.f32 $Qd, $Qn, $Qm",
5818 (VCGEfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5820 // VCLT (register) is an assembler alias for VCGT w/ the operands reversed.
5821 // D-register versions.
5822 def : NEONInstAlias<"vclt${p}.s8 $Dd, $Dn, $Dm",
5823 (VCGTsv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5824 def : NEONInstAlias<"vclt${p}.s16 $Dd, $Dn, $Dm",
5825 (VCGTsv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5826 def : NEONInstAlias<"vclt${p}.s32 $Dd, $Dn, $Dm",
5827 (VCGTsv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5828 def : NEONInstAlias<"vclt${p}.u8 $Dd, $Dn, $Dm",
5829 (VCGTuv8i8 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5830 def : NEONInstAlias<"vclt${p}.u16 $Dd, $Dn, $Dm",
5831 (VCGTuv4i16 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5832 def : NEONInstAlias<"vclt${p}.u32 $Dd, $Dn, $Dm",
5833 (VCGTuv2i32 DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5834 def : NEONInstAlias<"vclt${p}.f32 $Dd, $Dn, $Dm",
5835 (VCGTfd DPR:$Dd, DPR:$Dm, DPR:$Dn, pred:$p)>;
5836 // Q-register versions.
5837 def : NEONInstAlias<"vclt${p}.s8 $Qd, $Qn, $Qm",
5838 (VCGTsv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5839 def : NEONInstAlias<"vclt${p}.s16 $Qd, $Qn, $Qm",
5840 (VCGTsv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5841 def : NEONInstAlias<"vclt${p}.s32 $Qd, $Qn, $Qm",
5842 (VCGTsv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5843 def : NEONInstAlias<"vclt${p}.u8 $Qd, $Qn, $Qm",
5844 (VCGTuv16i8 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5845 def : NEONInstAlias<"vclt${p}.u16 $Qd, $Qn, $Qm",
5846 (VCGTuv8i16 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5847 def : NEONInstAlias<"vclt${p}.u32 $Qd, $Qn, $Qm",
5848 (VCGTuv4i32 QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5849 def : NEONInstAlias<"vclt${p}.f32 $Qd, $Qn, $Qm",
5850 (VCGTfq QPR:$Qd, QPR:$Qm, QPR:$Qn, pred:$p)>;
5852 // Two-operand variants for VEXT
5853 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5854 (VEXTd8 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_7:$imm, pred:$p)>;
5855 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5856 (VEXTd16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_3:$imm, pred:$p)>;
5857 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5858 (VEXTd32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, imm0_1:$imm, pred:$p)>;
5860 def : NEONInstAlias<"vext${p}.8 $Vdn, $Vm, $imm",
5861 (VEXTq8 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_15:$imm, pred:$p)>;
5862 def : NEONInstAlias<"vext${p}.16 $Vdn, $Vm, $imm",
5863 (VEXTq16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_7:$imm, pred:$p)>;
5864 def : NEONInstAlias<"vext${p}.32 $Vdn, $Vm, $imm",
5865 (VEXTq32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_3:$imm, pred:$p)>;
5866 def : NEONInstAlias<"vext${p}.64 $Vdn, $Vm, $imm",
5867 (VEXTq64 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, imm0_1:$imm, pred:$p)>;
5869 // Two-operand variants for VQDMULH
5870 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5871 (VQDMULHv4i16 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5872 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5873 (VQDMULHv2i32 DPR:$Vdn, DPR:$Vdn, DPR:$Vm, pred:$p)>;
5875 def : NEONInstAlias<"vqdmulh${p}.s16 $Vdn, $Vm",
5876 (VQDMULHv8i16 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5877 def : NEONInstAlias<"vqdmulh${p}.s32 $Vdn, $Vm",
5878 (VQDMULHv4i32 QPR:$Vdn, QPR:$Vdn, QPR:$Vm, pred:$p)>;
5880 // 'gas' compatibility aliases for quad-word instructions. Strictly speaking,
5881 // these should restrict to just the Q register variants, but the register
5882 // classes are enough to match correctly regardless, so we keep it simple
5883 // and just use MnemonicAlias.
5884 def : NEONMnemonicAlias<"vbicq", "vbic">;
5885 def : NEONMnemonicAlias<"vandq", "vand">;
5886 def : NEONMnemonicAlias<"veorq", "veor">;
5887 def : NEONMnemonicAlias<"vorrq", "vorr">;
5889 def : NEONMnemonicAlias<"vmovq", "vmov">;
5890 def : NEONMnemonicAlias<"vmvnq", "vmvn">;
5891 // Explicit versions for floating point so that the FPImm variants get
5892 // handled early. The parser gets confused otherwise.
5893 def : NEONMnemonicAlias<"vmovq.f32", "vmov.f32">;
5894 def : NEONMnemonicAlias<"vmovq.f64", "vmov.f64">;
5896 def : NEONMnemonicAlias<"vaddq", "vadd">;
5897 def : NEONMnemonicAlias<"vsubq", "vsub">;
5899 def : NEONMnemonicAlias<"vminq", "vmin">;
5900 def : NEONMnemonicAlias<"vmaxq", "vmax">;
5902 def : NEONMnemonicAlias<"vmulq", "vmul">;
5904 def : NEONMnemonicAlias<"vabsq", "vabs">;
5906 def : NEONMnemonicAlias<"vshlq", "vshl">;
5907 def : NEONMnemonicAlias<"vshrq", "vshr">;
5909 def : NEONMnemonicAlias<"vcvtq", "vcvt">;
5911 def : NEONMnemonicAlias<"vcleq", "vcle">;
5912 def : NEONMnemonicAlias<"vceqq", "vceq">;