1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : ImmLeaf<i32, [{
31 return Imm >= 0 && Imm < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; }
38 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
39 let ParserMatchClass = imm0_255_asmoperand;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : ImmLeaf<i32, [{
46 return Imm >= 8 && Imm < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift. This uses
54 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
55 // to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // ADR instruction labels.
71 def t_adrlabel : Operand<i32> {
72 let EncoderMethod = "getThumbAdrLabelOpValue";
75 // Scaled 4 immediate.
76 def t_imm_s4 : Operand<i32> {
77 let PrintMethod = "printThumbS4ImmOperand";
80 // Define Thumb specific addressing modes.
82 def t_brtarget : Operand<OtherVT> {
83 let EncoderMethod = "getThumbBRTargetOpValue";
86 def t_bcctarget : Operand<i32> {
87 let EncoderMethod = "getThumbBCCTargetOpValue";
90 def t_cbtarget : Operand<i32> {
91 let EncoderMethod = "getThumbCBTargetOpValue";
94 def t_bltarget : Operand<i32> {
95 let EncoderMethod = "getThumbBLTargetOpValue";
98 def t_blxtarget : Operand<i32> {
99 let EncoderMethod = "getThumbBLXTargetOpValue";
102 def MemModeRegThumbAsmOperand : AsmOperandClass {
103 let Name = "MemModeRegThumb";
104 let SuperClasses = [];
107 def MemModeImmThumbAsmOperand : AsmOperandClass {
108 let Name = "MemModeImmThumb";
109 let SuperClasses = [];
112 // t_addrmode_rr := reg + reg
114 def t_addrmode_rr : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
116 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
117 let PrintMethod = "printThumbAddrModeRROperand";
118 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
121 // t_addrmode_rrs := reg + reg
123 def t_addrmode_rrs1 : Operand<i32>,
124 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
125 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
126 let PrintMethod = "printThumbAddrModeRROperand";
127 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
128 let ParserMatchClass = MemModeRegThumbAsmOperand;
130 def t_addrmode_rrs2 : Operand<i32>,
131 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
132 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
133 let PrintMethod = "printThumbAddrModeRROperand";
134 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
135 let ParserMatchClass = MemModeRegThumbAsmOperand;
137 def t_addrmode_rrs4 : Operand<i32>,
138 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
139 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
140 let PrintMethod = "printThumbAddrModeRROperand";
141 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
142 let ParserMatchClass = MemModeRegThumbAsmOperand;
145 // t_addrmode_is4 := reg + imm5 * 4
147 def t_addrmode_is4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
149 let EncoderMethod = "getAddrModeISOpValue";
150 let PrintMethod = "printThumbAddrModeImm5S4Operand";
151 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
152 let ParserMatchClass = MemModeImmThumbAsmOperand;
155 // t_addrmode_is2 := reg + imm5 * 2
157 def t_addrmode_is2 : Operand<i32>,
158 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
159 let EncoderMethod = "getAddrModeISOpValue";
160 let PrintMethod = "printThumbAddrModeImm5S2Operand";
161 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
162 let ParserMatchClass = MemModeImmThumbAsmOperand;
165 // t_addrmode_is1 := reg + imm5
167 def t_addrmode_is1 : Operand<i32>,
168 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
169 let EncoderMethod = "getAddrModeISOpValue";
170 let PrintMethod = "printThumbAddrModeImm5S1Operand";
171 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
172 let ParserMatchClass = MemModeImmThumbAsmOperand;
175 // t_addrmode_sp := sp + imm8 * 4
177 def t_addrmode_sp : Operand<i32>,
178 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
179 let EncoderMethod = "getAddrModeThumbSPOpValue";
180 let PrintMethod = "printThumbAddrModeSPOperand";
181 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
182 let ParserMatchClass = MemModeImmThumbAsmOperand;
185 // t_addrmode_pc := <label> => pc + imm8 * 4
187 def t_addrmode_pc : Operand<i32> {
188 let EncoderMethod = "getAddrModePCOpValue";
189 let ParserMatchClass = MemModeImmThumbAsmOperand;
192 //===----------------------------------------------------------------------===//
193 // Miscellaneous Instructions.
196 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
197 // from removing one half of the matched pairs. That breaks PEI, which assumes
198 // these will always be in pairs, and asserts if it finds otherwise. Better way?
199 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
200 def tADJCALLSTACKUP :
201 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
202 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
203 Requires<[IsThumb, IsThumb1Only]>;
205 def tADJCALLSTACKDOWN :
206 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
207 [(ARMcallseq_start imm:$amt)]>,
208 Requires<[IsThumb, IsThumb1Only]>;
211 // T1Disassembly - A simple class to make encoding some disassembly patterns
212 // easier and less verbose.
213 class T1Disassembly<bits<2> op1, bits<8> op2>
214 : T1Encoding<0b101111> {
219 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
220 [/* For disassembly only; pattern left blank */]>,
221 T1Disassembly<0b11, 0x00>; // A8.6.110
223 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
224 [/* For disassembly only; pattern left blank */]>,
225 T1Disassembly<0b11, 0x10>; // A8.6.410
227 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
228 [/* For disassembly only; pattern left blank */]>,
229 T1Disassembly<0b11, 0x20>; // A8.6.408
231 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
232 [/* For disassembly only; pattern left blank */]>,
233 T1Disassembly<0b11, 0x30>; // A8.6.409
235 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
236 [/* For disassembly only; pattern left blank */]>,
237 T1Disassembly<0b11, 0x40>; // A8.6.157
239 // The i32imm operand $val can be used by a debugger to store more information
240 // about the breakpoint.
241 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
242 [/* For disassembly only; pattern left blank */]>,
243 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
249 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
250 [/* For disassembly only; pattern left blank */]>,
251 T1Encoding<0b101101> {
253 let Inst{9-5} = 0b10010;
255 let Inst{3} = 1; // Big-Endian
256 let Inst{2-0} = 0b000;
259 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
260 [/* For disassembly only; pattern left blank */]>,
261 T1Encoding<0b101101> {
263 let Inst{9-5} = 0b10010;
265 let Inst{3} = 0; // Little-Endian
266 let Inst{2-0} = 0b000;
269 // Change Processor State is a system instruction -- for disassembly only.
270 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
271 NoItinerary, "cps$imod $iflags",
272 [/* For disassembly only; pattern left blank */]>,
280 let Inst{2-0} = iflags;
283 // For both thumb1 and thumb2.
284 let isNotDuplicable = 1, isCodeGenOnly = 1 in
285 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
286 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
287 T1Special<{0,0,?,?}> {
290 let Inst{6-3} = 0b1111; // Rm = pc
294 // PC relative add (ADR).
295 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
296 "add\t$dst, pc, $rhs", []>,
297 T1Encoding<{1,0,1,0,0,?}> {
301 let Inst{10-8} = dst;
305 // ADD <Rd>, sp, #<imm8>
306 // This is rematerializable, which is particularly useful for taking the
307 // address of locals.
308 let isReMaterializable = 1 in
309 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
310 "add\t$dst, $sp, $rhs", []>,
311 T1Encoding<{1,0,1,0,1,?}> {
315 let Inst{10-8} = dst;
319 // ADD sp, sp, #<imm7>
320 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
321 "add\t$dst, $rhs", []>,
322 T1Misc<{0,0,0,0,0,?,?}> {
328 // SUB sp, sp, #<imm7>
329 // FIXME: The encoding and the ASM string don't match up.
330 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
331 "sub\t$dst, $rhs", []>,
332 T1Misc<{0,0,0,0,1,?,?}> {
339 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
340 "add\t$dst, $rhs", []>,
341 T1Special<{0,0,?,?}> {
342 // A8.6.9 Encoding T1
344 let Inst{7} = dst{3};
345 let Inst{6-3} = 0b1101;
346 let Inst{2-0} = dst{2-0};
350 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
351 "add\t$dst, $rhs", []>,
352 T1Special<{0,0,?,?}> {
353 // A8.6.9 Encoding T2
357 let Inst{2-0} = 0b101;
360 //===----------------------------------------------------------------------===//
361 // Control Flow Instructions.
364 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
365 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
367 T1Special<{1,1,0,?}> {
369 let Inst{6-3} = 0b1110; // Rm = lr
370 let Inst{2-0} = 0b000;
373 // Alternative return instruction used by vararg functions.
374 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
377 T1Special<{1,1,0,?}> {
381 let Inst{2-0} = 0b000;
386 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
387 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
388 T1Special<{1,1,0,?}> {
392 let Inst{2-0} = 0b000;
395 def tBRIND : TI<(outs), (ins GPR:$Rm),
399 T1Special<{1,0,?,?}> {
402 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
404 let Inst{2-0} = 0b111;
408 // All calls clobber the non-callee saved registers. SP is marked as a use to
409 // prevent stack-pointer assignments that appear immediately before calls from
410 // potentially appearing dead.
412 // On non-Darwin platforms R9 is callee-saved.
413 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
415 // Also used for Thumb2
416 def tBL : TIx2<0b11110, 0b11, 1,
417 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
419 [(ARMtcall tglobaladdr:$func)]>,
420 Requires<[IsThumb, IsNotDarwin]> {
422 let Inst{25-16} = func{20-11};
425 let Inst{10-0} = func{10-0};
428 // ARMv5T and above, also used for Thumb2
429 def tBLXi : TIx2<0b11110, 0b11, 0,
430 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
432 [(ARMcall tglobaladdr:$func)]>,
433 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
435 let Inst{25-16} = func{20-11};
438 let Inst{10-1} = func{10-1};
439 let Inst{0} = 0; // func{0} is assumed zero
442 // Also used for Thumb2
443 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
445 [(ARMtcall GPR:$func)]>,
446 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
447 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
449 let Inst{6-3} = func;
450 let Inst{2-0} = 0b000;
454 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
456 [(ARMcall_nolink tGPR:$func)]>,
457 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
461 // On Darwin R9 is call-clobbered.
462 // R7 is marked as a use to prevent frame-pointer assignments from being
463 // moved above / below calls.
464 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
466 // Also used for Thumb2
467 def tBLr9 : TIx2<0b11110, 0b11, 1,
468 (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
469 IIC_Br, "bl${p}\t$func",
470 [(ARMtcall tglobaladdr:$func)]>,
471 Requires<[IsThumb, IsDarwin]> {
473 let Inst{25-16} = func{20-11};
476 let Inst{10-0} = func{10-0};
479 // ARMv5T and above, also used for Thumb2
480 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
481 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
482 IIC_Br, "blx${p}\t$func",
483 [(ARMcall tglobaladdr:$func)]>,
484 Requires<[IsThumb, HasV5T, IsDarwin]> {
486 let Inst{25-16} = func{20-11};
489 let Inst{10-1} = func{10-1};
490 let Inst{0} = 0; // func{0} is assumed zero
493 // Also used for Thumb2
494 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
496 [(ARMtcall GPR:$func)]>,
497 Requires<[IsThumb, HasV5T, IsDarwin]>,
498 T1Special<{1,1,1,?}> {
501 let Inst{6-3} = func;
502 let Inst{2-0} = 0b000;
506 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
508 [(ARMcall_nolink tGPR:$func)]>,
509 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
512 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
513 let isPredicable = 1 in
514 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
515 "b\t$target", [(br bb:$target)]>,
516 T1Encoding<{1,1,1,0,0,?}> {
518 let Inst{10-0} = target;
522 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
523 // the clobber of LR.
525 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target),
526 Size4Bytes, IIC_Br, [], (tBL t_bltarget:$target)>;
528 def tBR_JTr : tPseudoInst<(outs),
529 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
531 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
532 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
536 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
537 // a two-value operand where a dag node expects two operands. :(
538 let isBranch = 1, isTerminator = 1 in
539 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
541 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
542 T1BranchCond<{1,1,0,1}> {
546 let Inst{7-0} = target;
549 // Compare and branch on zero / non-zero
550 let isBranch = 1, isTerminator = 1 in {
551 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
552 "cbz\t$Rn, $target", []>,
553 T1Misc<{0,0,?,1,?,?,?}> {
557 let Inst{9} = target{5};
558 let Inst{7-3} = target{4-0};
562 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
563 "cbnz\t$cmp, $target", []>,
564 T1Misc<{1,0,?,1,?,?,?}> {
568 let Inst{9} = target{5};
569 let Inst{7-3} = target{4-0};
575 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
577 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
579 def tTAILJMPd: tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
581 []>, Requires<[IsThumb, IsDarwin]>;
582 def tTAILJMPr : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
584 []>, Requires<[IsThumb, IsDarwin]>;
586 // Non-Darwin versions (the difference is R9).
587 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
589 def tTAILJMPdND : tPseudoInst<(outs), (ins brtarget:$dst, variable_ops),
591 []>, Requires<[IsThumb, IsNotDarwin]>;
592 def tTAILJMPrND : tPseudoInst<(outs), (ins tcGPR:$dst, variable_ops),
594 []>, Requires<[IsThumb, IsNotDarwin]>;
599 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
600 // A8.6.16 B: Encoding T1
601 // If Inst{11-8} == 0b1111 then SEE SVC
602 let isCall = 1, Uses = [SP] in
603 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
604 "svc", "\t$imm", []>, Encoding16 {
606 let Inst{15-12} = 0b1101;
607 let Inst{11-8} = 0b1111;
611 // The assembler uses 0xDEFE for a trap instruction.
612 let isBarrier = 1, isTerminator = 1 in
613 def tTRAP : TI<(outs), (ins), IIC_Br,
614 "trap", [(trap)]>, Encoding16 {
618 //===----------------------------------------------------------------------===//
619 // Load Store Instructions.
622 // Loads: reg/reg and reg/imm5
623 let canFoldAsLoad = 1, isReMaterializable = 1 in
624 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
625 Operand AddrMode_r, Operand AddrMode_i,
626 AddrMode am, InstrItinClass itin_r,
627 InstrItinClass itin_i, string asm,
630 T1pILdStEncode<reg_opc,
631 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
632 am, itin_r, asm, "\t$Rt, $addr",
633 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
635 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
636 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
637 am, itin_i, asm, "\t$Rt, $addr",
638 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
640 // Stores: reg/reg and reg/imm5
641 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
642 Operand AddrMode_r, Operand AddrMode_i,
643 AddrMode am, InstrItinClass itin_r,
644 InstrItinClass itin_i, string asm,
647 T1pILdStEncode<reg_opc,
648 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
649 am, itin_r, asm, "\t$Rt, $addr",
650 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
652 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
653 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
654 am, itin_i, asm, "\t$Rt, $addr",
655 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
659 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
660 t_addrmode_is4, AddrModeT1_4,
661 IIC_iLoad_r, IIC_iLoad_i, "ldr",
662 UnOpFrag<(load node:$Src)>>;
665 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
666 t_addrmode_is1, AddrModeT1_1,
667 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
668 UnOpFrag<(zextloadi8 node:$Src)>>;
671 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
672 t_addrmode_is2, AddrModeT1_2,
673 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
674 UnOpFrag<(zextloadi16 node:$Src)>>;
676 let AddedComplexity = 10 in
677 def tLDRSB : // A8.6.80
678 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
679 AddrModeT1_1, IIC_iLoad_bh_r,
680 "ldrsb", "\t$dst, $addr",
681 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
683 let AddedComplexity = 10 in
684 def tLDRSH : // A8.6.84
685 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
686 AddrModeT1_2, IIC_iLoad_bh_r,
687 "ldrsh", "\t$dst, $addr",
688 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
690 let canFoldAsLoad = 1 in
691 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
692 "ldr", "\t$Rt, $addr",
693 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
698 let Inst{7-0} = addr;
702 // FIXME: Use ldr.n to work around a Darwin assembler bug.
703 let canFoldAsLoad = 1, isReMaterializable = 1 in
704 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
705 "ldr", ".n\t$Rt, $addr",
706 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
707 T1Encoding<{0,1,0,0,1,?}> {
712 let Inst{7-0} = addr;
715 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
716 // For disassembly use only.
717 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
718 "ldr", "\t$Rt, $addr",
719 [/* disassembly only */]>,
720 T1Encoding<{0,1,0,0,1,?}> {
725 let Inst{7-0} = addr;
728 // A8.6.194 & A8.6.192
729 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
730 t_addrmode_is4, AddrModeT1_4,
731 IIC_iStore_r, IIC_iStore_i, "str",
732 BinOpFrag<(store node:$LHS, node:$RHS)>>;
734 // A8.6.197 & A8.6.195
735 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
736 t_addrmode_is1, AddrModeT1_1,
737 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
738 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
740 // A8.6.207 & A8.6.205
741 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
742 t_addrmode_is2, AddrModeT1_2,
743 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
744 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
747 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
748 "str", "\t$Rt, $addr",
749 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
754 let Inst{7-0} = addr;
757 //===----------------------------------------------------------------------===//
758 // Load / store multiple Instructions.
761 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
762 InstrItinClass itin_upd, bits<6> T1Enc,
765 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
766 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
771 let Inst{7-0} = regs;
774 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
775 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
780 let Inst{7-0} = regs;
784 // These require base address to be written back or one of the loaded regs.
785 let neverHasSideEffects = 1 in {
787 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
788 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
791 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
792 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
795 } // neverHasSideEffects
797 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
798 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
800 "pop${p}\t$regs", []>,
801 T1Misc<{1,1,0,?,?,?,?}> {
803 let Inst{8} = regs{15};
804 let Inst{7-0} = regs{7-0};
807 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
808 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
810 "push${p}\t$regs", []>,
811 T1Misc<{0,1,0,?,?,?,?}> {
813 let Inst{8} = regs{14};
814 let Inst{7-0} = regs{7-0};
817 //===----------------------------------------------------------------------===//
818 // Arithmetic Instructions.
821 // Helper classes for encoding T1pI patterns:
822 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
823 string opc, string asm, list<dag> pattern>
824 : T1pI<oops, iops, itin, opc, asm, pattern>,
825 T1DataProcessing<opA> {
831 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
832 string opc, string asm, list<dag> pattern>
833 : T1pI<oops, iops, itin, opc, asm, pattern>,
841 // Helper classes for encoding T1sI patterns:
842 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
843 string opc, string asm, list<dag> pattern>
844 : T1sI<oops, iops, itin, opc, asm, pattern>,
845 T1DataProcessing<opA> {
851 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
852 string opc, string asm, list<dag> pattern>
853 : T1sI<oops, iops, itin, opc, asm, pattern>,
862 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
863 string opc, string asm, list<dag> pattern>
864 : T1sI<oops, iops, itin, opc, asm, pattern>,
872 // Helper classes for encoding T1sIt patterns:
873 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
874 string opc, string asm, list<dag> pattern>
875 : T1sIt<oops, iops, itin, opc, asm, pattern>,
876 T1DataProcessing<opA> {
882 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
883 string opc, string asm, list<dag> pattern>
884 : T1sIt<oops, iops, itin, opc, asm, pattern>,
888 let Inst{10-8} = Rdn;
889 let Inst{7-0} = imm8;
892 // Add with carry register
893 let isCommutable = 1, Uses = [CPSR] in
895 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
896 "adc", "\t$Rdn, $Rm",
897 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
900 def tADDi3 : // A8.6.4 T1
901 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
903 "add", "\t$Rd, $Rm, $imm3",
904 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
906 let Inst{8-6} = imm3;
909 def tADDi8 : // A8.6.4 T2
910 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
912 "add", "\t$Rdn, $imm8",
913 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
916 let isCommutable = 1 in
917 def tADDrr : // A8.6.6 T1
918 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
920 "add", "\t$Rd, $Rn, $Rm",
921 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
923 let neverHasSideEffects = 1 in
924 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
925 "add", "\t$Rdn, $Rm", []>,
926 T1Special<{0,0,?,?}> {
930 let Inst{7} = Rdn{3};
932 let Inst{2-0} = Rdn{2-0};
936 let isCommutable = 1 in
937 def tAND : // A8.6.12
938 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
940 "and", "\t$Rdn, $Rm",
941 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
944 def tASRri : // A8.6.14
945 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
947 "asr", "\t$Rd, $Rm, $imm5",
948 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
950 let Inst{10-6} = imm5;
954 def tASRrr : // A8.6.15
955 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
957 "asr", "\t$Rdn, $Rm",
958 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
961 def tBIC : // A8.6.20
962 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
964 "bic", "\t$Rdn, $Rm",
965 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
968 let isCompare = 1, Defs = [CPSR] in {
969 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
970 // Compare-to-zero still works out, just not the relationals
971 //def tCMN : // A8.6.33
972 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
974 // "cmn", "\t$lhs, $rhs",
975 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
977 def tCMNz : // A8.6.33
978 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
981 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
983 } // isCompare = 1, Defs = [CPSR]
986 let isCompare = 1, Defs = [CPSR] in {
987 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
988 "cmp", "\t$Rn, $imm8",
989 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
990 T1General<{1,0,1,?,?}> {
995 let Inst{7-0} = imm8;
999 def tCMPr : // A8.6.36 T1
1000 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1002 "cmp", "\t$Rn, $Rm",
1003 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
1005 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1006 "cmp", "\t$Rn, $Rm", []>,
1007 T1Special<{0,1,?,?}> {
1011 let Inst{7} = Rn{3};
1013 let Inst{2-0} = Rn{2-0};
1015 } // isCompare = 1, Defs = [CPSR]
1019 let isCommutable = 1 in
1020 def tEOR : // A8.6.45
1021 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1023 "eor", "\t$Rdn, $Rm",
1024 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1027 def tLSLri : // A8.6.88
1028 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1030 "lsl", "\t$Rd, $Rm, $imm5",
1031 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1033 let Inst{10-6} = imm5;
1037 def tLSLrr : // A8.6.89
1038 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1040 "lsl", "\t$Rdn, $Rm",
1041 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1044 def tLSRri : // A8.6.90
1045 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1047 "lsr", "\t$Rd, $Rm, $imm5",
1048 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1050 let Inst{10-6} = imm5;
1054 def tLSRrr : // A8.6.91
1055 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1057 "lsr", "\t$Rdn, $Rm",
1058 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1061 let isMoveImm = 1 in
1062 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1063 "mov", "\t$Rd, $imm8",
1064 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1065 T1General<{1,0,0,?,?}> {
1069 let Inst{10-8} = Rd;
1070 let Inst{7-0} = imm8;
1073 // A7-73: MOV(2) - mov setting flag.
1075 let neverHasSideEffects = 1 in {
1076 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1077 Size2Bytes, IIC_iMOVr,
1078 "mov", "\t$Rd, $Rm", "", []>,
1079 T1Special<{1,0,?,?}> {
1083 let Inst{7} = Rd{3};
1085 let Inst{2-0} = Rd{2-0};
1087 let Defs = [CPSR] in
1088 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1089 "movs\t$Rd, $Rm", []>, Encoding16 {
1093 let Inst{15-6} = 0b0000000000;
1097 } // neverHasSideEffects
1099 // Multiply register
1100 let isCommutable = 1 in
1101 def tMUL : // A8.6.105 T1
1102 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1104 "mul", "\t$Rdn, $Rm, $Rdn",
1105 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1107 // Move inverse register
1108 def tMVN : // A8.6.107
1109 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1110 "mvn", "\t$Rd, $Rn",
1111 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1113 // Bitwise or register
1114 let isCommutable = 1 in
1115 def tORR : // A8.6.114
1116 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1118 "orr", "\t$Rdn, $Rm",
1119 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1122 def tREV : // A8.6.134
1123 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1125 "rev", "\t$Rd, $Rm",
1126 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1127 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1129 def tREV16 : // A8.6.135
1130 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1132 "rev16", "\t$Rd, $Rm",
1133 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1134 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1136 def tREVSH : // A8.6.136
1137 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1139 "revsh", "\t$Rd, $Rm",
1140 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1141 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1143 // Rotate right register
1144 def tROR : // A8.6.139
1145 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1147 "ror", "\t$Rdn, $Rm",
1148 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1151 def tRSB : // A8.6.141
1152 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1154 "rsb", "\t$Rd, $Rn, #0",
1155 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1157 // Subtract with carry register
1158 let Uses = [CPSR] in
1159 def tSBC : // A8.6.151
1160 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1162 "sbc", "\t$Rdn, $Rm",
1163 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1165 // Subtract immediate
1166 def tSUBi3 : // A8.6.210 T1
1167 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1169 "sub", "\t$Rd, $Rm, $imm3",
1170 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1172 let Inst{8-6} = imm3;
1175 def tSUBi8 : // A8.6.210 T2
1176 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1178 "sub", "\t$Rdn, $imm8",
1179 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1181 // Subtract register
1182 def tSUBrr : // A8.6.212
1183 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1185 "sub", "\t$Rd, $Rn, $Rm",
1186 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1188 // TODO: A7-96: STMIA - store multiple.
1191 def tSXTB : // A8.6.222
1192 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1194 "sxtb", "\t$Rd, $Rm",
1195 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1196 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1198 // Sign-extend short
1199 def tSXTH : // A8.6.224
1200 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1202 "sxth", "\t$Rd, $Rm",
1203 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1204 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1207 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1208 def tTST : // A8.6.230
1209 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1210 "tst", "\t$Rn, $Rm",
1211 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1214 def tUXTB : // A8.6.262
1215 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1217 "uxtb", "\t$Rd, $Rm",
1218 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1219 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1221 // Zero-extend short
1222 def tUXTH : // A8.6.264
1223 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1225 "uxth", "\t$Rd, $Rm",
1226 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1227 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1229 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1230 // Expanded after instruction selection into a branch sequence.
1231 let usesCustomInserter = 1 in // Expanded after instruction selection.
1232 def tMOVCCr_pseudo :
1233 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1235 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1237 // tLEApcrel - Load a pc-relative address into a register without offending the
1240 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1241 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1242 T1Encoding<{1,0,1,0,0,?}> {
1245 let Inst{10-8} = Rd;
1246 let Inst{7-0} = addr;
1249 let neverHasSideEffects = 1, isReMaterializable = 1 in
1250 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1251 Size2Bytes, IIC_iALUi, []>;
1253 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1254 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1255 Size2Bytes, IIC_iALUi, []>;
1257 //===----------------------------------------------------------------------===//
1258 // Move between coprocessor and ARM core register -- for disassembly only
1261 class tMovRCopro<string opc, bit direction, dag oops, dag iops,
1263 : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1265 let Inst{27-24} = 0b1110;
1266 let Inst{20} = direction;
1276 let Inst{15-12} = Rt;
1277 let Inst{11-8} = cop;
1278 let Inst{23-21} = opc1;
1279 let Inst{7-5} = opc2;
1280 let Inst{3-0} = CRm;
1281 let Inst{19-16} = CRn;
1284 def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
1286 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
1287 c_imm:$CRm, i32imm:$opc2),
1288 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
1289 imm:$CRm, imm:$opc2)]>;
1290 def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
1292 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1295 def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
1296 (tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>,
1297 Requires<[IsThumb, HasV6T2]>;
1299 class tMovRRCopro<string opc, bit direction,
1300 list<dag> pattern = [/* For disassembly only */]>
1301 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1302 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
1303 let Inst{27-24} = 0b1100;
1304 let Inst{23-21} = 0b010;
1305 let Inst{20} = direction;
1313 let Inst{15-12} = Rt;
1314 let Inst{19-16} = Rt2;
1315 let Inst{11-8} = cop;
1316 let Inst{7-4} = opc1;
1317 let Inst{3-0} = CRm;
1320 def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
1321 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
1323 def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1325 //===----------------------------------------------------------------------===//
1326 // Other Coprocessor Instructions. For disassembly only.
1328 def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1329 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1330 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1331 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
1332 imm:$CRm, imm:$opc2)]> {
1333 let Inst{27-24} = 0b1110;
1342 let Inst{3-0} = CRm;
1344 let Inst{7-5} = opc2;
1345 let Inst{11-8} = cop;
1346 let Inst{15-12} = CRd;
1347 let Inst{19-16} = CRn;
1348 let Inst{23-20} = opc1;
1351 //===----------------------------------------------------------------------===//
1355 // __aeabi_read_tp preserves the registers r1-r3.
1356 // This is a pseudo inst so that we can get the encoding right,
1357 // complete with fixup for the aeabi_read_tp function.
1358 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1359 def tTPsoft : tPseudoInst<(outs), (ins), Size4Bytes, IIC_Br,
1360 [(set R0, ARMthread_pointer)]>;
1362 //===----------------------------------------------------------------------===//
1363 // SJLJ Exception handling intrinsics
1366 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1367 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1368 // from some other function to get here, and we're using the stack frame for the
1369 // containing function to save/restore registers, we can't keep anything live in
1370 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1371 // tromped upon when we get here from a longjmp(). We force everything out of
1372 // registers except for our own input by listing the relevant registers in
1373 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1374 // preserve all of the callee-saved resgisters, which is exactly what we want.
1375 // $val is a scratch register for our use.
1376 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1377 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1378 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1379 AddrModeNone, SizeSpecial, NoItinerary, "","",
1380 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1382 // FIXME: Non-Darwin version(s)
1383 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1384 Defs = [ R7, LR, SP ] in
1385 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1386 AddrModeNone, SizeSpecial, IndexModeNone,
1387 Pseudo, NoItinerary, "", "",
1388 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1389 Requires<[IsThumb, IsDarwin]>;
1391 //===----------------------------------------------------------------------===//
1392 // Non-Instruction Patterns
1396 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1397 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1398 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1399 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1402 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1403 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1404 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1405 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1406 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1407 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1409 // Subtract with carry
1410 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1411 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1412 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1413 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1414 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1415 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1417 // ConstantPool, GlobalAddress
1418 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1419 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1422 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1423 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1426 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1427 Requires<[IsThumb, IsNotDarwin]>;
1428 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1429 Requires<[IsThumb, IsDarwin]>;
1431 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1432 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1433 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1434 Requires<[IsThumb, HasV5T, IsDarwin]>;
1436 // Indirect calls to ARM routines
1437 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1438 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1439 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1440 Requires<[IsThumb, HasV5T, IsDarwin]>;
1442 // zextload i1 -> zextload i8
1443 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1444 (tLDRBr t_addrmode_rrs1:$addr)>;
1445 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1446 (tLDRBi t_addrmode_is1:$addr)>;
1448 // extload -> zextload
1449 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1450 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1451 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1452 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1453 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1454 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1456 // If it's impossible to use [r,r] address mode for sextload, select to
1457 // ldr{b|h} + sxt{b|h} instead.
1458 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1459 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1460 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1461 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1462 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1463 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1464 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1465 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1466 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1467 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1468 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1469 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1471 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1472 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1473 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1474 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1475 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1476 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1477 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1478 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1480 // Large immediate handling.
1483 def : T1Pat<(i32 thumb_immshifted:$src),
1484 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1485 (thumb_immshifted_shamt imm:$src))>;
1487 def : T1Pat<(i32 imm0_255_comp:$src),
1488 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1490 // Pseudo instruction that combines ldr from constpool and add pc. This should
1491 // be expanded into two instructions late to allow if-conversion and
1493 let isReMaterializable = 1 in
1494 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1496 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1498 Requires<[IsThumb, IsThumb1Only]>;
1500 // Pseudo-instruction for merged POP and return.
1501 // FIXME: remove when we have a way to marking a MI with these properties.
1502 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1503 hasExtraDefRegAllocReq = 1 in
1504 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1505 Size2Bytes, IIC_iPop_Br, [],
1506 (tPOP pred:$p, reglist:$regs)>;