1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, "",
130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
132 def tADJCALLSTACKDOWN :
133 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, "",
134 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
137 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
138 [/* For disassembly only; pattern left blank */]>,
139 T1Encoding<0b101111> {
140 let Inst{9-8} = 0b11;
141 let Inst{7-0} = 0b00000000;
144 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
145 [/* For disassembly only; pattern left blank */]>,
146 T1Encoding<0b101111> {
147 let Inst{9-8} = 0b11;
148 let Inst{7-0} = 0b00010000;
151 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
152 [/* For disassembly only; pattern left blank */]>,
153 T1Encoding<0b101111> {
154 let Inst{9-8} = 0b11;
155 let Inst{7-0} = 0b00100000;
158 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
159 [/* For disassembly only; pattern left blank */]>,
160 T1Encoding<0b101111> {
161 let Inst{9-8} = 0b11;
162 let Inst{7-0} = 0b00110000;
165 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
166 [/* For disassembly only; pattern left blank */]>,
167 T1Encoding<0b101111> {
168 let Inst{9-8} = 0b11;
169 let Inst{7-0} = 0b01000000;
172 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
173 [/* For disassembly only; pattern left blank */]>,
174 T1Encoding<0b101101> {
175 let Inst{9-5} = 0b10010;
179 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
180 [/* For disassembly only; pattern left blank */]>,
181 T1Encoding<0b101101> {
182 let Inst{9-5} = 0b10010;
186 // The i32imm operand $val can be used by a debugger to store more information
187 // about the breakpoint.
188 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
189 [/* For disassembly only; pattern left blank */]>,
190 T1Encoding<0b101111> {
191 let Inst{9-8} = 0b10;
194 // Change Processor State is a system instruction -- for disassembly only.
195 // The singleton $opt operand contains the following information:
196 // opt{4-0} = mode ==> don't care
197 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
198 // opt{8-6} = AIF from Inst{2-0}
199 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
201 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
202 // CPS which has more options.
203 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
204 [/* For disassembly only; pattern left blank */]>,
207 // For both thumb1 and thumb2.
208 let isNotDuplicable = 1, isCodeGenOnly = 1 in
209 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
210 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
211 T1Special<{0,0,?,?}> {
212 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
216 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
217 "add\t$dst, pc, $rhs", []>,
218 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
221 // This is rematerializable, which is particularly useful for taking the
222 // address of locals.
223 let isReMaterializable = 1 in {
224 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
225 "add\t$dst, $sp, $rhs", []>,
226 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
230 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
231 "add\t$dst, $rhs", []>,
232 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
235 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
236 "sub\t$dst, $rhs", []>,
237 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
240 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
241 "add\t$dst, $rhs", []>,
242 T1Special<{0,0,?,?}> {
243 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
247 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
248 "add\t$dst, $rhs", []>,
249 T1Special<{0,0,?,?}> {
250 // A8.6.9 Encoding T2
252 let Inst{2-0} = 0b101;
255 //===----------------------------------------------------------------------===//
256 // Control Flow Instructions.
259 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
260 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
261 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
262 let Inst{6-3} = 0b1110; // Rm = lr
264 // Alternative return instruction used by vararg functions.
265 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
266 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
270 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
271 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
273 T1Special<{1,0,1,?}> {
274 // <Rd> = Inst{7:2-0} = pc
275 let Inst{2-0} = 0b111;
279 // FIXME: remove when we have a way to marking a MI with these properties.
280 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
281 hasExtraDefRegAllocReq = 1 in
282 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops),
284 "pop${p}\t$dsts", []>,
285 T1Misc<{1,1,0,?,?,?,?}>;
288 Defs = [R0, R1, R2, R3, R12, LR,
289 D0, D1, D2, D3, D4, D5, D6, D7,
290 D16, D17, D18, D19, D20, D21, D22, D23,
291 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
292 // Also used for Thumb2
293 def tBL : TIx2<0b11110, 0b11, 1,
294 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
296 [(ARMtcall tglobaladdr:$func)]>,
297 Requires<[IsThumb, IsNotDarwin]>;
299 // ARMv5T and above, also used for Thumb2
300 def tBLXi : TIx2<0b11110, 0b11, 0,
301 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
303 [(ARMcall tglobaladdr:$func)]>,
304 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
306 // Also used for Thumb2
307 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
309 [(ARMtcall GPR:$func)]>,
310 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
311 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
314 let isCodeGenOnly = 1 in
315 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
316 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
317 "mov\tlr, pc\n\tbx\t$func",
318 [(ARMcall_nolink tGPR:$func)]>,
319 Requires<[IsThumb1Only, IsNotDarwin]>;
322 // On Darwin R9 is call-clobbered.
324 Defs = [R0, R1, R2, R3, R9, R12, LR,
325 D0, D1, D2, D3, D4, D5, D6, D7,
326 D16, D17, D18, D19, D20, D21, D22, D23,
327 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
328 // Also used for Thumb2
329 def tBLr9 : TIx2<0b11110, 0b11, 1,
330 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
332 [(ARMtcall tglobaladdr:$func)]>,
333 Requires<[IsThumb, IsDarwin]>;
335 // ARMv5T and above, also used for Thumb2
336 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
337 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
339 [(ARMcall tglobaladdr:$func)]>,
340 Requires<[IsThumb, HasV5T, IsDarwin]>;
342 // Also used for Thumb2
343 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
345 [(ARMtcall GPR:$func)]>,
346 Requires<[IsThumb, HasV5T, IsDarwin]>,
347 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
350 let isCodeGenOnly = 1 in
351 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
352 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
353 "mov\tlr, pc\n\tbx\t$func",
354 [(ARMcall_nolink tGPR:$func)]>,
355 Requires<[IsThumb1Only, IsDarwin]>;
358 let isBranch = 1, isTerminator = 1 in {
359 let isBarrier = 1 in {
360 let isPredicable = 1 in
361 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
362 "b\t$target", [(br bb:$target)]>,
363 T1Encoding<{1,1,1,0,0,?}>;
367 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
370 let isCodeGenOnly = 1 in
371 def tBR_JTr : T1JTI<(outs),
372 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
373 IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
374 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
376 let Inst{15-7} = 0b010001101;
377 let Inst{2-0} = 0b111;
382 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
383 // a two-value operand where a dag node expects two operands. :(
384 let isBranch = 1, isTerminator = 1 in
385 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
387 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
388 T1Encoding<{1,1,0,1,?,?}>;
390 // Compare and branch on zero / non-zero
391 let isBranch = 1, isTerminator = 1 in {
392 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
393 "cbz\t$cmp, $target", []>,
394 T1Misc<{0,0,?,1,?,?,?}>;
396 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
397 "cbnz\t$cmp, $target", []>,
398 T1Misc<{1,0,?,1,?,?,?}>;
401 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
402 // A8.6.16 B: Encoding T1
403 // If Inst{11-8} == 0b1111 then SEE SVC
405 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
407 let Inst{15-12} = 0b1101;
408 let Inst{11-8} = 0b1111;
412 // A8.6.16 B: Encoding T1
413 // If Inst{11-8} == 0b1110 then UNDEFINED
414 let isBarrier = 1, isTerminator = 1 in
415 def tTRAP : TI<(outs), (ins), IIC_Br,
416 "trap", [(trap)]>, Encoding16 {
417 let Inst{15-12} = 0b1101;
418 let Inst{11-8} = 0b1110;
421 //===----------------------------------------------------------------------===//
422 // Load Store Instructions.
425 let canFoldAsLoad = 1, isReMaterializable = 1 in
426 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
427 "ldr", "\t$dst, $addr",
428 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
430 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
431 "ldr", "\t$dst, $addr",
435 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
436 "ldrb", "\t$dst, $addr",
437 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
439 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
440 "ldrb", "\t$dst, $addr",
444 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
445 "ldrh", "\t$dst, $addr",
446 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
448 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
449 "ldrh", "\t$dst, $addr",
453 let AddedComplexity = 10 in
454 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
455 "ldrsb", "\t$dst, $addr",
456 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
459 let AddedComplexity = 10 in
460 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
461 "ldrsh", "\t$dst, $addr",
462 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
465 let canFoldAsLoad = 1 in
466 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
467 "ldr", "\t$dst, $addr",
468 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
471 // Special instruction for restore. It cannot clobber condition register
472 // when it's expanded by eliminateCallFramePseudoInstr().
473 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
474 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
475 "ldr", "\t$dst, $addr", []>,
479 // FIXME: Use ldr.n to work around a Darwin assembler bug.
480 let canFoldAsLoad = 1, isReMaterializable = 1 in
481 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
482 "ldr", ".n\t$dst, $addr",
483 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
484 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
486 // Special LDR for loads from non-pc-relative constpools.
487 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
488 isReMaterializable = 1 in
489 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
490 "ldr", "\t$dst, $addr", []>,
493 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
494 "str", "\t$src, $addr",
495 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
497 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
498 "str", "\t$src, $addr",
502 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
503 "strb", "\t$src, $addr",
504 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
506 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
507 "strb", "\t$src, $addr",
511 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
512 "strh", "\t$src, $addr",
513 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
515 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
516 "strh", "\t$src, $addr",
520 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
521 "str", "\t$src, $addr",
522 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
525 let mayStore = 1, neverHasSideEffects = 1 in {
526 // Special instruction for spill. It cannot clobber condition register
527 // when it's expanded by eliminateCallFramePseudoInstr().
528 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
529 "str", "\t$src, $addr", []>,
533 //===----------------------------------------------------------------------===//
534 // Load / store multiple Instructions.
537 // These require base address to be written back or one of the loaded regs.
538 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1,
539 isCodeGenOnly = 1 in {
540 def tLDM : T1I<(outs),
541 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
543 "ldm${addr:submode}${p}\t$addr, $dsts", []>,
544 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
546 def tLDM_UPD : T1It<(outs tGPR:$wb),
547 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
549 "ldm${addr:submode}${p}\t$addr!, $dsts",
550 "$addr.addr = $wb", []>,
551 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
552 } // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq
554 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1,
556 def tSTM_UPD : T1It<(outs tGPR:$wb),
557 (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops),
559 "stm${addr:submode}${p}\t$addr!, $srcs",
560 "$addr.addr = $wb", []>,
561 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
563 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
564 def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops),
566 "pop${p}\t$dsts", []>,
567 T1Misc<{1,1,0,?,?,?,?}>;
569 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
570 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops),
572 "push${p}\t$srcs", []>,
573 T1Misc<{0,1,0,?,?,?,?}>;
575 //===----------------------------------------------------------------------===//
576 // Arithmetic Instructions.
579 // Add with carry register
580 let isCommutable = 1, Uses = [CPSR] in
581 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
582 "adc", "\t$dst, $rhs",
583 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
584 T1DataProcessing<0b0101>;
587 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
588 "add", "\t$dst, $lhs, $rhs",
589 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
592 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
593 "add", "\t$dst, $rhs",
594 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
595 T1General<{1,1,0,?,?}>;
598 let isCommutable = 1 in
599 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
600 "add", "\t$dst, $lhs, $rhs",
601 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
604 let neverHasSideEffects = 1 in
605 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
606 "add", "\t$dst, $rhs", []>,
607 T1Special<{0,0,?,?}>;
610 let isCommutable = 1 in
611 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
612 "and", "\t$dst, $rhs",
613 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
614 T1DataProcessing<0b0000>;
617 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
618 "asr", "\t$dst, $lhs, $rhs",
619 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
620 T1General<{0,1,0,?,?}>;
623 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
624 "asr", "\t$dst, $rhs",
625 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
626 T1DataProcessing<0b0100>;
629 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
630 "bic", "\t$dst, $rhs",
631 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
632 T1DataProcessing<0b1110>;
635 let isCompare = 1, Defs = [CPSR] in {
636 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
637 // Compare-to-zero still works out, just not the relationals
638 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
639 // "cmn", "\t$lhs, $rhs",
640 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
641 // T1DataProcessing<0b1011>;
642 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
643 "cmn", "\t$lhs, $rhs",
644 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
645 T1DataProcessing<0b1011>;
649 let isCompare = 1, Defs = [CPSR] in {
650 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
651 "cmp", "\t$lhs, $rhs",
652 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
653 T1General<{1,0,1,?,?}>;
654 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
655 "cmp", "\t$lhs, $rhs",
656 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
657 T1General<{1,0,1,?,?}>;
661 let isCompare = 1, Defs = [CPSR] in {
662 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
663 "cmp", "\t$lhs, $rhs",
664 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
665 T1DataProcessing<0b1010>;
666 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
667 "cmp", "\t$lhs, $rhs",
668 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
669 T1DataProcessing<0b1010>;
671 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
672 "cmp", "\t$lhs, $rhs", []>,
673 T1Special<{0,1,?,?}>;
674 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
675 "cmp", "\t$lhs, $rhs", []>,
676 T1Special<{0,1,?,?}>;
681 let isCommutable = 1 in
682 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
683 "eor", "\t$dst, $rhs",
684 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
685 T1DataProcessing<0b0001>;
688 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
689 "lsl", "\t$dst, $lhs, $rhs",
690 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
691 T1General<{0,0,0,?,?}>;
694 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
695 "lsl", "\t$dst, $rhs",
696 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
697 T1DataProcessing<0b0010>;
700 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
701 "lsr", "\t$dst, $lhs, $rhs",
702 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
703 T1General<{0,0,1,?,?}>;
706 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
707 "lsr", "\t$dst, $rhs",
708 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
709 T1DataProcessing<0b0011>;
712 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
713 "mov", "\t$dst, $src",
714 [(set tGPR:$dst, imm0_255:$src)]>,
715 T1General<{1,0,0,?,?}>;
717 // TODO: A7-73: MOV(2) - mov setting flag.
720 let neverHasSideEffects = 1 in {
721 // FIXME: Make this predicable.
722 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
723 "mov\t$dst, $src", []>,
726 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
727 "movs\t$dst, $src", []>, Encoding16 {
728 let Inst{15-6} = 0b0000000000;
731 // FIXME: Make these predicable.
732 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
733 "mov\t$dst, $src", []>,
734 T1Special<{1,0,0,?}>;
735 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
736 "mov\t$dst, $src", []>,
737 T1Special<{1,0,?,0}>;
738 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
739 "mov\t$dst, $src", []>,
740 T1Special<{1,0,?,?}>;
741 } // neverHasSideEffects
744 let isCommutable = 1 in
745 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
746 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
747 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
748 T1DataProcessing<0b1101>;
750 // move inverse register
751 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMVNr,
752 "mvn", "\t$dst, $src",
753 [(set tGPR:$dst, (not tGPR:$src))]>,
754 T1DataProcessing<0b1111>;
756 // bitwise or register
757 let isCommutable = 1 in
758 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
759 "orr", "\t$dst, $rhs",
760 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
761 T1DataProcessing<0b1100>;
764 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
765 "rev", "\t$dst, $src",
766 [(set tGPR:$dst, (bswap tGPR:$src))]>,
767 Requires<[IsThumb1Only, HasV6]>,
768 T1Misc<{1,0,1,0,0,0,?}>;
770 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
771 "rev16", "\t$dst, $src",
773 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
774 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
775 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
776 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
777 Requires<[IsThumb1Only, HasV6]>,
778 T1Misc<{1,0,1,0,0,1,?}>;
780 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
781 "revsh", "\t$dst, $src",
784 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
785 (shl tGPR:$src, (i32 8))), i16))]>,
786 Requires<[IsThumb1Only, HasV6]>,
787 T1Misc<{1,0,1,0,1,1,?}>;
789 // rotate right register
790 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
791 "ror", "\t$dst, $rhs",
792 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
793 T1DataProcessing<0b0111>;
796 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
797 "rsb", "\t$dst, $src, #0",
798 [(set tGPR:$dst, (ineg tGPR:$src))]>,
799 T1DataProcessing<0b1001>;
801 // Subtract with carry register
803 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
804 "sbc", "\t$dst, $rhs",
805 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
806 T1DataProcessing<0b0110>;
808 // Subtract immediate
809 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
810 "sub", "\t$dst, $lhs, $rhs",
811 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
814 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
815 "sub", "\t$dst, $rhs",
816 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
817 T1General<{1,1,1,?,?}>;
820 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
821 "sub", "\t$dst, $lhs, $rhs",
822 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
825 // TODO: A7-96: STMIA - store multiple.
828 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
829 "sxtb", "\t$dst, $src",
830 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
831 Requires<[IsThumb1Only, HasV6]>,
832 T1Misc<{0,0,1,0,0,1,?}>;
835 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
836 "sxth", "\t$dst, $src",
837 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
838 Requires<[IsThumb1Only, HasV6]>,
839 T1Misc<{0,0,1,0,0,0,?}>;
842 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
843 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iTSTr,
844 "tst", "\t$lhs, $rhs",
845 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
846 T1DataProcessing<0b1000>;
849 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
850 "uxtb", "\t$dst, $src",
851 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
852 Requires<[IsThumb1Only, HasV6]>,
853 T1Misc<{0,0,1,0,1,1,?}>;
856 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
857 "uxth", "\t$dst, $src",
858 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
859 Requires<[IsThumb1Only, HasV6]>,
860 T1Misc<{0,0,1,0,1,0,?}>;
863 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
864 // Expanded after instruction selection into a branch sequence.
865 let usesCustomInserter = 1 in // Expanded after instruction selection.
867 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
869 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
872 // 16-bit movcc in IT blocks for Thumb2.
873 let neverHasSideEffects = 1 in {
874 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
875 "mov", "\t$dst, $rhs", []>,
876 T1Special<{1,0,?,?}>;
878 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
879 "mov", "\t$dst, $rhs", []>,
880 T1General<{1,0,0,?,?}>;
881 } // neverHasSideEffects
883 // tLEApcrel - Load a pc-relative address into a register without offending the
885 let neverHasSideEffects = 1 in {
886 let isReMaterializable = 1 in
887 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
888 "adr$p\t$dst, #$label", []>,
889 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
891 } // neverHasSideEffects
892 def tLEApcrelJT : T1I<(outs tGPR:$dst),
893 (ins i32imm:$label, nohash_imm:$id, pred:$p),
894 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
895 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
897 //===----------------------------------------------------------------------===//
901 // __aeabi_read_tp preserves the registers r1-r3.
904 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
905 "bl\t__aeabi_read_tp",
906 [(set R0, ARMthread_pointer)]>;
909 // SJLJ Exception handling intrinsics
910 // eh_sjlj_setjmp() is an instruction sequence to store the return
911 // address and save #0 in R0 for the non-longjmp case.
912 // Since by its nature we may be coming from some other function to get
913 // here, and we're using the stack frame for the containing function to
914 // save/restore registers, we can't keep anything live in regs across
915 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
916 // when we get here from a longjmp(). We force everthing out of registers
917 // except for our own input by listing the relevant registers in Defs. By
918 // doing so, we also cause the prologue/epilogue code to actively preserve
919 // all of the callee-saved resgisters, which is exactly what we want.
920 // $val is a scratch register for our use.
922 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
923 isBarrier = 1, isCodeGenOnly = 1 in {
924 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
925 AddrModeNone, SizeSpecial, NoItinerary, "", "",
926 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
929 // FIXME: Non-Darwin version(s)
930 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
931 Defs = [ R7, LR, SP ] in {
932 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
933 AddrModeNone, SizeSpecial, IndexModeNone,
934 Pseudo, NoItinerary, "", "",
935 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
936 Requires<[IsThumb, IsDarwin]>;
939 //===----------------------------------------------------------------------===//
940 // Non-Instruction Patterns
944 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
945 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
946 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
947 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
948 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
949 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
951 // Subtract with carry
952 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
953 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
954 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
955 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
956 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
957 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
959 // ConstantPool, GlobalAddress
960 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
961 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
964 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
965 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
968 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
969 Requires<[IsThumb, IsNotDarwin]>;
970 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
971 Requires<[IsThumb, IsDarwin]>;
973 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
974 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
975 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
976 Requires<[IsThumb, HasV5T, IsDarwin]>;
978 // Indirect calls to ARM routines
979 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
980 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
981 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
982 Requires<[IsThumb, HasV5T, IsDarwin]>;
984 // zextload i1 -> zextload i8
985 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
986 (tLDRB t_addrmode_s1:$addr)>;
988 // extload -> zextload
989 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
990 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
991 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
993 // If it's impossible to use [r,r] address mode for sextload, select to
994 // ldr{b|h} + sxt{b|h} instead.
995 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
996 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
997 Requires<[IsThumb1Only, HasV6]>;
998 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
999 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1000 Requires<[IsThumb1Only, HasV6]>;
1002 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1003 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1004 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1005 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1007 // Large immediate handling.
1010 def : T1Pat<(i32 thumb_immshifted:$src),
1011 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1012 (thumb_immshifted_shamt imm:$src))>;
1014 def : T1Pat<(i32 imm0_255_comp:$src),
1015 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1017 // Pseudo instruction that combines ldr from constpool and add pc. This should
1018 // be expanded into two instructions late to allow if-conversion and
1020 let isReMaterializable = 1 in
1021 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1023 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1025 Requires<[IsThumb1Only]>;