1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
126 // t_addrmode_rrs := reg + reg
128 def t_addrmode_rrs1 : Operand<i32>,
129 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
130 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
131 let PrintMethod = "printThumbAddrModeRROperand";
132 let DecoderMethod = "DecodeThumbAddrModeRR";
133 let ParserMatchClass = t_addrmode_rr_asm_operand;
134 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
136 def t_addrmode_rrs2 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
138 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139 let DecoderMethod = "DecodeThumbAddrModeRR";
140 let PrintMethod = "printThumbAddrModeRROperand";
141 let ParserMatchClass = t_addrmode_rr_asm_operand;
142 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
144 def t_addrmode_rrs4 : Operand<i32>,
145 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
146 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
147 let DecoderMethod = "DecodeThumbAddrModeRR";
148 let PrintMethod = "printThumbAddrModeRROperand";
149 let ParserMatchClass = t_addrmode_rr_asm_operand;
150 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
153 // t_addrmode_is4 := reg + imm5 * 4
155 def t_addrmode_is4 : Operand<i32>,
156 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
157 let EncoderMethod = "getAddrModeISOpValue";
158 let DecoderMethod = "DecodeThumbAddrModeIS";
159 let PrintMethod = "printThumbAddrModeImm5S4Operand";
160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
163 // t_addrmode_is2 := reg + imm5 * 2
165 def t_addrmode_is2 : Operand<i32>,
166 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
167 let EncoderMethod = "getAddrModeISOpValue";
168 let DecoderMethod = "DecodeThumbAddrModeIS";
169 let PrintMethod = "printThumbAddrModeImm5S2Operand";
170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
173 // t_addrmode_is1 := reg + imm5
175 def t_addrmode_is1 : Operand<i32>,
176 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
177 let EncoderMethod = "getAddrModeISOpValue";
178 let DecoderMethod = "DecodeThumbAddrModeIS";
179 let PrintMethod = "printThumbAddrModeImm5S1Operand";
180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
183 // t_addrmode_sp := sp + imm8 * 4
185 def t_addrmode_sp : Operand<i32>,
186 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
187 let EncoderMethod = "getAddrModeThumbSPOpValue";
188 let DecoderMethod = "DecodeThumbAddrModeSP";
189 let PrintMethod = "printThumbAddrModeSPOperand";
190 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
193 // t_addrmode_pc := <label> => pc + imm8 * 4
195 def t_addrmode_pc : Operand<i32> {
196 let EncoderMethod = "getAddrModePCOpValue";
197 let DecoderMethod = "DecodeThumbAddrModePC";
200 //===----------------------------------------------------------------------===//
201 // Miscellaneous Instructions.
204 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
205 // from removing one half of the matched pairs. That breaks PEI, which assumes
206 // these will always be in pairs, and asserts if it finds otherwise. Better way?
207 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
208 def tADJCALLSTACKUP :
209 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
210 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
211 Requires<[IsThumb, IsThumb1Only]>;
213 def tADJCALLSTACKDOWN :
214 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
215 [(ARMcallseq_start imm:$amt)]>,
216 Requires<[IsThumb, IsThumb1Only]>;
219 // T1Disassembly - A simple class to make encoding some disassembly patterns
220 // easier and less verbose.
221 class T1Disassembly<bits<2> op1, bits<8> op2>
222 : T1Encoding<0b101111> {
227 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
228 [/* For disassembly only; pattern left blank */]>,
229 T1Disassembly<0b11, 0x00>; // A8.6.110
231 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
232 [/* For disassembly only; pattern left blank */]>,
233 T1Disassembly<0b11, 0x10>; // A8.6.410
235 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
236 [/* For disassembly only; pattern left blank */]>,
237 T1Disassembly<0b11, 0x20>; // A8.6.408
239 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
240 [/* For disassembly only; pattern left blank */]>,
241 T1Disassembly<0b11, 0x30>; // A8.6.409
243 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
244 [/* For disassembly only; pattern left blank */]>,
245 T1Disassembly<0b11, 0x40>; // A8.6.157
247 // The i32imm operand $val can be used by a debugger to store more information
248 // about the breakpoint.
249 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
250 [/* For disassembly only; pattern left blank */]>,
251 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
257 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
258 []>, T1Encoding<0b101101> {
261 let Inst{9-5} = 0b10010;
264 let Inst{2-0} = 0b000;
267 // Change Processor State is a system instruction -- for disassembly only.
268 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
269 NoItinerary, "cps$imod $iflags",
270 [/* For disassembly only; pattern left blank */]>,
278 let Inst{2-0} = iflags;
279 let DecoderMethod = "DecodeThumbCPS";
282 // For both thumb1 and thumb2.
283 let isNotDuplicable = 1, isCodeGenOnly = 1 in
284 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
285 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
286 T1Special<{0,0,?,?}> {
289 let Inst{6-3} = 0b1111; // Rm = pc
293 // ADD <Rd>, sp, #<imm8>
294 // This is rematerializable, which is particularly useful for taking the
295 // address of locals.
296 let isReMaterializable = 1 in
297 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
298 "add\t$dst, $sp, $rhs", []>,
299 T1Encoding<{1,0,1,0,1,?}> {
303 let Inst{10-8} = dst;
305 let DecoderMethod = "DecodeThumbAddSpecialReg";
308 // ADD sp, sp, #<imm7>
309 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
310 "add\t$dst, $rhs", []>,
311 T1Misc<{0,0,0,0,0,?,?}> {
315 let DecoderMethod = "DecodeThumbAddSPImm";
318 // SUB sp, sp, #<imm7>
319 // FIXME: The encoding and the ASM string don't match up.
320 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
321 "sub\t$dst, $rhs", []>,
322 T1Misc<{0,0,0,0,1,?,?}> {
326 let DecoderMethod = "DecodeThumbAddSPImm";
330 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
331 "add\t$dst, $rhs", []>,
332 T1Special<{0,0,?,?}> {
333 // A8.6.9 Encoding T1
335 let Inst{7} = dst{3};
336 let Inst{6-3} = 0b1101;
337 let Inst{2-0} = dst{2-0};
338 let DecoderMethod = "DecodeThumbAddSPReg";
342 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
343 "add\t$dst, $rhs", []>,
344 T1Special<{0,0,?,?}> {
345 // A8.6.9 Encoding T2
349 let Inst{2-0} = 0b101;
350 let DecoderMethod = "DecodeThumbAddSPReg";
353 //===----------------------------------------------------------------------===//
354 // Control Flow Instructions.
358 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
359 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
360 T1Special<{1,1,0,?}> {
364 let Inst{2-0} = 0b000;
368 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
369 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
370 [(ARMretflag)], (tBX LR, pred:$p)>;
372 // Alternative return instruction used by vararg functions.
373 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
375 (tBX GPR:$Rm, pred:$p)>;
378 // All calls clobber the non-callee saved registers. SP is marked as a use to
379 // prevent stack-pointer assignments that appear immediately before calls from
380 // potentially appearing dead.
382 // On non-Darwin platforms R9 is callee-saved.
383 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
385 // Also used for Thumb2
386 def tBL : TIx2<0b11110, 0b11, 1,
387 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
389 [(ARMtcall tglobaladdr:$func)]>,
390 Requires<[IsThumb, IsNotDarwin]> {
392 let Inst{26} = func{21};
393 let Inst{25-16} = func{20-11};
396 let Inst{10-0} = func{10-0};
399 // ARMv5T and above, also used for Thumb2
400 def tBLXi : TIx2<0b11110, 0b11, 0,
401 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
403 [(ARMcall tglobaladdr:$func)]>,
404 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
406 let Inst{25-16} = func{20-11};
409 let Inst{10-1} = func{10-1};
410 let Inst{0} = 0; // func{0} is assumed zero
413 // Also used for Thumb2
414 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
416 [(ARMtcall GPR:$func)]>,
417 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
418 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
420 let Inst{6-3} = func;
421 let Inst{2-0} = 0b000;
425 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
427 [(ARMcall_nolink tGPR:$func)]>,
428 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
432 // On Darwin R9 is call-clobbered.
433 // R7 is marked as a use to prevent frame-pointer assignments from being
434 // moved above / below calls.
435 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
437 // Also used for Thumb2
438 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
439 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
440 (tBL pred:$p, t_bltarget:$func)>,
441 Requires<[IsThumb, IsDarwin]>;
443 // ARMv5T and above, also used for Thumb2
444 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
445 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
446 (tBLXi pred:$p, t_blxtarget:$func)>,
447 Requires<[IsThumb, HasV5T, IsDarwin]>;
449 // Also used for Thumb2
450 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
451 2, IIC_Br, [(ARMtcall GPR:$func)],
452 (tBLXr pred:$p, GPR:$func)>,
453 Requires<[IsThumb, HasV5T, IsDarwin]>;
456 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
458 [(ARMcall_nolink tGPR:$func)]>,
459 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
462 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
463 let isPredicable = 1 in
464 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
465 "b\t$target", [(br bb:$target)]>,
466 T1Encoding<{1,1,1,0,0,?}> {
468 let Inst{10-0} = target;
472 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
473 // the clobber of LR.
475 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
476 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
478 def tBR_JTr : tPseudoInst<(outs),
479 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
481 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
482 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
486 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
487 // a two-value operand where a dag node expects two operands. :(
488 let isBranch = 1, isTerminator = 1 in
489 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
491 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
492 T1BranchCond<{1,1,0,1}> {
496 let Inst{7-0} = target;
499 // Compare and branch on zero / non-zero
500 let isBranch = 1, isTerminator = 1 in {
501 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
502 "cbz\t$Rn, $target", []>,
503 T1Misc<{0,0,?,1,?,?,?}> {
507 let Inst{9} = target{5};
508 let Inst{7-3} = target{4-0};
512 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
513 "cbnz\t$Rn, $target", []>,
514 T1Misc<{1,0,?,1,?,?,?}> {
518 let Inst{9} = target{5};
519 let Inst{7-3} = target{4-0};
525 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
527 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
529 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
530 // on Darwin), so it's in ARMInstrThumb2.td.
531 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
533 (tBX GPR:$dst, (ops 14, zero_reg))>,
534 Requires<[IsThumb, IsDarwin]>;
536 // Non-Darwin versions (the difference is R9).
537 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
539 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
541 (tB t_brtarget:$dst)>,
542 Requires<[IsThumb, IsNotDarwin]>;
543 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
545 (tBX GPR:$dst, (ops 14, zero_reg))>,
546 Requires<[IsThumb, IsNotDarwin]>;
551 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
552 // A8.6.16 B: Encoding T1
553 // If Inst{11-8} == 0b1111 then SEE SVC
554 let isCall = 1, Uses = [SP] in
555 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
556 "svc", "\t$imm", []>, Encoding16 {
558 let Inst{15-12} = 0b1101;
559 let Inst{11-8} = 0b1111;
563 // The assembler uses 0xDEFE for a trap instruction.
564 let isBarrier = 1, isTerminator = 1 in
565 def tTRAP : TI<(outs), (ins), IIC_Br,
566 "trap", [(trap)]>, Encoding16 {
570 //===----------------------------------------------------------------------===//
571 // Load Store Instructions.
574 // Loads: reg/reg and reg/imm5
575 let canFoldAsLoad = 1, isReMaterializable = 1 in
576 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
577 Operand AddrMode_r, Operand AddrMode_i,
578 AddrMode am, InstrItinClass itin_r,
579 InstrItinClass itin_i, string asm,
582 T1pILdStEncode<reg_opc,
583 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
584 am, itin_r, asm, "\t$Rt, $addr",
585 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
587 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
588 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
589 am, itin_i, asm, "\t$Rt, $addr",
590 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
592 // Stores: reg/reg and reg/imm5
593 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
594 Operand AddrMode_r, Operand AddrMode_i,
595 AddrMode am, InstrItinClass itin_r,
596 InstrItinClass itin_i, string asm,
599 T1pILdStEncode<reg_opc,
600 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
601 am, itin_r, asm, "\t$Rt, $addr",
602 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
604 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
605 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
606 am, itin_i, asm, "\t$Rt, $addr",
607 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
611 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
612 t_addrmode_is4, AddrModeT1_4,
613 IIC_iLoad_r, IIC_iLoad_i, "ldr",
614 UnOpFrag<(load node:$Src)>>;
617 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
618 t_addrmode_is1, AddrModeT1_1,
619 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
620 UnOpFrag<(zextloadi8 node:$Src)>>;
623 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
624 t_addrmode_is2, AddrModeT1_2,
625 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
626 UnOpFrag<(zextloadi16 node:$Src)>>;
628 let AddedComplexity = 10 in
629 def tLDRSB : // A8.6.80
630 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
631 AddrModeT1_1, IIC_iLoad_bh_r,
632 "ldrsb", "\t$Rt, $addr",
633 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
635 let AddedComplexity = 10 in
636 def tLDRSH : // A8.6.84
637 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
638 AddrModeT1_2, IIC_iLoad_bh_r,
639 "ldrsh", "\t$Rt, $addr",
640 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
642 let canFoldAsLoad = 1 in
643 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
644 "ldr", "\t$Rt, $addr",
645 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
650 let Inst{7-0} = addr;
654 // FIXME: Use ldr.n to work around a Darwin assembler bug.
655 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
656 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
657 "ldr", ".n\t$Rt, $addr",
658 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
659 T1Encoding<{0,1,0,0,1,?}> {
664 let Inst{7-0} = addr;
667 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
668 // For disassembly use only.
669 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
670 "ldr", "\t$Rt, $addr",
671 [/* disassembly only */]>,
672 T1Encoding<{0,1,0,0,1,?}> {
677 let Inst{7-0} = addr;
680 // A8.6.194 & A8.6.192
681 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
682 t_addrmode_is4, AddrModeT1_4,
683 IIC_iStore_r, IIC_iStore_i, "str",
684 BinOpFrag<(store node:$LHS, node:$RHS)>>;
686 // A8.6.197 & A8.6.195
687 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
688 t_addrmode_is1, AddrModeT1_1,
689 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
690 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
692 // A8.6.207 & A8.6.205
693 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
694 t_addrmode_is2, AddrModeT1_2,
695 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
696 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
699 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
700 "str", "\t$Rt, $addr",
701 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
706 let Inst{7-0} = addr;
709 //===----------------------------------------------------------------------===//
710 // Load / store multiple Instructions.
713 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
714 InstrItinClass itin_upd, bits<6> T1Enc,
715 bit L_bit, string baseOpc> {
717 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
718 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
723 let Inst{7-0} = regs;
727 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
728 "$Rn = $wb", itin_upd>,
729 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
730 GPR:$Rn, pred:$p, reglist:$regs)> {
732 let OutOperandList = (outs GPR:$wb);
733 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
735 let isCodeGenOnly = 1;
737 list<Predicate> Predicates = [IsThumb];
741 // These require base address to be written back or one of the loaded regs.
742 let neverHasSideEffects = 1 in {
744 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
745 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
746 {1,1,0,0,1,?}, 1, "tLDM">;
748 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
749 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
750 {1,1,0,0,0,?}, 0, "tSTM">;
752 } // neverHasSideEffects
754 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
755 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
757 "pop${p}\t$regs", []>,
758 T1Misc<{1,1,0,?,?,?,?}> {
760 let Inst{8} = regs{15};
761 let Inst{7-0} = regs{7-0};
764 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
765 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
767 "push${p}\t$regs", []>,
768 T1Misc<{0,1,0,?,?,?,?}> {
770 let Inst{8} = regs{14};
771 let Inst{7-0} = regs{7-0};
774 //===----------------------------------------------------------------------===//
775 // Arithmetic Instructions.
778 // Helper classes for encoding T1pI patterns:
779 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
780 string opc, string asm, list<dag> pattern>
781 : T1pI<oops, iops, itin, opc, asm, pattern>,
782 T1DataProcessing<opA> {
788 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
789 string opc, string asm, list<dag> pattern>
790 : T1pI<oops, iops, itin, opc, asm, pattern>,
798 // Helper classes for encoding T1sI patterns:
799 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
800 string opc, string asm, list<dag> pattern>
801 : T1sI<oops, iops, itin, opc, asm, pattern>,
802 T1DataProcessing<opA> {
808 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : T1sI<oops, iops, itin, opc, asm, pattern>,
819 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
820 string opc, string asm, list<dag> pattern>
821 : T1sI<oops, iops, itin, opc, asm, pattern>,
829 // Helper classes for encoding T1sIt patterns:
830 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
831 string opc, string asm, list<dag> pattern>
832 : T1sIt<oops, iops, itin, opc, asm, pattern>,
833 T1DataProcessing<opA> {
839 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
840 string opc, string asm, list<dag> pattern>
841 : T1sIt<oops, iops, itin, opc, asm, pattern>,
845 let Inst{10-8} = Rdn;
846 let Inst{7-0} = imm8;
849 // Add with carry register
850 let isCommutable = 1, Uses = [CPSR] in
852 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
853 "adc", "\t$Rdn, $Rm",
854 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
857 def tADDi3 : // A8.6.4 T1
858 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
860 "add", "\t$Rd, $Rm, $imm3",
861 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
863 let Inst{8-6} = imm3;
866 def tADDi8 : // A8.6.4 T2
867 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
868 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
869 "add", "\t$Rdn, $imm8",
870 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
873 let isCommutable = 1 in
874 def tADDrr : // A8.6.6 T1
875 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
877 "add", "\t$Rd, $Rn, $Rm",
878 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
880 let neverHasSideEffects = 1 in
881 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
882 "add", "\t$Rdn, $Rm", []>,
883 T1Special<{0,0,?,?}> {
887 let Inst{7} = Rdn{3};
889 let Inst{2-0} = Rdn{2-0};
893 let isCommutable = 1 in
894 def tAND : // A8.6.12
895 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
897 "and", "\t$Rdn, $Rm",
898 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
901 def tASRri : // A8.6.14
902 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
904 "asr", "\t$Rd, $Rm, $imm5",
905 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
907 let Inst{10-6} = imm5;
911 def tASRrr : // A8.6.15
912 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
914 "asr", "\t$Rdn, $Rm",
915 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
918 def tBIC : // A8.6.20
919 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
921 "bic", "\t$Rdn, $Rm",
922 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
925 let isCompare = 1, Defs = [CPSR] in {
926 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
927 // Compare-to-zero still works out, just not the relationals
928 //def tCMN : // A8.6.33
929 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
931 // "cmn", "\t$lhs, $rhs",
932 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
934 def tCMNz : // A8.6.33
935 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
938 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
940 } // isCompare = 1, Defs = [CPSR]
943 let isCompare = 1, Defs = [CPSR] in {
944 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
945 "cmp", "\t$Rn, $imm8",
946 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
947 T1General<{1,0,1,?,?}> {
952 let Inst{7-0} = imm8;
956 def tCMPr : // A8.6.36 T1
957 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
960 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
962 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
963 "cmp", "\t$Rn, $Rm", []>,
964 T1Special<{0,1,?,?}> {
970 let Inst{2-0} = Rn{2-0};
972 } // isCompare = 1, Defs = [CPSR]
976 let isCommutable = 1 in
977 def tEOR : // A8.6.45
978 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
980 "eor", "\t$Rdn, $Rm",
981 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
984 def tLSLri : // A8.6.88
985 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
987 "lsl", "\t$Rd, $Rm, $imm5",
988 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
990 let Inst{10-6} = imm5;
994 def tLSLrr : // A8.6.89
995 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
997 "lsl", "\t$Rdn, $Rm",
998 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1001 def tLSRri : // A8.6.90
1002 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1004 "lsr", "\t$Rd, $Rm, $imm5",
1005 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
1007 let Inst{10-6} = imm5;
1011 def tLSRrr : // A8.6.91
1012 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1014 "lsr", "\t$Rdn, $Rm",
1015 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1018 let isMoveImm = 1 in
1019 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1020 "mov", "\t$Rd, $imm8",
1021 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1022 T1General<{1,0,0,?,?}> {
1026 let Inst{10-8} = Rd;
1027 let Inst{7-0} = imm8;
1030 // A7-73: MOV(2) - mov setting flag.
1032 let neverHasSideEffects = 1 in {
1033 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1035 "mov", "\t$Rd, $Rm", "", []>,
1036 T1Special<{1,0,?,?}> {
1040 let Inst{7} = Rd{3};
1042 let Inst{2-0} = Rd{2-0};
1044 let Defs = [CPSR] in
1045 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1046 "movs\t$Rd, $Rm", []>, Encoding16 {
1050 let Inst{15-6} = 0b0000000000;
1054 } // neverHasSideEffects
1056 // Multiply register
1057 let isCommutable = 1 in
1058 def tMUL : // A8.6.105 T1
1059 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1061 "mul", "\t$Rdn, $Rm, $Rdn",
1062 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1064 // Move inverse register
1065 def tMVN : // A8.6.107
1066 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1067 "mvn", "\t$Rd, $Rn",
1068 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1070 // Bitwise or register
1071 let isCommutable = 1 in
1072 def tORR : // A8.6.114
1073 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1075 "orr", "\t$Rdn, $Rm",
1076 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1079 def tREV : // A8.6.134
1080 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1082 "rev", "\t$Rd, $Rm",
1083 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1084 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1086 def tREV16 : // A8.6.135
1087 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1089 "rev16", "\t$Rd, $Rm",
1090 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1091 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1093 def tREVSH : // A8.6.136
1094 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1096 "revsh", "\t$Rd, $Rm",
1097 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1098 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1100 // Rotate right register
1101 def tROR : // A8.6.139
1102 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1104 "ror", "\t$Rdn, $Rm",
1105 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1108 def tRSB : // A8.6.141
1109 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1111 "rsb", "\t$Rd, $Rn, #0",
1112 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1114 // Subtract with carry register
1115 let Uses = [CPSR] in
1116 def tSBC : // A8.6.151
1117 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1119 "sbc", "\t$Rdn, $Rm",
1120 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1122 // Subtract immediate
1123 def tSUBi3 : // A8.6.210 T1
1124 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1126 "sub", "\t$Rd, $Rm, $imm3",
1127 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1129 let Inst{8-6} = imm3;
1132 def tSUBi8 : // A8.6.210 T2
1133 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1135 "sub", "\t$Rdn, $imm8",
1136 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1138 // Subtract register
1139 def tSUBrr : // A8.6.212
1140 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1142 "sub", "\t$Rd, $Rn, $Rm",
1143 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1145 // TODO: A7-96: STMIA - store multiple.
1148 def tSXTB : // A8.6.222
1149 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1151 "sxtb", "\t$Rd, $Rm",
1152 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1153 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1155 // Sign-extend short
1156 def tSXTH : // A8.6.224
1157 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1159 "sxth", "\t$Rd, $Rm",
1160 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1161 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1164 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1165 def tTST : // A8.6.230
1166 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1167 "tst", "\t$Rn, $Rm",
1168 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1171 def tUXTB : // A8.6.262
1172 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1174 "uxtb", "\t$Rd, $Rm",
1175 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1176 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1178 // Zero-extend short
1179 def tUXTH : // A8.6.264
1180 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1182 "uxth", "\t$Rd, $Rm",
1183 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1184 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1186 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1187 // Expanded after instruction selection into a branch sequence.
1188 let usesCustomInserter = 1 in // Expanded after instruction selection.
1189 def tMOVCCr_pseudo :
1190 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1192 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1194 // tLEApcrel - Load a pc-relative address into a register without offending the
1197 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1198 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1199 T1Encoding<{1,0,1,0,0,?}> {
1202 let Inst{10-8} = Rd;
1203 let Inst{7-0} = addr;
1204 let DecoderMethod = "DecodeThumbAddSpecialReg";
1207 let neverHasSideEffects = 1, isReMaterializable = 1 in
1208 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1211 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1212 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1215 //===----------------------------------------------------------------------===//
1219 // __aeabi_read_tp preserves the registers r1-r3.
1220 // This is a pseudo inst so that we can get the encoding right,
1221 // complete with fixup for the aeabi_read_tp function.
1222 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1223 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1224 [(set R0, ARMthread_pointer)]>;
1226 //===----------------------------------------------------------------------===//
1227 // SJLJ Exception handling intrinsics
1230 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1231 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1232 // from some other function to get here, and we're using the stack frame for the
1233 // containing function to save/restore registers, we can't keep anything live in
1234 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1235 // tromped upon when we get here from a longjmp(). We force everything out of
1236 // registers except for our own input by listing the relevant registers in
1237 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1238 // preserve all of the callee-saved resgisters, which is exactly what we want.
1239 // $val is a scratch register for our use.
1240 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1241 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1242 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1243 AddrModeNone, 0, NoItinerary, "","",
1244 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1246 // FIXME: Non-Darwin version(s)
1247 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1248 Defs = [ R7, LR, SP ] in
1249 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1250 AddrModeNone, 0, IndexModeNone,
1251 Pseudo, NoItinerary, "", "",
1252 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1253 Requires<[IsThumb, IsDarwin]>;
1255 //===----------------------------------------------------------------------===//
1256 // Non-Instruction Patterns
1260 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1261 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1262 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1263 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1266 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1267 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1268 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1269 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1270 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1271 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1273 // Subtract with carry
1274 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1275 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1276 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1277 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1278 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1279 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1281 // ConstantPool, GlobalAddress
1282 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1283 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1286 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1287 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1290 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1291 Requires<[IsThumb, IsNotDarwin]>;
1292 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1293 Requires<[IsThumb, IsDarwin]>;
1295 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1296 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1297 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1298 Requires<[IsThumb, HasV5T, IsDarwin]>;
1300 // Indirect calls to ARM routines
1301 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1302 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1303 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1304 Requires<[IsThumb, HasV5T, IsDarwin]>;
1306 // zextload i1 -> zextload i8
1307 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1308 (tLDRBr t_addrmode_rrs1:$addr)>;
1309 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1310 (tLDRBi t_addrmode_is1:$addr)>;
1312 // extload -> zextload
1313 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1314 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1315 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1316 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1317 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1318 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1320 // If it's impossible to use [r,r] address mode for sextload, select to
1321 // ldr{b|h} + sxt{b|h} instead.
1322 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1323 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1324 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1325 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1326 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1327 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1328 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1329 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1330 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1331 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1332 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1333 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1335 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1336 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1337 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1338 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1339 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1340 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1341 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1342 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1344 // Large immediate handling.
1347 def : T1Pat<(i32 thumb_immshifted:$src),
1348 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1349 (thumb_immshifted_shamt imm:$src))>;
1351 def : T1Pat<(i32 imm0_255_comp:$src),
1352 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1354 // Pseudo instruction that combines ldr from constpool and add pc. This should
1355 // be expanded into two instructions late to allow if-conversion and
1357 let isReMaterializable = 1 in
1358 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1360 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1362 Requires<[IsThumb, IsThumb1Only]>;
1364 // Pseudo-instruction for merged POP and return.
1365 // FIXME: remove when we have a way to marking a MI with these properties.
1366 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1367 hasExtraDefRegAllocReq = 1 in
1368 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1370 (tPOP pred:$p, reglist:$regs)>;
1372 // Indirect branch using "mov pc, $Rm"
1373 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1374 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1375 2, IIC_Br, [(brind GPR:$Rm)],
1376 (tMOVr PC, GPR:$Rm, pred:$p)>;