1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
131 Requires<[IsThumb, IsThumb1Only]>;
133 def tADJCALLSTACKDOWN :
134 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
135 [(ARMcallseq_start imm:$amt)]>,
136 Requires<[IsThumb, IsThumb1Only]>;
139 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
140 [/* For disassembly only; pattern left blank */]>,
141 T1Encoding<0b101111> {
142 let Inst{9-8} = 0b11;
143 let Inst{7-0} = 0x00;
146 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
147 [/* For disassembly only; pattern left blank */]>,
148 T1Encoding<0b101111> {
149 let Inst{9-8} = 0b11;
150 let Inst{7-0} = 0x10;
153 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
154 [/* For disassembly only; pattern left blank */]>,
155 T1Encoding<0b101111> {
156 let Inst{9-8} = 0b11;
157 let Inst{7-0} = 0x20;
160 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
161 [/* For disassembly only; pattern left blank */]>,
162 T1Encoding<0b101111> {
163 let Inst{9-8} = 0b11;
164 let Inst{7-0} = 0x30;
167 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
168 [/* For disassembly only; pattern left blank */]>,
169 T1Encoding<0b101111> {
170 let Inst{9-8} = 0b11;
171 let Inst{7-0} = 0x40;
174 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
175 [/* For disassembly only; pattern left blank */]>,
176 T1Encoding<0b101101> {
177 let Inst{9-5} = 0b10010;
179 let Inst{3} = 1; // Big-Endian
180 let Inst{2-0} = 0b000;
183 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
184 [/* For disassembly only; pattern left blank */]>,
185 T1Encoding<0b101101> {
186 let Inst{9-5} = 0b10010;
188 let Inst{3} = 0; // Little-Endian
189 let Inst{2-0} = 0b000;
192 // The i32imm operand $val can be used by a debugger to store more information
193 // about the breakpoint.
194 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
195 [/* For disassembly only; pattern left blank */]>,
196 T1Encoding<0b101111> {
198 let Inst{9-8} = 0b10;
202 // Change Processor State is a system instruction -- for disassembly only.
203 // The singleton $opt operand contains the following information:
204 // opt{4-0} = mode ==> don't care
205 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
206 // opt{8-6} = AIF from Inst{2-0}
207 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
209 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
210 // CPS which has more options.
211 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
212 [/* For disassembly only; pattern left blank */]>,
215 // For both thumb1 and thumb2.
216 let isNotDuplicable = 1, isCodeGenOnly = 1 in
217 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
218 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
219 T1Special<{0,0,?,?}> {
222 let Inst{6-3} = 0b1111;
227 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
228 "add\t$dst, pc, $rhs", []>,
229 T1Encoding<{1,0,1,0,0,?}> {
233 let Inst{10-8} = dst;
237 // ADD <Rd>, sp, #<imm8>
238 // This is rematerializable, which is particularly useful for taking the
239 // address of locals.
240 let isReMaterializable = 1 in
241 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
242 "add\t$dst, $sp, $rhs", []>,
243 T1Encoding<{1,0,1,0,1,?}> {
247 let Inst{10-8} = dst;
251 // ADD sp, sp, #<imm7>
252 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
253 "add\t$dst, $rhs", []>,
254 T1Misc<{0,0,0,0,0,?,?}> {
260 // SUB sp, sp, #<imm7>
261 // FIXME: The encoding and the ASM string don't match up.
262 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
263 "sub\t$dst, $rhs", []>,
264 T1Misc<{0,0,0,0,1,?,?}> {
271 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
272 "add\t$dst, $rhs", []>,
273 T1Special<{0,0,?,?}> {
274 // A8.6.9 Encoding T1
276 let Inst{7} = dst{3};
277 let Inst{6-3} = 0b1101;
278 let Inst{2-0} = dst{2-0};
282 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
283 "add\t$dst, $rhs", []>,
284 T1Special<{0,0,?,?}> {
285 // A8.6.9 Encoding T2
289 let Inst{2-0} = 0b101;
292 //===----------------------------------------------------------------------===//
293 // Control Flow Instructions.
296 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
297 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
299 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
300 let Inst{6-3} = 0b1110; // Rm = lr
301 let Inst{2-0} = 0b000;
304 // Alternative return instruction used by vararg functions.
305 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
308 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
311 let Inst{2-0} = 0b000;
316 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
317 def tBRIND : TI<(outs), (ins GPR:$Rm), IIC_Br, "mov\tpc, $Rm",
319 T1Special<{1,0,1,?}> {
323 let Inst{2-0} = 0b111; // <Rd> = Inst{7:2-0} = pc
327 // FIXME: remove when we have a way to marking a MI with these properties.
328 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
329 hasExtraDefRegAllocReq = 1 in
330 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
332 "pop${p}\t$regs", []>,
333 T1Misc<{1,1,0,?,?,?,?}> {
336 let Inst{8} = regs{15};
337 let Inst{7-0} = regs{7-0};
341 Defs = [R0, R1, R2, R3, R12, LR,
342 D0, D1, D2, D3, D4, D5, D6, D7,
343 D16, D17, D18, D19, D20, D21, D22, D23,
344 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
345 // Also used for Thumb2
346 def tBL : TIx2<0b11110, 0b11, 1,
347 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
349 [(ARMtcall tglobaladdr:$func)]>,
350 Requires<[IsThumb, IsNotDarwin]>;
352 // ARMv5T and above, also used for Thumb2
353 def tBLXi : TIx2<0b11110, 0b11, 0,
354 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
356 [(ARMcall tglobaladdr:$func)]>,
357 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
359 // Also used for Thumb2
360 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
362 [(ARMtcall GPR:$func)]>,
363 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
364 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
367 let isCodeGenOnly = 1 in
368 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
369 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
370 "mov\tlr, pc\n\tbx\t$func",
371 [(ARMcall_nolink tGPR:$func)]>,
372 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
375 // On Darwin R9 is call-clobbered.
377 Defs = [R0, R1, R2, R3, R9, R12, LR,
378 D0, D1, D2, D3, D4, D5, D6, D7,
379 D16, D17, D18, D19, D20, D21, D22, D23,
380 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
381 // Also used for Thumb2
382 def tBLr9 : TIx2<0b11110, 0b11, 1,
383 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
385 [(ARMtcall tglobaladdr:$func)]>,
386 Requires<[IsThumb, IsDarwin]>;
388 // ARMv5T and above, also used for Thumb2
389 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
390 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
392 [(ARMcall tglobaladdr:$func)]>,
393 Requires<[IsThumb, HasV5T, IsDarwin]>;
395 // Also used for Thumb2
396 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
398 [(ARMtcall GPR:$func)]>,
399 Requires<[IsThumb, HasV5T, IsDarwin]>,
400 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
403 let isCodeGenOnly = 1 in
404 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
405 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
406 "mov\tlr, pc\n\tbx\t$func",
407 [(ARMcall_nolink tGPR:$func)]>,
408 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
411 let isBranch = 1, isTerminator = 1 in {
412 let isBarrier = 1 in {
413 let isPredicable = 1 in
414 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
415 "b\t$target", [(br bb:$target)]>,
416 T1Encoding<{1,1,1,0,0,?}>;
420 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
423 let isCodeGenOnly = 1 in
424 def tBR_JTr : T1JTI<(outs),
425 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
426 IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
427 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
429 let Inst{15-7} = 0b010001101;
430 let Inst{2-0} = 0b111;
435 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
436 // a two-value operand where a dag node expects two operands. :(
437 let isBranch = 1, isTerminator = 1 in
438 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
440 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
441 T1Encoding<{1,1,0,1,?,?}>;
443 // Compare and branch on zero / non-zero
444 let isBranch = 1, isTerminator = 1 in {
445 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
446 "cbz\t$cmp, $target", []>,
447 T1Misc<{0,0,?,1,?,?,?}>;
449 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
450 "cbnz\t$cmp, $target", []>,
451 T1Misc<{1,0,?,1,?,?,?}>;
454 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
455 // A8.6.16 B: Encoding T1
456 // If Inst{11-8} == 0b1111 then SEE SVC
458 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
460 let Inst{15-12} = 0b1101;
461 let Inst{11-8} = 0b1111;
465 // A8.6.16 B: Encoding T1
466 // If Inst{11-8} == 0b1110 then UNDEFINED
467 let isBarrier = 1, isTerminator = 1 in
468 def tTRAP : TI<(outs), (ins), IIC_Br,
469 "trap", [(trap)]>, Encoding16 {
470 let Inst{15-12} = 0b1101;
471 let Inst{11-8} = 0b1110;
474 //===----------------------------------------------------------------------===//
475 // Load Store Instructions.
478 let canFoldAsLoad = 1, isReMaterializable = 1 in
479 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
480 "ldr", "\t$dst, $addr",
481 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
483 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
484 "ldr", "\t$dst, $addr",
488 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
489 "ldrb", "\t$dst, $addr",
490 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
492 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
493 "ldrb", "\t$dst, $addr",
497 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
498 "ldrh", "\t$dst, $addr",
499 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
501 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
502 "ldrh", "\t$dst, $addr",
506 let AddedComplexity = 10 in
507 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
508 "ldrsb", "\t$dst, $addr",
509 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
512 let AddedComplexity = 10 in
513 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
514 "ldrsh", "\t$dst, $addr",
515 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
518 let canFoldAsLoad = 1 in
519 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
520 "ldr", "\t$dst, $addr",
521 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
524 // Special instruction for restore. It cannot clobber condition register
525 // when it's expanded by eliminateCallFramePseudoInstr().
526 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
527 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
528 "ldr", "\t$dst, $addr", []>,
532 // FIXME: Use ldr.n to work around a Darwin assembler bug.
533 let canFoldAsLoad = 1, isReMaterializable = 1 in
534 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
535 "ldr", ".n\t$dst, $addr",
536 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
537 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
539 // Special LDR for loads from non-pc-relative constpools.
540 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
541 isReMaterializable = 1 in
542 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
543 "ldr", "\t$dst, $addr", []>,
546 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
547 "str", "\t$src, $addr",
548 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
550 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
551 "str", "\t$src, $addr",
555 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
556 "strb", "\t$src, $addr",
557 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
559 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
560 "strb", "\t$src, $addr",
564 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
565 "strh", "\t$src, $addr",
566 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
568 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
569 "strh", "\t$src, $addr",
573 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
574 "str", "\t$src, $addr",
575 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
578 let mayStore = 1, neverHasSideEffects = 1 in {
579 // Special instruction for spill. It cannot clobber condition register
580 // when it's expanded by eliminateCallFramePseudoInstr().
581 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
582 "str", "\t$src, $addr", []>,
586 //===----------------------------------------------------------------------===//
587 // Load / store multiple Instructions.
590 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
591 InstrItinClass itin_upd, bits<6> T1Enc,
594 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
595 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
598 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
599 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
603 // These require base address to be written back or one of the loaded regs.
604 let neverHasSideEffects = 1 in {
606 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
607 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
610 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
611 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
614 } // neverHasSideEffects
616 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
617 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
619 "pop${p}\t$regs", []>,
620 T1Misc<{1,1,0,?,?,?,?}> {
623 let Inst{8} = regs{15};
624 let Inst{7-0} = regs{7-0};
627 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
628 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops),
630 "push${p}\t$srcs", []>,
631 T1Misc<{0,1,0,?,?,?,?}>;
633 //===----------------------------------------------------------------------===//
634 // Arithmetic Instructions.
637 // Add with carry register
638 let isCommutable = 1, Uses = [CPSR] in
639 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
640 "adc", "\t$dst, $rhs",
641 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
642 T1DataProcessing<0b0101>;
645 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
646 "add", "\t$dst, $lhs, $rhs",
647 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
650 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
651 "add", "\t$dst, $rhs",
652 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
653 T1General<{1,1,0,?,?}>;
656 let isCommutable = 1 in
657 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
658 "add", "\t$dst, $lhs, $rhs",
659 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
662 let neverHasSideEffects = 1 in
663 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
664 "add", "\t$dst, $rhs", []>,
665 T1Special<{0,0,?,?}>;
668 let isCommutable = 1 in
669 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
670 "and", "\t$dst, $rhs",
671 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
672 T1DataProcessing<0b0000>;
675 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
676 "asr", "\t$dst, $lhs, $rhs",
677 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
678 T1General<{0,1,0,?,?}>;
681 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
682 "asr", "\t$dst, $rhs",
683 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
684 T1DataProcessing<0b0100>;
687 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
688 "bic", "\t$dst, $rhs",
689 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
690 T1DataProcessing<0b1110>;
693 let isCompare = 1, Defs = [CPSR] in {
694 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
695 // Compare-to-zero still works out, just not the relationals
696 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
697 // "cmn", "\t$lhs, $rhs",
698 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
699 // T1DataProcessing<0b1011>;
700 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
701 "cmn", "\t$lhs, $rhs",
702 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
703 T1DataProcessing<0b1011>;
707 let isCompare = 1, Defs = [CPSR] in {
708 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
709 "cmp", "\t$lhs, $rhs",
710 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
711 T1General<{1,0,1,?,?}>;
712 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
713 "cmp", "\t$lhs, $rhs",
714 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
715 T1General<{1,0,1,?,?}>;
719 let isCompare = 1, Defs = [CPSR] in {
720 def tCMPr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
722 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>,
723 T1DataProcessing<0b1010> {
731 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
732 "cmp", "\t$lhs, $rhs",
733 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
734 T1DataProcessing<0b1010>;
736 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
737 "cmp", "\t$lhs, $rhs", []>,
738 T1Special<{0,1,?,?}>;
739 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
740 "cmp", "\t$lhs, $rhs", []>,
741 T1Special<{0,1,?,?}>;
746 let isCommutable = 1 in
747 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
748 "eor", "\t$dst, $rhs",
749 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
750 T1DataProcessing<0b0001>;
753 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
754 "lsl", "\t$dst, $lhs, $rhs",
755 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
756 T1General<{0,0,0,?,?}>;
759 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
760 "lsl", "\t$dst, $rhs",
761 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
762 T1DataProcessing<0b0010>;
765 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
766 "lsr", "\t$dst, $lhs, $rhs",
767 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
768 T1General<{0,0,1,?,?}>;
771 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
772 "lsr", "\t$dst, $rhs",
773 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
774 T1DataProcessing<0b0011>;
778 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
779 "mov", "\t$dst, $src",
780 [(set tGPR:$dst, imm0_255:$src)]>,
781 T1General<{1,0,0,?,?}>;
783 // TODO: A7-73: MOV(2) - mov setting flag.
786 let neverHasSideEffects = 1 in {
787 // FIXME: Make this predicable.
788 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
789 "mov\t$dst, $src", []>,
792 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
793 "movs\t$dst, $src", []>, Encoding16 {
794 let Inst{15-6} = 0b0000000000;
797 // FIXME: Make these predicable.
798 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
799 "mov\t$dst, $src", []>,
800 T1Special<{1,0,0,?}>;
801 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
802 "mov\t$dst, $src", []>,
803 T1Special<{1,0,?,0}>;
804 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
805 "mov\t$dst, $src", []>,
806 T1Special<{1,0,?,?}>;
807 } // neverHasSideEffects
810 let isCommutable = 1 in
811 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
812 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
813 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
814 T1DataProcessing<0b1101>;
816 // move inverse register
817 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMVNr,
818 "mvn", "\t$dst, $src",
819 [(set tGPR:$dst, (not tGPR:$src))]>,
820 T1DataProcessing<0b1111>;
822 // bitwise or register
823 let isCommutable = 1 in
824 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
825 "orr", "\t$dst, $rhs",
826 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
827 T1DataProcessing<0b1100>;
830 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
831 "rev", "\t$dst, $src",
832 [(set tGPR:$dst, (bswap tGPR:$src))]>,
833 Requires<[IsThumb, IsThumb1Only, HasV6]>,
834 T1Misc<{1,0,1,0,0,0,?}>;
836 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
837 "rev16", "\t$dst, $src",
839 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
840 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
841 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
842 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
843 Requires<[IsThumb, IsThumb1Only, HasV6]>,
844 T1Misc<{1,0,1,0,0,1,?}>;
846 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
847 "revsh", "\t$dst, $src",
850 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
851 (shl tGPR:$src, (i32 8))), i16))]>,
852 Requires<[IsThumb, IsThumb1Only, HasV6]>,
853 T1Misc<{1,0,1,0,1,1,?}>;
855 // rotate right register
856 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
857 "ror", "\t$dst, $rhs",
858 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
859 T1DataProcessing<0b0111>;
862 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
863 "rsb", "\t$dst, $src, #0",
864 [(set tGPR:$dst, (ineg tGPR:$src))]>,
865 T1DataProcessing<0b1001>;
867 // Subtract with carry register
869 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
870 "sbc", "\t$dst, $rhs",
871 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
872 T1DataProcessing<0b0110>;
874 // Subtract immediate
875 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
876 "sub", "\t$dst, $lhs, $rhs",
877 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
880 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
881 "sub", "\t$dst, $rhs",
882 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
883 T1General<{1,1,1,?,?}>;
886 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
887 "sub", "\t$dst, $lhs, $rhs",
888 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
891 // TODO: A7-96: STMIA - store multiple.
894 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
895 "sxtb", "\t$dst, $src",
896 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
897 Requires<[IsThumb, IsThumb1Only, HasV6]>,
898 T1Misc<{0,0,1,0,0,1,?}>;
901 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
902 "sxth", "\t$dst, $src",
903 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
904 Requires<[IsThumb, IsThumb1Only, HasV6]>,
905 T1Misc<{0,0,1,0,0,0,?}>;
908 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
909 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iTSTr,
910 "tst", "\t$lhs, $rhs",
911 [(ARMcmpZ (and_su tGPR:$lhs, tGPR:$rhs), 0)]>,
912 T1DataProcessing<0b1000>;
915 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
916 "uxtb", "\t$dst, $src",
917 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
918 Requires<[IsThumb, IsThumb1Only, HasV6]>,
919 T1Misc<{0,0,1,0,1,1,?}>;
922 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
923 "uxth", "\t$dst, $src",
924 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
925 Requires<[IsThumb, IsThumb1Only, HasV6]>,
926 T1Misc<{0,0,1,0,1,0,?}>;
929 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
930 // Expanded after instruction selection into a branch sequence.
931 let usesCustomInserter = 1 in // Expanded after instruction selection.
933 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
935 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
938 // 16-bit movcc in IT blocks for Thumb2.
939 let neverHasSideEffects = 1 in {
940 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
941 "mov", "\t$dst, $rhs", []>,
942 T1Special<{1,0,?,?}>;
945 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
946 "mov", "\t$dst, $rhs", []>,
947 T1General<{1,0,0,?,?}>;
948 } // neverHasSideEffects
950 // tLEApcrel - Load a pc-relative address into a register without offending the
952 let neverHasSideEffects = 1 in {
953 let isReMaterializable = 1 in
954 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
955 "adr$p\t$dst, #$label", []>,
956 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
958 } // neverHasSideEffects
959 def tLEApcrelJT : T1I<(outs tGPR:$dst),
960 (ins i32imm:$label, nohash_imm:$id, pred:$p),
961 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
962 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
964 //===----------------------------------------------------------------------===//
968 // __aeabi_read_tp preserves the registers r1-r3.
971 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
972 "bl\t__aeabi_read_tp",
973 [(set R0, ARMthread_pointer)]>;
976 // SJLJ Exception handling intrinsics
977 // eh_sjlj_setjmp() is an instruction sequence to store the return
978 // address and save #0 in R0 for the non-longjmp case.
979 // Since by its nature we may be coming from some other function to get
980 // here, and we're using the stack frame for the containing function to
981 // save/restore registers, we can't keep anything live in regs across
982 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
983 // when we get here from a longjmp(). We force everthing out of registers
984 // except for our own input by listing the relevant registers in Defs. By
985 // doing so, we also cause the prologue/epilogue code to actively preserve
986 // all of the callee-saved resgisters, which is exactly what we want.
987 // $val is a scratch register for our use.
989 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
990 isBarrier = 1, isCodeGenOnly = 1 in {
991 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
992 AddrModeNone, SizeSpecial, NoItinerary, "", "",
993 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
996 // FIXME: Non-Darwin version(s)
997 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
998 Defs = [ R7, LR, SP ] in {
999 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1000 AddrModeNone, SizeSpecial, IndexModeNone,
1001 Pseudo, NoItinerary, "", "",
1002 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1003 Requires<[IsThumb, IsDarwin]>;
1006 //===----------------------------------------------------------------------===//
1007 // Non-Instruction Patterns
1011 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1012 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1013 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1014 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1015 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1016 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1018 // Subtract with carry
1019 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1020 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1021 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1022 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1023 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1024 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1026 // ConstantPool, GlobalAddress
1027 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1028 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1031 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1032 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1035 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1036 Requires<[IsThumb, IsNotDarwin]>;
1037 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1038 Requires<[IsThumb, IsDarwin]>;
1040 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1041 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1042 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1043 Requires<[IsThumb, HasV5T, IsDarwin]>;
1045 // Indirect calls to ARM routines
1046 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1047 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1048 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1049 Requires<[IsThumb, HasV5T, IsDarwin]>;
1051 // zextload i1 -> zextload i8
1052 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
1053 (tLDRB t_addrmode_s1:$addr)>;
1055 // extload -> zextload
1056 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1057 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1058 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
1060 // If it's impossible to use [r,r] address mode for sextload, select to
1061 // ldr{b|h} + sxt{b|h} instead.
1062 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1063 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1064 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1065 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1066 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1067 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1069 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1070 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1071 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1072 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1074 // Large immediate handling.
1077 def : T1Pat<(i32 thumb_immshifted:$src),
1078 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1079 (thumb_immshifted_shamt imm:$src))>;
1081 def : T1Pat<(i32 imm0_255_comp:$src),
1082 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1084 // Pseudo instruction that combines ldr from constpool and add pc. This should
1085 // be expanded into two instructions late to allow if-conversion and
1087 let isReMaterializable = 1 in
1088 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1090 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1092 Requires<[IsThumb, IsThumb1Only]>;