1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 def MemModeThumbAsmOperand : AsmOperandClass {
78 let Name = "MemModeThumb";
79 let SuperClasses = [];
82 // t_addrmode_rr := reg + reg
84 def t_addrmode_rr : Operand<i32>,
85 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
86 let PrintMethod = "printThumbAddrModeRROperand";
87 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
90 // t_addrmode_s4 := reg + reg
93 def t_addrmode_s4 : Operand<i32>,
94 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
95 string EncoderMethod = "getAddrModeS4OpValue";
96 let PrintMethod = "printThumbAddrModeS4Operand";
97 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
98 let ParserMatchClass = MemModeThumbAsmOperand;
101 // t_addrmode_s2 := reg + reg
104 def t_addrmode_s2 : Operand<i32>,
105 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
106 string EncoderMethod = "getAddrModeS2OpValue";
107 let PrintMethod = "printThumbAddrModeS2Operand";
108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
109 let ParserMatchClass = MemModeThumbAsmOperand;
112 // t_addrmode_s1 := reg + reg
115 def t_addrmode_s1 : Operand<i32>,
116 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
117 string EncoderMethod = "getAddrModeS1OpValue";
118 let PrintMethod = "printThumbAddrModeS1Operand";
119 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
120 let ParserMatchClass = MemModeThumbAsmOperand;
123 // t_addrmode_sp := sp + imm8 * 4
125 def t_addrmode_sp : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
127 let PrintMethod = "printThumbAddrModeSPOperand";
128 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
129 let ParserMatchClass = MemModeThumbAsmOperand;
132 //===----------------------------------------------------------------------===//
133 // Miscellaneous Instructions.
136 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
137 // from removing one half of the matched pairs. That breaks PEI, which assumes
138 // these will always be in pairs, and asserts if it finds otherwise. Better way?
139 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
140 def tADJCALLSTACKUP :
141 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
142 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
143 Requires<[IsThumb, IsThumb1Only]>;
145 def tADJCALLSTACKDOWN :
146 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
147 [(ARMcallseq_start imm:$amt)]>,
148 Requires<[IsThumb, IsThumb1Only]>;
151 // T1Disassembly - A simple class to make encoding some disassembly patterns
152 // easier and less verbose.
153 class T1Disassembly<bits<2> op1, bits<8> op2>
154 : T1Encoding<0b101111> {
159 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
160 [/* For disassembly only; pattern left blank */]>,
161 T1Disassembly<0b11, 0x00>; // A8.6.110
163 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
164 [/* For disassembly only; pattern left blank */]>,
165 T1Disassembly<0b11, 0x10>; // A8.6.410
167 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
168 [/* For disassembly only; pattern left blank */]>,
169 T1Disassembly<0b11, 0x20>; // A8.6.408
171 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
172 [/* For disassembly only; pattern left blank */]>,
173 T1Disassembly<0b11, 0x30>; // A8.6.409
175 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
176 [/* For disassembly only; pattern left blank */]>,
177 T1Disassembly<0b11, 0x40>; // A8.6.157
179 // The i32imm operand $val can be used by a debugger to store more information
180 // about the breakpoint.
181 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
182 [/* For disassembly only; pattern left blank */]>,
183 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
189 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
190 [/* For disassembly only; pattern left blank */]>,
191 T1Encoding<0b101101> {
193 let Inst{9-5} = 0b10010;
195 let Inst{3} = 1; // Big-Endian
196 let Inst{2-0} = 0b000;
199 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
200 [/* For disassembly only; pattern left blank */]>,
201 T1Encoding<0b101101> {
203 let Inst{9-5} = 0b10010;
205 let Inst{3} = 0; // Little-Endian
206 let Inst{2-0} = 0b000;
209 // Change Processor State is a system instruction -- for disassembly only.
210 // The singleton $opt operand contains the following information:
211 // opt{4-0} = mode ==> don't care
212 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
213 // opt{8-6} = AIF from Inst{2-0}
214 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
216 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
217 // CPS which has more options.
218 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
219 [/* For disassembly only; pattern left blank */]>,
223 // FIXME: Finish encoding.
226 // For both thumb1 and thumb2.
227 let isNotDuplicable = 1, isCodeGenOnly = 1 in
228 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
229 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
230 T1Special<{0,0,?,?}> {
233 let Inst{6-3} = 0b1111; // Rm = pc
237 // PC relative add (ADR).
238 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
239 "add\t$dst, pc, $rhs", []>,
240 T1Encoding<{1,0,1,0,0,?}> {
244 let Inst{10-8} = dst;
248 // ADD <Rd>, sp, #<imm8>
249 // This is rematerializable, which is particularly useful for taking the
250 // address of locals.
251 let isReMaterializable = 1 in
252 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
253 "add\t$dst, $sp, $rhs", []>,
254 T1Encoding<{1,0,1,0,1,?}> {
258 let Inst{10-8} = dst;
262 // ADD sp, sp, #<imm7>
263 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
264 "add\t$dst, $rhs", []>,
265 T1Misc<{0,0,0,0,0,?,?}> {
271 // SUB sp, sp, #<imm7>
272 // FIXME: The encoding and the ASM string don't match up.
273 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
274 "sub\t$dst, $rhs", []>,
275 T1Misc<{0,0,0,0,1,?,?}> {
282 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
283 "add\t$dst, $rhs", []>,
284 T1Special<{0,0,?,?}> {
285 // A8.6.9 Encoding T1
287 let Inst{7} = dst{3};
288 let Inst{6-3} = 0b1101;
289 let Inst{2-0} = dst{2-0};
293 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
294 "add\t$dst, $rhs", []>,
295 T1Special<{0,0,?,?}> {
296 // A8.6.9 Encoding T2
300 let Inst{2-0} = 0b101;
303 //===----------------------------------------------------------------------===//
304 // Control Flow Instructions.
307 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
308 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
310 T1Special<{1,1,0,?}> {
312 let Inst{6-3} = 0b1110; // Rm = lr
313 let Inst{2-0} = 0b000;
316 // Alternative return instruction used by vararg functions.
317 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
320 T1Special<{1,1,0,?}> {
324 let Inst{2-0} = 0b000;
329 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
330 def tBRIND : TI<(outs), (ins GPR:$Rm), IIC_Br, "mov\tpc, $Rm",
332 T1Special<{1,0,?,?}> {
335 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
337 let Inst{2-0} = 0b111;
341 // FIXME: remove when we have a way to marking a MI with these properties.
342 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
343 hasExtraDefRegAllocReq = 1 in
344 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
346 "pop${p}\t$regs", []>,
347 T1Misc<{1,1,0,?,?,?,?}> {
350 let Inst{8} = regs{15}; // registers = P:'0000000':register_list
351 let Inst{7-0} = regs{7-0};
354 // All calls clobber the non-callee saved registers. SP is marked as
355 // a use to prevent stack-pointer assignments that appear immediately
356 // before calls from potentially appearing dead.
358 // On non-Darwin platforms R9 is callee-saved.
359 Defs = [R0, R1, R2, R3, R12, LR,
360 D0, D1, D2, D3, D4, D5, D6, D7,
361 D16, D17, D18, D19, D20, D21, D22, D23,
362 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
364 // Also used for Thumb2
365 def tBL : TIx2<0b11110, 0b11, 1,
366 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
368 [(ARMtcall tglobaladdr:$func)]>,
369 Requires<[IsThumb, IsNotDarwin]>;
371 // ARMv5T and above, also used for Thumb2
372 def tBLXi : TIx2<0b11110, 0b11, 0,
373 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
375 [(ARMcall tglobaladdr:$func)]>,
376 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
378 // Also used for Thumb2
379 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
381 [(ARMtcall GPR:$func)]>,
382 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
383 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
386 let isCodeGenOnly = 1 in
387 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
388 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
389 "mov\tlr, pc\n\tbx\t$func",
390 [(ARMcall_nolink tGPR:$func)]>,
391 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
395 // On Darwin R9 is call-clobbered.
396 // R7 is marked as a use to prevent frame-pointer assignments from being
397 // moved above / below calls.
398 Defs = [R0, R1, R2, R3, R9, R12, LR,
399 D0, D1, D2, D3, D4, D5, D6, D7,
400 D16, D17, D18, D19, D20, D21, D22, D23,
401 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
403 // Also used for Thumb2
404 def tBLr9 : TIx2<0b11110, 0b11, 1,
405 (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br,
407 [(ARMtcall tglobaladdr:$func)]>,
408 Requires<[IsThumb, IsDarwin]>;
410 // ARMv5T and above, also used for Thumb2
411 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
412 (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br,
414 [(ARMcall tglobaladdr:$func)]>,
415 Requires<[IsThumb, HasV5T, IsDarwin]>;
417 // Also used for Thumb2
418 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
420 [(ARMtcall GPR:$func)]>,
421 Requires<[IsThumb, HasV5T, IsDarwin]>,
422 T1Special<{1,1,1,?}> {
425 let Inst{6-3} = func;
426 let Inst{2-0} = 0b000;
430 let isCodeGenOnly = 1 in
431 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
432 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
433 "mov\tlr, pc\n\tbx\t$func",
434 [(ARMcall_nolink tGPR:$func)]>,
435 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
438 let isBranch = 1, isTerminator = 1 in {
439 let isBarrier = 1 in {
440 let isPredicable = 1 in
441 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
442 "b\t$target", [(br bb:$target)]>,
443 T1Encoding<{1,1,1,0,0,?}>;
447 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
450 def tBR_JTr : tPseudoInst<(outs),
451 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
453 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
454 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
459 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
460 // a two-value operand where a dag node expects two operands. :(
461 let isBranch = 1, isTerminator = 1 in
462 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
464 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
465 T1Encoding<{1,1,0,1,?,?}>;
467 // Compare and branch on zero / non-zero
468 let isBranch = 1, isTerminator = 1 in {
469 def tCBZ : T1I<(outs), (ins tGPR:$Rn, brtarget:$target), IIC_Br,
470 "cbz\t$Rn, $target", []>,
471 T1Misc<{0,0,?,1,?,?,?}> {
475 let Inst{9} = target{5};
476 let Inst{7-3} = target{4-0};
480 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
481 "cbnz\t$cmp, $target", []>,
482 T1Misc<{1,0,?,1,?,?,?}> {
486 let Inst{9} = target{5};
487 let Inst{7-3} = target{4-0};
492 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
493 // A8.6.16 B: Encoding T1
494 // If Inst{11-8} == 0b1111 then SEE SVC
495 let isCall = 1, Uses = [SP] in
496 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
497 "svc", "\t$imm", []>, Encoding16 {
499 let Inst{15-12} = 0b1101;
500 let Inst{11-8} = 0b1111;
504 // The assembler uses 0xDEFE for a trap instruction.
505 let isBarrier = 1, isTerminator = 1 in
506 def tTRAP : TI<(outs), (ins), IIC_Br,
507 "trap", [(trap)]>, Encoding16 {
511 //===----------------------------------------------------------------------===//
512 // Load Store Instructions.
515 let canFoldAsLoad = 1, isReMaterializable = 1 in
516 def tLDR : // A8.6.60
517 T1pIEncode<0b100, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
518 AddrModeT1_4, IIC_iLoad_r,
519 "ldr", "\t$Rt, $addr",
520 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>;
522 def tLDRi: // A8.6.57
523 T1pIEncodeImm<0b0110, 1, (outs tGPR:$Rt), (ins t_addrmode_s4:$addr),
524 AddrModeT1_4, IIC_iLoad_r,
525 "ldr", "\t$Rt, $addr",
528 def tLDRB : // A8.6.64
529 T1pIEncode<0b110, (outs tGPR:$Rt), (ins t_addrmode_s1:$addr),
530 AddrModeT1_1, IIC_iLoad_bh_r,
531 "ldrb", "\t$Rt, $addr",
532 [(set tGPR:$Rt, (zextloadi8 t_addrmode_s1:$addr))]>;
534 def tLDRBi : // A8.6.61
535 T1pIEncodeImm<0b0111, 1, (outs tGPR:$dst), (ins t_addrmode_s1:$addr),
536 AddrModeT1_1, IIC_iLoad_bh_r,
537 "ldrb", "\t$dst, $addr",
540 def tLDRH : // A8.6.76
541 T1pIEncode<0b101, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
542 AddrModeT1_2, IIC_iLoad_bh_r,
543 "ldrh", "\t$dst, $addr",
544 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
546 def tLDRHi: // A8.6.73
547 T1pIEncodeImm<0b1000, 1, (outs tGPR:$dst), (ins t_addrmode_s2:$addr),
548 AddrModeT1_2, IIC_iLoad_bh_r,
549 "ldrh", "\t$dst, $addr",
552 let AddedComplexity = 10 in
553 def tLDRSB : // A8.6.80
554 T1pIEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
555 AddrModeT1_1, IIC_iLoad_bh_r,
556 "ldrsb", "\t$dst, $addr",
557 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
559 let AddedComplexity = 10 in
560 def tLDRSH : // A8.6.84
561 T1pIEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
562 AddrModeT1_2, IIC_iLoad_bh_r,
563 "ldrsh", "\t$dst, $addr",
564 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
566 let canFoldAsLoad = 1 in
567 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
568 "ldr", "\t$dst, $addr",
569 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
572 // Special instruction for restore. It cannot clobber condition register
573 // when it's expanded by eliminateCallFramePseudoInstr().
574 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
575 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
576 "ldr", "\t$dst, $addr", []>,
580 // FIXME: Use ldr.n to work around a Darwin assembler bug.
581 let canFoldAsLoad = 1, isReMaterializable = 1 in
582 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins i32imm:$addr), IIC_iLoad_i,
583 "ldr", ".n\t$Rt, $addr",
584 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
585 T1Encoding<{0,1,0,0,1,?}> {
589 // FIXME: Finish for the addr.
592 // Special LDR for loads from non-pc-relative constpools.
593 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
594 isReMaterializable = 1 in
595 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
596 "ldr", "\t$dst, $addr", []>,
599 def tSTR : // A8.6.194
600 T1pIEncode<0b000, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
601 AddrModeT1_4, IIC_iStore_r,
602 "str", "\t$src, $addr",
603 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
605 def tSTRi : // A8.6.192
606 T1pIEncodeImm<0b0110, 0, (outs), (ins tGPR:$src, t_addrmode_s4:$addr),
607 AddrModeT1_4, IIC_iStore_r,
608 "str", "\t$src, $addr",
611 def tSTRB : // A8.6.197
612 T1pIEncode<0b010, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
613 AddrModeT1_1, IIC_iStore_bh_r,
614 "strb", "\t$src, $addr",
615 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
617 def tSTRBi : // A8.6.195
618 T1pIEncodeImm<0b0111, 0, (outs), (ins tGPR:$src, t_addrmode_s1:$addr),
619 AddrModeT1_1, IIC_iStore_bh_r,
620 "strb", "\t$src, $addr",
623 def tSTRH : // A8.6.207
624 T1pIEncode<0b001, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
625 AddrModeT1_2, IIC_iStore_bh_r,
626 "strh", "\t$src, $addr",
627 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
629 def tSTRHi : // A8.6.205
630 T1pIEncodeImm<0b1000, 0, (outs), (ins tGPR:$src, t_addrmode_s2:$addr),
631 AddrModeT1_2, IIC_iStore_bh_r,
632 "strh", "\t$src, $addr",
635 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
636 "str", "\t$src, $addr",
637 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
640 let mayStore = 1, neverHasSideEffects = 1 in
641 // Special instruction for spill. It cannot clobber condition register when it's
642 // expanded by eliminateCallFramePseudoInstr().
643 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
644 "str", "\t$src, $addr", []>,
647 //===----------------------------------------------------------------------===//
648 // Load / store multiple Instructions.
651 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
652 InstrItinClass itin_upd, bits<6> T1Enc,
655 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
656 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
661 let Inst{7-0} = regs;
664 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
665 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
670 let Inst{7-0} = regs;
674 // These require base address to be written back or one of the loaded regs.
675 let neverHasSideEffects = 1 in {
677 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
678 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
681 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
682 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
685 } // neverHasSideEffects
687 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
688 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
690 "pop${p}\t$regs", []>,
691 T1Misc<{1,1,0,?,?,?,?}> {
693 let Inst{8} = regs{15};
694 let Inst{7-0} = regs{7-0};
697 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
698 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
700 "push${p}\t$regs", []>,
701 T1Misc<{0,1,0,?,?,?,?}> {
703 let Inst{8} = regs{14};
704 let Inst{7-0} = regs{7-0};
707 //===----------------------------------------------------------------------===//
708 // Arithmetic Instructions.
711 // Helper classes for encoding T1sI patterns:
712 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
713 string opc, string asm, list<dag> pattern>
714 : T1sI<oops, iops, itin, opc, asm, pattern>,
715 T1DataProcessing<opA> {
721 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
722 string opc, string asm, list<dag> pattern>
723 : T1sI<oops, iops, itin, opc, asm, pattern>,
732 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
733 string opc, string asm, list<dag> pattern>
734 : T1sI<oops, iops, itin, opc, asm, pattern>,
742 // Helper classes for encoding T1sIt patterns:
743 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
744 string opc, string asm, list<dag> pattern>
745 : T1sIt<oops, iops, itin, opc, asm, pattern>,
746 T1DataProcessing<opA> {
752 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
753 string opc, string asm, list<dag> pattern>
754 : T1sIt<oops, iops, itin, opc, asm, pattern>,
758 let Inst{10-8} = Rdn;
759 let Inst{7-0} = imm8;
762 // Add with carry register
763 let isCommutable = 1, Uses = [CPSR] in
765 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
766 "adc", "\t$Rdn, $Rm",
767 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
770 def tADDi3 : // A8.6.4 T1
771 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
772 "add", "\t$Rd, $Rm, $imm3",
773 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
775 let Inst{8-6} = imm3;
778 def tADDi8 : // A8.6.4 T2
779 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
781 "add", "\t$Rdn, $imm8",
782 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
785 let isCommutable = 1 in
786 def tADDrr : // A8.6.6 T1
787 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
789 "add", "\t$Rd, $Rn, $Rm",
790 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
792 let neverHasSideEffects = 1 in
793 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
794 "add", "\t$Rdn, $Rm", []>,
795 T1Special<{0,0,?,?}> {
799 let Inst{7} = Rdn{3};
801 let Inst{2-0} = Rdn{2-0};
805 let isCommutable = 1 in
806 def tAND : // A8.6.12
807 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
809 "and", "\t$Rdn, $Rm",
810 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
813 def tASRri : // A8.6.14
814 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
816 "asr", "\t$Rd, $Rm, $imm5",
817 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
819 let Inst{10-6} = imm5;
823 def tASRrr : // A8.6.15
824 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
826 "asr", "\t$Rdn, $Rm",
827 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
830 def tBIC : // A8.6.20
831 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
833 "bic", "\t$Rdn, $Rm",
834 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
837 let isCompare = 1, Defs = [CPSR] in {
838 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
839 // Compare-to-zero still works out, just not the relationals
840 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
841 // "cmn", "\t$lhs, $rhs",
842 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
843 // T1DataProcessing<0b1011>;
844 def tCMNz : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
846 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>,
847 T1DataProcessing<0b1011> {
857 let isCompare = 1, Defs = [CPSR] in {
858 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
859 "cmp", "\t$Rn, $imm8",
860 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
861 T1General<{1,0,1,?,?}> {
866 let Inst{7-0} = imm8;
869 def tCMPzi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
870 "cmp", "\t$Rn, $imm8",
871 [(ARMcmpZ tGPR:$Rn, imm0_255:$imm8)]>,
872 T1General<{1,0,1,?,?}> {
876 let Inst{7-0} = 0x00;
880 def tCMPr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
882 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>,
883 T1DataProcessing<0b1010> {
890 def tCMPzr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
892 [(ARMcmpZ tGPR:$Rn, tGPR:$Rm)]>,
893 T1DataProcessing<0b1010> {
901 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
902 "cmp", "\t$Rn, $Rm", []>,
903 T1Special<{0,1,?,?}> {
909 let Inst{2-0} = Rn{2-0};
911 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
912 "cmp", "\t$lhs, $rhs", []>,
913 T1Special<{0,1,?,?}> {
919 let Inst{2-0} = Rn{2-0};
922 } // isCompare = 1, Defs = [CPSR]
926 let isCommutable = 1 in
927 def tEOR : // A8.6.45
928 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
930 "eor", "\t$Rdn, $Rm",
931 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
934 def tLSLri : // A8.6.88
935 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
937 "lsl", "\t$Rd, $Rm, $imm5",
938 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
940 let Inst{10-6} = imm5;
944 def tLSLrr : // A8.6.89
945 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
947 "lsl", "\t$Rdn, $Rm",
948 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
951 def tLSRri : // A8.6.90
952 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
954 "lsr", "\t$Rd, $Rm, $imm5",
955 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
957 let Inst{10-6} = imm5;
961 def tLSRrr : // A8.6.91
962 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
964 "lsr", "\t$Rdn, $Rm",
965 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
969 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
970 "mov", "\t$Rd, $imm8",
971 [(set tGPR:$Rd, imm0_255:$imm8)]>,
972 T1General<{1,0,0,?,?}> {
977 let Inst{7-0} = imm8;
980 // TODO: A7-73: MOV(2) - mov setting flag.
982 let neverHasSideEffects = 1 in {
983 // FIXME: Make this predicable.
984 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
985 "mov\t$dst, $src", []>,
988 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
989 "movs\t$dst, $src", []>, Encoding16 {
990 let Inst{15-6} = 0b0000000000;
993 // FIXME: Make these predicable.
994 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
995 "mov\t$dst, $src", []>,
996 T1Special<{1,0,0,?}>;
997 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
998 "mov\t$dst, $src", []>,
999 T1Special<{1,0,?,0}>;
1000 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
1001 "mov\t$dst, $src", []>,
1002 T1Special<{1,0,?,?}>;
1003 } // neverHasSideEffects
1005 // multiply register
1006 let isCommutable = 1 in
1007 def tMUL : // A8.6.105 T1
1008 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1010 "mul", "\t$Rdn, $Rm, $Rdn",
1011 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1013 // Move inverse register
1014 def tMVN : // A8.6.107
1015 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1016 "mvn", "\t$Rd, $Rn",
1017 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1019 // Bitwise or register
1020 let isCommutable = 1 in
1021 def tORR : // A8.6.114
1022 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1024 "orr", "\t$Rdn, $Rm",
1025 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1028 def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1029 "rev", "\t$Rd, $Rm",
1030 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1031 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1032 T1Misc<{1,0,1,0,0,0,?}> {
1040 def tREV16 : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1041 "rev16", "\t$Rd, $Rm",
1043 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1044 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1045 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1046 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1047 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1048 T1Misc<{1,0,1,0,0,1,?}> {
1056 def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1057 "revsh", "\t$Rd, $Rm",
1060 (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1061 (shl tGPR:$Rm, (i32 8))), i16))]>,
1062 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1063 T1Misc<{1,0,1,0,1,1,?}> {
1071 // Rotate right register
1072 def tROR : // A8.6.139
1073 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1075 "ror", "\t$Rdn, $Rm",
1076 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1079 def tRSB : // A8.6.141
1080 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1082 "rsb", "\t$Rd, $Rn, #0",
1083 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1085 // Subtract with carry register
1086 let Uses = [CPSR] in
1087 def tSBC : // A8.6.151
1088 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1090 "sbc", "\t$Rdn, $Rm",
1091 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1093 // Subtract immediate
1094 def tSUBi3 : // A8.6.210 T1
1095 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1097 "sub", "\t$Rd, $Rm, $imm3",
1098 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1100 let Inst{8-6} = imm3;
1103 def tSUBi8 : // A8.6.210 T2
1104 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1106 "sub", "\t$Rdn, $imm8",
1107 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1109 // Subtract register
1110 def tSUBrr : // A8.6.212
1111 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1113 "sub", "\t$Rd, $Rn, $Rm",
1114 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1116 // TODO: A7-96: STMIA - store multiple.
1119 def tSXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1120 "sxtb", "\t$Rd, $Rm",
1121 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1122 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1123 T1Misc<{0,0,1,0,0,1,?}> {
1131 // sign-extend short
1132 def tSXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1133 "sxth", "\t$Rd, $Rm",
1134 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1135 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1136 T1Misc<{0,0,1,0,0,0,?}> {
1145 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1146 def tTST : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1147 "tst", "\t$Rn, $Rm",
1148 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1149 T1DataProcessing<0b1000> {
1158 def tUXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1159 "uxtb", "\t$Rd, $Rm",
1160 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1161 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1162 T1Misc<{0,0,1,0,1,1,?}> {
1170 // zero-extend short
1171 def tUXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1172 "uxth", "\t$Rd, $Rm",
1173 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1174 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1175 T1Misc<{0,0,1,0,1,0,?}> {
1184 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1185 // Expanded after instruction selection into a branch sequence.
1186 let usesCustomInserter = 1 in // Expanded after instruction selection.
1187 def tMOVCCr_pseudo :
1188 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1190 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1193 // 16-bit movcc in IT blocks for Thumb2.
1194 let neverHasSideEffects = 1 in {
1195 def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1196 "mov", "\t$Rdn, $Rm", []>,
1197 T1Special<{1,0,?,?}> {
1200 let Inst{7} = Rdn{3};
1202 let Inst{2-0} = Rdn{2-0};
1205 let isMoveImm = 1 in
1206 def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1207 "mov", "\t$Rdn, $Rm", []>,
1208 T1General<{1,0,0,?,?}> {
1211 let Inst{10-8} = Rdn;
1215 } // neverHasSideEffects
1217 // tLEApcrel - Load a pc-relative address into a register without offending the
1219 let neverHasSideEffects = 1, isReMaterializable = 1 in
1220 def tLEApcrel : T1I<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), IIC_iALUi,
1221 "adr${p}\t$Rd, #$label", []>,
1222 T1Encoding<{1,0,1,0,0,?}> {
1225 let Inst{10-8} = Rd;
1226 // FIXME: Add label encoding/fixup
1229 def tLEApcrelJT : T1I<(outs tGPR:$Rd),
1230 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1231 IIC_iALUi, "adr${p}\t$Rd, #${label}_${id}", []>,
1232 T1Encoding<{1,0,1,0,0,?}> {
1235 let Inst{10-8} = Rd;
1236 // FIXME: Add label encoding/fixup
1239 //===----------------------------------------------------------------------===//
1243 // __aeabi_read_tp preserves the registers r1-r3.
1244 let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1245 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1246 "bl\t__aeabi_read_tp",
1247 [(set R0, ARMthread_pointer)]> {
1248 // Encoding is 0xf7fffffe.
1249 let Inst = 0xf7fffffe;
1252 // SJLJ Exception handling intrinsics
1253 // eh_sjlj_setjmp() is an instruction sequence to store the return
1254 // address and save #0 in R0 for the non-longjmp case.
1255 // Since by its nature we may be coming from some other function to get
1256 // here, and we're using the stack frame for the containing function to
1257 // save/restore registers, we can't keep anything live in regs across
1258 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1259 // when we get here from a longjmp(). We force everthing out of registers
1260 // except for our own input by listing the relevant registers in Defs. By
1261 // doing so, we also cause the prologue/epilogue code to actively preserve
1262 // all of the callee-saved resgisters, which is exactly what we want.
1263 // $val is a scratch register for our use.
1264 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ],
1265 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1266 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1267 AddrModeNone, SizeSpecial, NoItinerary, "","",
1268 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1270 // FIXME: Non-Darwin version(s)
1271 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1272 Defs = [ R7, LR, SP ] in
1273 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1274 AddrModeNone, SizeSpecial, IndexModeNone,
1275 Pseudo, NoItinerary, "", "",
1276 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1277 Requires<[IsThumb, IsDarwin]>;
1279 //===----------------------------------------------------------------------===//
1280 // Non-Instruction Patterns
1284 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1285 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1286 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1287 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1288 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1289 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1291 // Subtract with carry
1292 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1293 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1294 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1295 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1296 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1297 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1299 // ConstantPool, GlobalAddress
1300 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1301 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1304 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1305 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1308 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1309 Requires<[IsThumb, IsNotDarwin]>;
1310 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1311 Requires<[IsThumb, IsDarwin]>;
1313 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1314 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1315 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1316 Requires<[IsThumb, HasV5T, IsDarwin]>;
1318 // Indirect calls to ARM routines
1319 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1320 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1321 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1322 Requires<[IsThumb, HasV5T, IsDarwin]>;
1324 // zextload i1 -> zextload i8
1325 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
1326 (tLDRB t_addrmode_s1:$addr)>;
1328 // extload -> zextload
1329 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1330 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1331 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
1333 // If it's impossible to use [r,r] address mode for sextload, select to
1334 // ldr{b|h} + sxt{b|h} instead.
1335 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1336 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1337 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1338 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1339 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1340 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1342 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1343 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1344 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1345 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1347 // Large immediate handling.
1350 def : T1Pat<(i32 thumb_immshifted:$src),
1351 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1352 (thumb_immshifted_shamt imm:$src))>;
1354 def : T1Pat<(i32 imm0_255_comp:$src),
1355 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1357 // Pseudo instruction that combines ldr from constpool and add pc. This should
1358 // be expanded into two instructions late to allow if-conversion and
1360 let isReMaterializable = 1 in
1361 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1363 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1365 Requires<[IsThumb, IsThumb1Only]>;