1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let ParserMatchClass = t_addrmode_rr_asm_operand;
124 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127 // t_addrmode_rrs := reg + reg
129 // We use separate scaled versions because the Select* functions need
130 // to explicitly check for a matching constant and return false here so that
131 // the reg+imm forms will match instead. This is a horrible way to do that,
132 // as it forces tight coupling between the methods, but it's how selectiondag
134 def t_addrmode_rrs1 : Operand<i32>,
135 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
136 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
137 let PrintMethod = "printThumbAddrModeRROperand";
138 let DecoderMethod = "DecodeThumbAddrModeRR";
139 let ParserMatchClass = t_addrmode_rr_asm_operand;
140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
142 def t_addrmode_rrs2 : Operand<i32>,
143 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
144 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
145 let DecoderMethod = "DecodeThumbAddrModeRR";
146 let PrintMethod = "printThumbAddrModeRROperand";
147 let ParserMatchClass = t_addrmode_rr_asm_operand;
148 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
150 def t_addrmode_rrs4 : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
152 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
153 let DecoderMethod = "DecodeThumbAddrModeRR";
154 let PrintMethod = "printThumbAddrModeRROperand";
155 let ParserMatchClass = t_addrmode_rr_asm_operand;
156 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
159 // t_addrmode_is4 := reg + imm5 * 4
161 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
162 def t_addrmode_is4 : Operand<i32>,
163 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
164 let EncoderMethod = "getAddrModeISOpValue";
165 let DecoderMethod = "DecodeThumbAddrModeIS";
166 let PrintMethod = "printThumbAddrModeImm5S4Operand";
167 let ParserMatchClass = t_addrmode_is4_asm_operand;
168 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171 // t_addrmode_is2 := reg + imm5 * 2
173 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
174 def t_addrmode_is2 : Operand<i32>,
175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
176 let EncoderMethod = "getAddrModeISOpValue";
177 let DecoderMethod = "DecodeThumbAddrModeIS";
178 let PrintMethod = "printThumbAddrModeImm5S2Operand";
179 let ParserMatchClass = t_addrmode_is2_asm_operand;
180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
183 // t_addrmode_is1 := reg + imm5
185 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
186 def t_addrmode_is1 : Operand<i32>,
187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
188 let EncoderMethod = "getAddrModeISOpValue";
189 let DecoderMethod = "DecodeThumbAddrModeIS";
190 let PrintMethod = "printThumbAddrModeImm5S1Operand";
191 let ParserMatchClass = t_addrmode_is1_asm_operand;
192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
195 // t_addrmode_sp := sp + imm8 * 4
197 // FIXME: This really shouldn't have an explicit SP operand at all. It should
198 // be implicit, just like in the instruction encoding itself.
199 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
200 def t_addrmode_sp : Operand<i32>,
201 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
202 let EncoderMethod = "getAddrModeThumbSPOpValue";
203 let DecoderMethod = "DecodeThumbAddrModeSP";
204 let PrintMethod = "printThumbAddrModeSPOperand";
205 let ParserMatchClass = t_addrmode_sp_asm_operand;
206 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
209 // t_addrmode_pc := <label> => pc + imm8 * 4
211 def t_addrmode_pc : Operand<i32> {
212 let EncoderMethod = "getAddrModePCOpValue";
213 let DecoderMethod = "DecodeThumbAddrModePC";
216 //===----------------------------------------------------------------------===//
217 // Miscellaneous Instructions.
220 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
221 // from removing one half of the matched pairs. That breaks PEI, which assumes
222 // these will always be in pairs, and asserts if it finds otherwise. Better way?
223 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
224 def tADJCALLSTACKUP :
225 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
226 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
227 Requires<[IsThumb, IsThumb1Only]>;
229 def tADJCALLSTACKDOWN :
230 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
231 [(ARMcallseq_start imm:$amt)]>,
232 Requires<[IsThumb, IsThumb1Only]>;
235 class T1SystemEncoding<bits<8> opc>
236 : T1Encoding<0b101111> {
237 let Inst{9-8} = 0b11;
241 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
242 T1SystemEncoding<0x00>, // A8.6.110
243 Requires<[IsThumb2]>;
245 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
246 T1SystemEncoding<0x10>; // A8.6.410
248 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
249 T1SystemEncoding<0x20>; // A8.6.408
251 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
252 T1SystemEncoding<0x30>; // A8.6.409
254 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
255 T1SystemEncoding<0x40>; // A8.6.157
257 // The imm operand $val can be used by a debugger to store more information
258 // about the breakpoint.
259 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
261 T1Encoding<0b101111> {
262 let Inst{9-8} = 0b10;
268 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
269 []>, T1Encoding<0b101101> {
272 let Inst{9-5} = 0b10010;
275 let Inst{2-0} = 0b000;
278 // Change Processor State is a system instruction -- for disassembly only.
279 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
280 NoItinerary, "cps$imod $iflags",
281 [/* For disassembly only; pattern left blank */]>,
289 let Inst{2-0} = iflags;
290 let DecoderMethod = "DecodeThumbCPS";
293 // For both thumb1 and thumb2.
294 let isNotDuplicable = 1, isCodeGenOnly = 1 in
295 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
296 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
297 T1Special<{0,0,?,?}> {
300 let Inst{6-3} = 0b1111; // Rm = pc
304 // ADD <Rd>, sp, #<imm8>
305 // This is rematerializable, which is particularly useful for taking the
306 // address of locals.
307 let isReMaterializable = 1 in
308 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm_s4:$rhs), IIC_iALUi,
309 "add", "\t$dst, $sp, $rhs", []>,
310 T1Encoding<{1,0,1,0,1,?}> {
314 let Inst{10-8} = dst;
316 let DecoderMethod = "DecodeThumbAddSpecialReg";
319 // ADD sp, sp, #<imm7>
320 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm_s4:$rhs),
321 IIC_iALUi, "add", "\t$Rdn, $rhs", []>,
322 T1Misc<{0,0,0,0,0,?,?}> {
326 let DecoderMethod = "DecodeThumbAddSPImm";
329 // SUB sp, sp, #<imm7>
330 // FIXME: The encoding and the ASM string don't match up.
331 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm_s4:$rhs),
332 IIC_iALUi, "sub", "\t$Rdn, $rhs", []>,
333 T1Misc<{0,0,0,0,1,?,?}> {
337 let DecoderMethod = "DecodeThumbAddSPImm";
341 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
342 "add", "\t$Rdn, $sp, $Rn", []>,
343 T1Special<{0,0,?,?}> {
344 // A8.6.9 Encoding T1
346 let Inst{7} = Rdn{3};
347 let Inst{6-3} = 0b1101;
348 let Inst{2-0} = Rdn{2-0};
349 let DecoderMethod = "DecodeThumbAddSPReg";
353 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$rhs), IIC_iALUr,
354 "add", "\t$Rdn, $rhs", []>,
355 T1Special<{0,0,?,?}> {
356 // A8.6.9 Encoding T2
360 let Inst{2-0} = 0b101;
361 let DecoderMethod = "DecodeThumbAddSPReg";
364 //===----------------------------------------------------------------------===//
365 // Control Flow Instructions.
369 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
370 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
371 T1Special<{1,1,0,?}> {
375 let Inst{2-0} = 0b000;
379 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
380 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
381 [(ARMretflag)], (tBX LR, pred:$p)>;
383 // Alternative return instruction used by vararg functions.
384 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
386 (tBX GPR:$Rm, pred:$p)>;
389 // All calls clobber the non-callee saved registers. SP is marked as a use to
390 // prevent stack-pointer assignments that appear immediately before calls from
391 // potentially appearing dead.
393 // On non-Darwin platforms R9 is callee-saved.
394 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
396 // Also used for Thumb2
397 def tBL : TIx2<0b11110, 0b11, 1,
398 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
400 [(ARMtcall tglobaladdr:$func)]>,
401 Requires<[IsThumb, IsNotDarwin]> {
403 let Inst{26} = func{21};
404 let Inst{25-16} = func{20-11};
407 let Inst{10-0} = func{10-0};
410 // ARMv5T and above, also used for Thumb2
411 def tBLXi : TIx2<0b11110, 0b11, 0,
412 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
414 [(ARMcall tglobaladdr:$func)]>,
415 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
417 let Inst{25-16} = func{20-11};
420 let Inst{10-1} = func{10-1};
421 let Inst{0} = 0; // func{0} is assumed zero
424 // Also used for Thumb2
425 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
427 [(ARMtcall GPR:$func)]>,
428 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
429 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
431 let Inst{6-3} = func;
432 let Inst{2-0} = 0b000;
436 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
438 [(ARMcall_nolink tGPR:$func)]>,
439 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
443 // On Darwin R9 is call-clobbered.
444 // R7 is marked as a use to prevent frame-pointer assignments from being
445 // moved above / below calls.
446 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
448 // Also used for Thumb2
449 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
450 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
451 (tBL pred:$p, t_bltarget:$func)>,
452 Requires<[IsThumb, IsDarwin]>;
454 // ARMv5T and above, also used for Thumb2
455 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
456 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
457 (tBLXi pred:$p, t_blxtarget:$func)>,
458 Requires<[IsThumb, HasV5T, IsDarwin]>;
460 // Also used for Thumb2
461 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
462 2, IIC_Br, [(ARMtcall GPR:$func)],
463 (tBLXr pred:$p, GPR:$func)>,
464 Requires<[IsThumb, HasV5T, IsDarwin]>;
467 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
469 [(ARMcall_nolink tGPR:$func)]>,
470 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
473 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
474 let isPredicable = 1 in
475 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
476 "b\t$target", [(br bb:$target)]>,
477 T1Encoding<{1,1,1,0,0,?}> {
479 let Inst{10-0} = target;
483 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
484 // the clobber of LR.
486 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
487 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
489 def tBR_JTr : tPseudoInst<(outs),
490 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
492 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
493 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
497 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
498 // a two-value operand where a dag node expects two operands. :(
499 let isBranch = 1, isTerminator = 1 in
500 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
502 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
503 T1BranchCond<{1,1,0,1}> {
507 let Inst{7-0} = target;
511 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
513 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
515 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
516 // on Darwin), so it's in ARMInstrThumb2.td.
517 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
519 (tBX GPR:$dst, (ops 14, zero_reg))>,
520 Requires<[IsThumb, IsDarwin]>;
522 // Non-Darwin versions (the difference is R9).
523 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
525 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
527 (tB t_brtarget:$dst)>,
528 Requires<[IsThumb, IsNotDarwin]>;
529 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
531 (tBX GPR:$dst, (ops 14, zero_reg))>,
532 Requires<[IsThumb, IsNotDarwin]>;
537 // A8.6.218 Supervisor Call (Software Interrupt)
538 // A8.6.16 B: Encoding T1
539 // If Inst{11-8} == 0b1111 then SEE SVC
540 let isCall = 1, Uses = [SP] in
541 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
542 "svc", "\t$imm", []>, Encoding16 {
544 let Inst{15-12} = 0b1101;
545 let Inst{11-8} = 0b1111;
549 // The assembler uses 0xDEFE for a trap instruction.
550 let isBarrier = 1, isTerminator = 1 in
551 def tTRAP : TI<(outs), (ins), IIC_Br,
552 "trap", [(trap)]>, Encoding16 {
556 //===----------------------------------------------------------------------===//
557 // Load Store Instructions.
560 // Loads: reg/reg and reg/imm5
561 let canFoldAsLoad = 1, isReMaterializable = 1 in
562 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
563 Operand AddrMode_r, Operand AddrMode_i,
564 AddrMode am, InstrItinClass itin_r,
565 InstrItinClass itin_i, string asm,
568 T1pILdStEncode<reg_opc,
569 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
570 am, itin_r, asm, "\t$Rt, $addr",
571 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
573 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
574 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
575 am, itin_i, asm, "\t$Rt, $addr",
576 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
578 // Stores: reg/reg and reg/imm5
579 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
580 Operand AddrMode_r, Operand AddrMode_i,
581 AddrMode am, InstrItinClass itin_r,
582 InstrItinClass itin_i, string asm,
585 T1pILdStEncode<reg_opc,
586 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
587 am, itin_r, asm, "\t$Rt, $addr",
588 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
590 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
591 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
592 am, itin_i, asm, "\t$Rt, $addr",
593 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
597 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
598 t_addrmode_is4, AddrModeT1_4,
599 IIC_iLoad_r, IIC_iLoad_i, "ldr",
600 UnOpFrag<(load node:$Src)>>;
603 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
604 t_addrmode_is1, AddrModeT1_1,
605 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
606 UnOpFrag<(zextloadi8 node:$Src)>>;
609 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
610 t_addrmode_is2, AddrModeT1_2,
611 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
612 UnOpFrag<(zextloadi16 node:$Src)>>;
614 let AddedComplexity = 10 in
615 def tLDRSB : // A8.6.80
616 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
617 AddrModeT1_1, IIC_iLoad_bh_r,
618 "ldrsb", "\t$Rt, $addr",
619 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
621 let AddedComplexity = 10 in
622 def tLDRSH : // A8.6.84
623 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
624 AddrModeT1_2, IIC_iLoad_bh_r,
625 "ldrsh", "\t$Rt, $addr",
626 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
628 let canFoldAsLoad = 1 in
629 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
630 "ldr", "\t$Rt, $addr",
631 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
636 let Inst{7-0} = addr;
640 // FIXME: Use ldr.n to work around a Darwin assembler bug.
641 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
642 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
643 "ldr", ".n\t$Rt, $addr",
644 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
645 T1Encoding<{0,1,0,0,1,?}> {
650 let Inst{7-0} = addr;
653 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
654 // For disassembly use only.
655 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
656 "ldr", "\t$Rt, $addr",
657 [/* disassembly only */]>,
658 T1Encoding<{0,1,0,0,1,?}> {
663 let Inst{7-0} = addr;
666 // A8.6.194 & A8.6.192
667 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
668 t_addrmode_is4, AddrModeT1_4,
669 IIC_iStore_r, IIC_iStore_i, "str",
670 BinOpFrag<(store node:$LHS, node:$RHS)>>;
672 // A8.6.197 & A8.6.195
673 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
674 t_addrmode_is1, AddrModeT1_1,
675 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
676 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
678 // A8.6.207 & A8.6.205
679 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
680 t_addrmode_is2, AddrModeT1_2,
681 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
682 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
685 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
686 "str", "\t$Rt, $addr",
687 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
692 let Inst{7-0} = addr;
695 //===----------------------------------------------------------------------===//
696 // Load / store multiple Instructions.
699 // These require base address to be written back or one of the loaded regs.
700 let neverHasSideEffects = 1 in {
702 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
703 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
704 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
708 let Inst{7-0} = regs;
711 // Writeback version is just a pseudo, as there's no encoding difference.
712 // Writeback happens iff the base register is not in the destination register
715 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
716 "$Rn = $wb", IIC_iLoad_mu>,
717 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
719 let OutOperandList = (outs GPR:$wb);
720 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
722 let isCodeGenOnly = 1;
724 list<Predicate> Predicates = [IsThumb];
727 // There is no non-writeback version of STM for Thumb.
728 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
729 def tSTMIA_UPD : T1I<(outs),
730 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
731 IIC_iStore_mu, "stm${p}\t$Rn!, $regs", []>,
732 T1Encoding<{1,1,0,0,0,?}> {
736 let Inst{7-0} = regs;
739 } // neverHasSideEffects
741 def : InstAlias<"ldm${p} $Rn!, $regs",
742 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
743 Requires<[IsThumb, IsThumb1Only]>;
745 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
746 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
748 "pop${p}\t$regs", []>,
749 T1Misc<{1,1,0,?,?,?,?}> {
751 let Inst{8} = regs{15};
752 let Inst{7-0} = regs{7-0};
755 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
756 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
758 "push${p}\t$regs", []>,
759 T1Misc<{0,1,0,?,?,?,?}> {
761 let Inst{8} = regs{14};
762 let Inst{7-0} = regs{7-0};
765 //===----------------------------------------------------------------------===//
766 // Arithmetic Instructions.
769 // Helper classes for encoding T1pI patterns:
770 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
771 string opc, string asm, list<dag> pattern>
772 : T1pI<oops, iops, itin, opc, asm, pattern>,
773 T1DataProcessing<opA> {
779 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
780 string opc, string asm, list<dag> pattern>
781 : T1pI<oops, iops, itin, opc, asm, pattern>,
789 // Helper classes for encoding T1sI patterns:
790 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
791 string opc, string asm, list<dag> pattern>
792 : T1sI<oops, iops, itin, opc, asm, pattern>,
793 T1DataProcessing<opA> {
799 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
800 string opc, string asm, list<dag> pattern>
801 : T1sI<oops, iops, itin, opc, asm, pattern>,
810 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
811 string opc, string asm, list<dag> pattern>
812 : T1sI<oops, iops, itin, opc, asm, pattern>,
820 // Helper classes for encoding T1sIt patterns:
821 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
822 string opc, string asm, list<dag> pattern>
823 : T1sIt<oops, iops, itin, opc, asm, pattern>,
824 T1DataProcessing<opA> {
830 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
831 string opc, string asm, list<dag> pattern>
832 : T1sIt<oops, iops, itin, opc, asm, pattern>,
836 let Inst{10-8} = Rdn;
837 let Inst{7-0} = imm8;
840 // Add with carry register
841 let isCommutable = 1, Uses = [CPSR] in
843 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
844 "adc", "\t$Rdn, $Rm",
845 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
848 def tADDi3 : // A8.6.4 T1
849 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
851 "add", "\t$Rd, $Rm, $imm3",
852 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
854 let Inst{8-6} = imm3;
857 def tADDi8 : // A8.6.4 T2
858 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
859 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
860 "add", "\t$Rdn, $imm8",
861 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
864 let isCommutable = 1 in
865 def tADDrr : // A8.6.6 T1
866 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
868 "add", "\t$Rd, $Rn, $Rm",
869 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
871 let neverHasSideEffects = 1 in
872 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
873 "add", "\t$Rdn, $Rm", []>,
874 T1Special<{0,0,?,?}> {
878 let Inst{7} = Rdn{3};
880 let Inst{2-0} = Rdn{2-0};
884 let isCommutable = 1 in
885 def tAND : // A8.6.12
886 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
888 "and", "\t$Rdn, $Rm",
889 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
892 def tASRri : // A8.6.14
893 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
895 "asr", "\t$Rd, $Rm, $imm5",
896 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
898 let Inst{10-6} = imm5;
902 def tASRrr : // A8.6.15
903 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
905 "asr", "\t$Rdn, $Rm",
906 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
909 def tBIC : // A8.6.20
910 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
912 "bic", "\t$Rdn, $Rm",
913 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
916 let isCompare = 1, Defs = [CPSR] in {
917 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
918 // Compare-to-zero still works out, just not the relationals
919 //def tCMN : // A8.6.33
920 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
922 // "cmn", "\t$lhs, $rhs",
923 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
925 def tCMNz : // A8.6.33
926 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
929 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
931 } // isCompare = 1, Defs = [CPSR]
934 let isCompare = 1, Defs = [CPSR] in {
935 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
936 "cmp", "\t$Rn, $imm8",
937 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
938 T1General<{1,0,1,?,?}> {
943 let Inst{7-0} = imm8;
947 def tCMPr : // A8.6.36 T1
948 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
951 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
953 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
954 "cmp", "\t$Rn, $Rm", []>,
955 T1Special<{0,1,?,?}> {
961 let Inst{2-0} = Rn{2-0};
963 } // isCompare = 1, Defs = [CPSR]
967 let isCommutable = 1 in
968 def tEOR : // A8.6.45
969 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
971 "eor", "\t$Rdn, $Rm",
972 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
975 def tLSLri : // A8.6.88
976 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
978 "lsl", "\t$Rd, $Rm, $imm5",
979 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
981 let Inst{10-6} = imm5;
985 def tLSLrr : // A8.6.89
986 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
988 "lsl", "\t$Rdn, $Rm",
989 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
992 def tLSRri : // A8.6.90
993 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
995 "lsr", "\t$Rd, $Rm, $imm5",
996 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
998 let Inst{10-6} = imm5;
1002 def tLSRrr : // A8.6.91
1003 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1005 "lsr", "\t$Rdn, $Rm",
1006 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1009 let isMoveImm = 1 in
1010 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1011 "mov", "\t$Rd, $imm8",
1012 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1013 T1General<{1,0,0,?,?}> {
1017 let Inst{10-8} = Rd;
1018 let Inst{7-0} = imm8;
1020 // Because we have an explicit tMOVSr below, we need an alias to handle
1021 // the immediate "movs" form here. Blech.
1022 def : tInstAlias <"movs $Rdn, $imm",
1023 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1025 // A7-73: MOV(2) - mov setting flag.
1027 let neverHasSideEffects = 1 in {
1028 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1030 "mov", "\t$Rd, $Rm", "", []>,
1031 T1Special<{1,0,?,?}> {
1035 let Inst{7} = Rd{3};
1037 let Inst{2-0} = Rd{2-0};
1039 let Defs = [CPSR] in
1040 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1041 "movs\t$Rd, $Rm", []>, Encoding16 {
1045 let Inst{15-6} = 0b0000000000;
1049 } // neverHasSideEffects
1051 // Multiply register
1052 let isCommutable = 1 in
1053 def tMUL : // A8.6.105 T1
1054 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1055 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1056 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1057 T1DataProcessing<0b1101> {
1062 let AsmMatchConverter = "cvtThumbMultiply";
1065 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1068 // Move inverse register
1069 def tMVN : // A8.6.107
1070 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1071 "mvn", "\t$Rd, $Rn",
1072 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1074 // Bitwise or register
1075 let isCommutable = 1 in
1076 def tORR : // A8.6.114
1077 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1079 "orr", "\t$Rdn, $Rm",
1080 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1083 def tREV : // A8.6.134
1084 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1086 "rev", "\t$Rd, $Rm",
1087 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1088 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1090 def tREV16 : // A8.6.135
1091 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1093 "rev16", "\t$Rd, $Rm",
1094 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1095 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1097 def tREVSH : // A8.6.136
1098 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1100 "revsh", "\t$Rd, $Rm",
1101 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1102 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1104 // Rotate right register
1105 def tROR : // A8.6.139
1106 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1108 "ror", "\t$Rdn, $Rm",
1109 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1112 def tRSB : // A8.6.141
1113 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1115 "rsb", "\t$Rd, $Rn, #0",
1116 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1118 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1119 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1121 // Subtract with carry register
1122 let Uses = [CPSR] in
1123 def tSBC : // A8.6.151
1124 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1126 "sbc", "\t$Rdn, $Rm",
1127 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1129 // Subtract immediate
1130 def tSUBi3 : // A8.6.210 T1
1131 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1133 "sub", "\t$Rd, $Rm, $imm3",
1134 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1136 let Inst{8-6} = imm3;
1139 def tSUBi8 : // A8.6.210 T2
1140 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1142 "sub", "\t$Rdn, $imm8",
1143 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1145 // Subtract register
1146 def tSUBrr : // A8.6.212
1147 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1149 "sub", "\t$Rd, $Rn, $Rm",
1150 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1153 def tSXTB : // A8.6.222
1154 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1156 "sxtb", "\t$Rd, $Rm",
1157 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1158 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1160 // Sign-extend short
1161 def tSXTH : // A8.6.224
1162 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1164 "sxth", "\t$Rd, $Rm",
1165 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1166 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1169 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1170 def tTST : // A8.6.230
1171 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1172 "tst", "\t$Rn, $Rm",
1173 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1176 def tUXTB : // A8.6.262
1177 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1179 "uxtb", "\t$Rd, $Rm",
1180 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1181 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1183 // Zero-extend short
1184 def tUXTH : // A8.6.264
1185 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1187 "uxth", "\t$Rd, $Rm",
1188 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1189 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1191 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1192 // Expanded after instruction selection into a branch sequence.
1193 let usesCustomInserter = 1 in // Expanded after instruction selection.
1194 def tMOVCCr_pseudo :
1195 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1197 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1199 // tLEApcrel - Load a pc-relative address into a register without offending the
1202 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1203 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1204 T1Encoding<{1,0,1,0,0,?}> {
1207 let Inst{10-8} = Rd;
1208 let Inst{7-0} = addr;
1209 let DecoderMethod = "DecodeThumbAddSpecialReg";
1212 let neverHasSideEffects = 1, isReMaterializable = 1 in
1213 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1216 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1217 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1220 //===----------------------------------------------------------------------===//
1224 // __aeabi_read_tp preserves the registers r1-r3.
1225 // This is a pseudo inst so that we can get the encoding right,
1226 // complete with fixup for the aeabi_read_tp function.
1227 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1228 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1229 [(set R0, ARMthread_pointer)]>;
1231 //===----------------------------------------------------------------------===//
1232 // SJLJ Exception handling intrinsics
1235 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1236 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1237 // from some other function to get here, and we're using the stack frame for the
1238 // containing function to save/restore registers, we can't keep anything live in
1239 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1240 // tromped upon when we get here from a longjmp(). We force everything out of
1241 // registers except for our own input by listing the relevant registers in
1242 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1243 // preserve all of the callee-saved resgisters, which is exactly what we want.
1244 // $val is a scratch register for our use.
1245 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1246 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1247 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1248 AddrModeNone, 0, NoItinerary, "","",
1249 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1251 // FIXME: Non-Darwin version(s)
1252 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1253 Defs = [ R7, LR, SP ] in
1254 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1255 AddrModeNone, 0, IndexModeNone,
1256 Pseudo, NoItinerary, "", "",
1257 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1258 Requires<[IsThumb, IsDarwin]>;
1260 //===----------------------------------------------------------------------===//
1261 // Non-Instruction Patterns
1265 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1266 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1267 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1268 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1271 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1272 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1273 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1274 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1275 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1276 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1278 // Subtract with carry
1279 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1280 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1281 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1282 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1283 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1284 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1286 // ConstantPool, GlobalAddress
1287 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1288 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1291 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1292 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1295 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1296 Requires<[IsThumb, IsNotDarwin]>;
1297 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1298 Requires<[IsThumb, IsDarwin]>;
1300 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1301 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1302 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1303 Requires<[IsThumb, HasV5T, IsDarwin]>;
1305 // Indirect calls to ARM routines
1306 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1307 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1308 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1309 Requires<[IsThumb, HasV5T, IsDarwin]>;
1311 // zextload i1 -> zextload i8
1312 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1313 (tLDRBr t_addrmode_rrs1:$addr)>;
1314 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1315 (tLDRBi t_addrmode_is1:$addr)>;
1317 // extload -> zextload
1318 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1319 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1320 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1321 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1322 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1323 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1325 // If it's impossible to use [r,r] address mode for sextload, select to
1326 // ldr{b|h} + sxt{b|h} instead.
1327 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1328 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1329 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1330 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1331 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1332 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1333 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1334 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1335 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1336 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1337 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1338 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1340 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1341 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1342 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1343 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1344 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1345 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1346 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1347 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1349 // Large immediate handling.
1352 def : T1Pat<(i32 thumb_immshifted:$src),
1353 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1354 (thumb_immshifted_shamt imm:$src))>;
1356 def : T1Pat<(i32 imm0_255_comp:$src),
1357 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1359 // Pseudo instruction that combines ldr from constpool and add pc. This should
1360 // be expanded into two instructions late to allow if-conversion and
1362 let isReMaterializable = 1 in
1363 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1365 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1367 Requires<[IsThumb, IsThumb1Only]>;
1369 // Pseudo-instruction for merged POP and return.
1370 // FIXME: remove when we have a way to marking a MI with these properties.
1371 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1372 hasExtraDefRegAllocReq = 1 in
1373 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1375 (tPOP pred:$p, reglist:$regs)>;
1377 // Indirect branch using "mov pc, $Rm"
1378 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1379 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1380 2, IIC_Br, [(brind GPR:$Rm)],
1381 (tMOVr PC, GPR:$Rm, pred:$p)>;
1385 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1386 // encoding is available on ARMv6K, but we don't differentiate that finely.
1387 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;