1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
136 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
137 "add $dst, pc, $rhs * 4", []>;
140 // FIXME: hard code sp?
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
142 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
145 // FIXME: hard code sp?
146 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
147 "add $dst, $rhs * 4", []>;
149 // FIXME: Make use of the following?
153 //===----------------------------------------------------------------------===//
154 // Control Flow Instructions.
157 let isReturn = 1, isTerminator = 1 in {
158 def tBX_RET : T1I<(outs), (ins), "bx lr", [(ARMretflag)]>;
159 // Alternative return instruction used by vararg functions.
160 def tBX_RET_vararg : T1I<(outs), (ins tGPR:$target), "bx $target", []>;
163 // FIXME: remove when we have a way to marking a MI with these properties.
164 let isReturn = 1, isTerminator = 1 in
165 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
169 Defs = [R0, R1, R2, R3, LR,
170 D0, D1, D2, D3, D4, D5, D6, D7] in {
171 def tBL : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
173 [(ARMtcall tglobaladdr:$func)]>;
175 def tBLXi : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
177 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
178 def tBLXr : T1I<(outs), (ins tGPR:$func, variable_ops),
180 [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
182 def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
183 "cpy lr, pc\n\tbx $func",
184 [(ARMcall_nolink tGPR:$func)]>;
187 let isBranch = 1, isTerminator = 1 in {
188 let isBarrier = 1 in {
189 let isPredicable = 1 in
190 def tB : T1I<(outs), (ins brtarget:$target), "b $target",
194 def tBfar : T1Ix2<(outs), (ins brtarget:$target),
195 "bl $target\t@ far jump",[]>;
197 def tBR_JTr : T1JTI<(outs),
198 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
199 "cpy pc, $target \n\t.align\t2\n$jt",
200 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
204 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
205 // a two-value operand where a dag node expects two operands. :(
206 let isBranch = 1, isTerminator = 1 in
207 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
208 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
210 //===----------------------------------------------------------------------===//
211 // Load Store Instructions.
214 let canFoldAsLoad = 1 in
215 def tLDR : T1I4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
217 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
219 def tLDRB : T1I1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
221 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
223 def tLDRH : T1I2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
225 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
227 def tLDRSB : T1I1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
229 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
231 def tLDRSH : T1I2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
233 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
235 let canFoldAsLoad = 1 in
236 def tLDRspi : T1Is<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
238 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
240 // Special instruction for restore. It cannot clobber condition register
241 // when it's expanded by eliminateCallFramePseudoInstr().
242 let canFoldAsLoad = 1, mayLoad = 1 in
243 def tRestore : T1Is<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
244 "ldr $dst, $addr", []>;
247 let canFoldAsLoad = 1 in
248 def tLDRpci : T1Is<(outs tGPR:$dst), (ins i32imm:$addr),
250 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
252 // Special LDR for loads from non-pc-relative constpools.
253 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
254 def tLDRcp : T1Is<(outs tGPR:$dst), (ins i32imm:$addr),
255 "ldr $dst, $addr", []>;
257 def tSTR : T1I4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
259 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
261 def tSTRB : T1I1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
263 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
265 def tSTRH : T1I2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
267 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
269 def tSTRspi : T1Is<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
271 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
273 let mayStore = 1 in {
274 // Special instruction for spill. It cannot clobber condition register
275 // when it's expanded by eliminateCallFramePseudoInstr().
276 def tSpill : T1Is<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
277 "str $src, $addr", []>;
280 //===----------------------------------------------------------------------===//
281 // Load / store multiple Instructions.
284 // TODO: A7-44: LDMIA - load multiple
287 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
291 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
294 //===----------------------------------------------------------------------===//
295 // Arithmetic Instructions.
298 // Add with carry register
299 let isCommutable = 1, Defs = [CPSR], Uses = [CPSR] in
300 def tADCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
302 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
306 def tADDi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
307 "add $dst, $lhs, $rhs",
308 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
311 def tADDi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
313 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
316 let isCommutable = 1, Defs = [CPSR] in
317 def tADDrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
318 "add $dst, $lhs, $rhs",
319 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
321 let neverHasSideEffects = 1 in
322 def tADDhirr : T1It<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
323 "add $dst, $rhs @ addhirr", []>;
326 let isCommutable = 1, Defs = [CPSR] in
327 def tAND : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
329 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
333 def tASRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
334 "asr $dst, $lhs, $rhs",
335 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
339 def tASRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
341 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
345 def tBIC : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
347 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
350 let Defs = [CPSR] in {
351 def tCMN : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
353 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
354 def tCMNZ : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
356 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
360 let Defs = [CPSR] in {
361 def tCMPi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
363 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
364 def tCMPZi8 : T1I<(outs), (ins tGPR:$lhs, i32imm:$rhs),
366 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
371 let Defs = [CPSR] in {
372 def tCMPr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
374 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
375 def tCMPZr : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
377 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
380 // TODO: A7-37: CMP(3) - cmp hi regs
383 let isCommutable = 1, Defs = [CPSR] in
384 def tEOR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
386 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
390 def tLSLri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
391 "lsl $dst, $lhs, $rhs",
392 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
396 def tLSLrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
398 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
402 def tLSRri : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
403 "lsr $dst, $lhs, $rhs",
404 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
408 def tLSRrr : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
410 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
414 def tMOVi8 : T1I<(outs tGPR:$dst), (ins i32imm:$src),
416 [(set tGPR:$dst, imm0_255:$src)]>;
418 // TODO: A7-73: MOV(2) - mov setting flag.
421 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
422 // which is MOV(3). This also supports high registers.
423 let neverHasSideEffects = 1 in {
424 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
425 "cpy $dst, $src", []>;
426 def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src),
427 "cpy $dst, $src\t@ hir2lor", []>;
428 def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src),
429 "cpy $dst, $src\t@ lor2hir", []>;
430 def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
431 "cpy $dst, $src\t@ hir2hir", []>;
432 } // neverHasSideEffects
435 let isCommutable = 1, Defs = [CPSR] in
436 def tMUL : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
438 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
440 // move inverse register
442 def tMVN : T1I<(outs tGPR:$dst), (ins tGPR:$src),
444 [(set tGPR:$dst, (not tGPR:$src))]>;
448 def tNEG : T1I<(outs tGPR:$dst), (ins tGPR:$src),
450 [(set tGPR:$dst, (ineg tGPR:$src))]>;
452 // bitwise or register
453 let isCommutable = 1, Defs = [CPSR] in
454 def tORR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
456 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
459 def tREV : T1I<(outs tGPR:$dst), (ins tGPR:$src),
461 [(set tGPR:$dst, (bswap tGPR:$src))]>,
462 Requires<[IsThumb1Only, HasV6]>;
464 def tREV16 : T1I<(outs tGPR:$dst), (ins tGPR:$src),
467 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
468 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
469 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
470 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
471 Requires<[IsThumb1Only, HasV6]>;
473 def tREVSH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
477 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
478 (shl tGPR:$src, (i32 8))), i16))]>,
479 Requires<[IsThumb1Only, HasV6]>;
481 // rotate right register
483 def tROR : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
485 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
487 // Subtract with carry register
488 let Defs = [CPSR], Uses = [CPSR] in
489 def tSBCS : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
491 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
493 // Subtract immediate
495 def tSUBi3 : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
496 "sub $dst, $lhs, $rhs",
497 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
500 def tSUBi8 : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
502 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
506 def tSUBrr : T1I<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
507 "sub $dst, $lhs, $rhs",
508 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
510 // TODO: A7-96: STMIA - store multiple.
512 def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
513 "sub $dst, $rhs * 4", []>;
516 def tSXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
518 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
519 Requires<[IsThumb1Only, HasV6]>;
522 def tSXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
524 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
525 Requires<[IsThumb1Only, HasV6]>;
528 let isCommutable = 1, Defs = [CPSR] in
529 def tTST : T1I<(outs), (ins tGPR:$lhs, tGPR:$rhs),
531 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
534 def tUXTB : T1I<(outs tGPR:$dst), (ins tGPR:$src),
536 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
537 Requires<[IsThumb1Only, HasV6]>;
540 def tUXTH : T1I<(outs tGPR:$dst), (ins tGPR:$src),
542 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
543 Requires<[IsThumb1Only, HasV6]>;
546 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
547 // Expanded by the scheduler into a branch sequence.
548 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
550 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
552 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
554 // tLEApcrel - Load a pc-relative address into a register without offending the
556 def tLEApcrel : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label),
557 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
558 "${:private}PCRELL${:uid}+4))\n"),
559 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
560 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
563 def tLEApcrelJT : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
564 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
565 "${:private}PCRELL${:uid}+4))\n"),
566 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
567 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
570 //===----------------------------------------------------------------------===//
574 // __aeabi_read_tp preserves the registers r1-r3.
577 def tTPsoft : T1Ix2<(outs), (ins),
578 "bl __aeabi_read_tp",
579 [(set R0, ARMthread_pointer)]>;
582 //===----------------------------------------------------------------------===//
583 // Non-Instruction Patterns
587 def : TPat<(addc tGPR:$lhs, imm0_7:$rhs),
588 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
589 def : TPat<(addc tGPR:$lhs, imm8_255:$rhs),
590 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
591 def : TPat<(addc tGPR:$lhs, tGPR:$rhs),
592 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
594 // Subtract with carry
595 def : TPat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
596 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
597 def : TPat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
598 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
599 def : TPat<(subc tGPR:$lhs, tGPR:$rhs),
600 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
602 // ConstantPool, GlobalAddress
603 def : TPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
604 def : TPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
607 def : TPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
608 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
611 def : TPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
612 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
614 // Indirect calls to ARM routines
615 def : Tv5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
617 // zextload i1 -> zextload i8
618 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
619 (tLDRB t_addrmode_s1:$addr)>;
621 // extload -> zextload
622 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
623 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
624 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
626 // Large immediate handling.
629 def : T1Pat<(i32 thumb_immshifted:$src),
630 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
631 (thumb_immshifted_shamt imm:$src))>;
633 def : T1Pat<(i32 imm0_255_comp:$src),
634 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;