1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : ImmLeaf<i32, [{
31 return Imm >= 0 && Imm < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; }
38 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
39 let ParserMatchClass = imm0_255_asmoperand;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : ImmLeaf<i32, [{
46 return Imm >= 8 && Imm < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift. This uses
54 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
55 // to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // ADR instruction labels.
71 def t_adrlabel : Operand<i32> {
72 let EncoderMethod = "getThumbAdrLabelOpValue";
75 // Scaled 4 immediate.
76 def t_imm_s4 : Operand<i32> {
77 let PrintMethod = "printThumbS4ImmOperand";
80 // Define Thumb specific addressing modes.
82 def t_brtarget : Operand<OtherVT> {
83 let EncoderMethod = "getThumbBRTargetOpValue";
86 def t_bcctarget : Operand<i32> {
87 let EncoderMethod = "getThumbBCCTargetOpValue";
90 def t_cbtarget : Operand<i32> {
91 let EncoderMethod = "getThumbCBTargetOpValue";
94 def t_bltarget : Operand<i32> {
95 let EncoderMethod = "getThumbBLTargetOpValue";
98 def t_blxtarget : Operand<i32> {
99 let EncoderMethod = "getThumbBLXTargetOpValue";
102 def MemModeRegThumbAsmOperand : AsmOperandClass {
103 let Name = "MemModeRegThumb";
104 let SuperClasses = [];
107 def MemModeImmThumbAsmOperand : AsmOperandClass {
108 let Name = "MemModeImmThumb";
109 let SuperClasses = [];
112 // t_addrmode_rr := reg + reg
114 def t_addrmode_rr : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
116 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
117 let PrintMethod = "printThumbAddrModeRROperand";
118 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
121 // t_addrmode_rrs := reg + reg
123 def t_addrmode_rrs1 : Operand<i32>,
124 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
125 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
126 let PrintMethod = "printThumbAddrModeRROperand";
127 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
128 let ParserMatchClass = MemModeRegThumbAsmOperand;
130 def t_addrmode_rrs2 : Operand<i32>,
131 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
132 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
133 let PrintMethod = "printThumbAddrModeRROperand";
134 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
135 let ParserMatchClass = MemModeRegThumbAsmOperand;
137 def t_addrmode_rrs4 : Operand<i32>,
138 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
139 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
140 let PrintMethod = "printThumbAddrModeRROperand";
141 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
142 let ParserMatchClass = MemModeRegThumbAsmOperand;
145 // t_addrmode_is4 := reg + imm5 * 4
147 def t_addrmode_is4 : Operand<i32>,
148 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
149 let EncoderMethod = "getAddrModeISOpValue";
150 let PrintMethod = "printThumbAddrModeImm5S4Operand";
151 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
152 let ParserMatchClass = MemModeImmThumbAsmOperand;
155 // t_addrmode_is2 := reg + imm5 * 2
157 def t_addrmode_is2 : Operand<i32>,
158 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
159 let EncoderMethod = "getAddrModeISOpValue";
160 let PrintMethod = "printThumbAddrModeImm5S2Operand";
161 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
162 let ParserMatchClass = MemModeImmThumbAsmOperand;
165 // t_addrmode_is1 := reg + imm5
167 def t_addrmode_is1 : Operand<i32>,
168 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
169 let EncoderMethod = "getAddrModeISOpValue";
170 let PrintMethod = "printThumbAddrModeImm5S1Operand";
171 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
172 let ParserMatchClass = MemModeImmThumbAsmOperand;
175 // t_addrmode_sp := sp + imm8 * 4
177 def t_addrmode_sp : Operand<i32>,
178 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
179 let EncoderMethod = "getAddrModeThumbSPOpValue";
180 let PrintMethod = "printThumbAddrModeSPOperand";
181 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
182 let ParserMatchClass = MemModeImmThumbAsmOperand;
185 // t_addrmode_pc := <label> => pc + imm8 * 4
187 def t_addrmode_pc : Operand<i32> {
188 let EncoderMethod = "getAddrModePCOpValue";
189 let ParserMatchClass = MemModeImmThumbAsmOperand;
192 //===----------------------------------------------------------------------===//
193 // Miscellaneous Instructions.
196 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
197 // from removing one half of the matched pairs. That breaks PEI, which assumes
198 // these will always be in pairs, and asserts if it finds otherwise. Better way?
199 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
200 def tADJCALLSTACKUP :
201 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
202 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
203 Requires<[IsThumb, IsThumb1Only]>;
205 def tADJCALLSTACKDOWN :
206 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
207 [(ARMcallseq_start imm:$amt)]>,
208 Requires<[IsThumb, IsThumb1Only]>;
211 // T1Disassembly - A simple class to make encoding some disassembly patterns
212 // easier and less verbose.
213 class T1Disassembly<bits<2> op1, bits<8> op2>
214 : T1Encoding<0b101111> {
219 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
220 [/* For disassembly only; pattern left blank */]>,
221 T1Disassembly<0b11, 0x00>; // A8.6.110
223 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
224 [/* For disassembly only; pattern left blank */]>,
225 T1Disassembly<0b11, 0x10>; // A8.6.410
227 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
228 [/* For disassembly only; pattern left blank */]>,
229 T1Disassembly<0b11, 0x20>; // A8.6.408
231 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
232 [/* For disassembly only; pattern left blank */]>,
233 T1Disassembly<0b11, 0x30>; // A8.6.409
235 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
236 [/* For disassembly only; pattern left blank */]>,
237 T1Disassembly<0b11, 0x40>; // A8.6.157
239 // The i32imm operand $val can be used by a debugger to store more information
240 // about the breakpoint.
241 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
242 [/* For disassembly only; pattern left blank */]>,
243 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
249 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
250 [/* For disassembly only; pattern left blank */]>,
251 T1Encoding<0b101101> {
253 let Inst{9-5} = 0b10010;
255 let Inst{3} = 1; // Big-Endian
256 let Inst{2-0} = 0b000;
259 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
260 [/* For disassembly only; pattern left blank */]>,
261 T1Encoding<0b101101> {
263 let Inst{9-5} = 0b10010;
265 let Inst{3} = 0; // Little-Endian
266 let Inst{2-0} = 0b000;
269 // Change Processor State is a system instruction -- for disassembly only.
270 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
271 NoItinerary, "cps$imod $iflags",
272 [/* For disassembly only; pattern left blank */]>,
280 let Inst{2-0} = iflags;
283 // For both thumb1 and thumb2.
284 let isNotDuplicable = 1, isCodeGenOnly = 1 in
285 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
286 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
287 T1Special<{0,0,?,?}> {
290 let Inst{6-3} = 0b1111; // Rm = pc
294 // PC relative add (ADR).
295 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
296 "add\t$dst, pc, $rhs", []>,
297 T1Encoding<{1,0,1,0,0,?}> {
301 let Inst{10-8} = dst;
305 // ADD <Rd>, sp, #<imm8>
306 // This is rematerializable, which is particularly useful for taking the
307 // address of locals.
308 let isReMaterializable = 1 in
309 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
310 "add\t$dst, $sp, $rhs", []>,
311 T1Encoding<{1,0,1,0,1,?}> {
315 let Inst{10-8} = dst;
319 // ADD sp, sp, #<imm7>
320 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
321 "add\t$dst, $rhs", []>,
322 T1Misc<{0,0,0,0,0,?,?}> {
328 // SUB sp, sp, #<imm7>
329 // FIXME: The encoding and the ASM string don't match up.
330 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
331 "sub\t$dst, $rhs", []>,
332 T1Misc<{0,0,0,0,1,?,?}> {
339 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
340 "add\t$dst, $rhs", []>,
341 T1Special<{0,0,?,?}> {
342 // A8.6.9 Encoding T1
344 let Inst{7} = dst{3};
345 let Inst{6-3} = 0b1101;
346 let Inst{2-0} = dst{2-0};
350 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
351 "add\t$dst, $rhs", []>,
352 T1Special<{0,0,?,?}> {
353 // A8.6.9 Encoding T2
357 let Inst{2-0} = 0b101;
360 //===----------------------------------------------------------------------===//
361 // Control Flow Instructions.
364 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
365 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
367 T1Special<{1,1,0,?}> {
369 let Inst{6-3} = 0b1110; // Rm = lr
370 let Inst{2-0} = 0b000;
373 // Alternative return instruction used by vararg functions.
374 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
377 T1Special<{1,1,0,?}> {
381 let Inst{2-0} = 0b000;
386 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
387 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
388 T1Special<{1,1,0,?}> {
392 let Inst{2-0} = 0b000;
395 def tBRIND : TI<(outs), (ins GPR:$Rm),
399 T1Special<{1,0,?,?}> {
402 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
404 let Inst{2-0} = 0b111;
408 // FIXME: remove when we have a way to marking a MI with these properties.
409 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
410 hasExtraDefRegAllocReq = 1 in
411 def tPOP_RET : tPseudoInst<(outs), (ins pred:$p, reglist:$regs, variable_ops),
412 Size2Bytes, IIC_iPop_Br, []>;
414 // All calls clobber the non-callee saved registers. SP is marked as a use to
415 // prevent stack-pointer assignments that appear immediately before calls from
416 // potentially appearing dead.
418 // On non-Darwin platforms R9 is callee-saved.
419 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
421 // Also used for Thumb2
422 def tBL : TIx2<0b11110, 0b11, 1,
423 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
425 [(ARMtcall tglobaladdr:$func)]>,
426 Requires<[IsThumb, IsNotDarwin]> {
428 let Inst{25-16} = func{20-11};
431 let Inst{10-0} = func{10-0};
434 // ARMv5T and above, also used for Thumb2
435 def tBLXi : TIx2<0b11110, 0b11, 0,
436 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
438 [(ARMcall tglobaladdr:$func)]>,
439 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
441 let Inst{25-16} = func{20-11};
444 let Inst{10-1} = func{10-1};
445 let Inst{0} = 0; // func{0} is assumed zero
448 // Also used for Thumb2
449 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
451 [(ARMtcall GPR:$func)]>,
452 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
453 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
455 let Inst{6-3} = func;
456 let Inst{2-0} = 0b000;
460 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
462 [(ARMcall_nolink tGPR:$func)]>,
463 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
467 // On Darwin R9 is call-clobbered.
468 // R7 is marked as a use to prevent frame-pointer assignments from being
469 // moved above / below calls.
470 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
472 // Also used for Thumb2
473 def tBLr9 : TIx2<0b11110, 0b11, 1,
474 (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
475 IIC_Br, "bl${p}\t$func",
476 [(ARMtcall tglobaladdr:$func)]>,
477 Requires<[IsThumb, IsDarwin]> {
479 let Inst{25-16} = func{20-11};
482 let Inst{10-0} = func{10-0};
485 // ARMv5T and above, also used for Thumb2
486 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
487 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
488 IIC_Br, "blx${p}\t$func",
489 [(ARMcall tglobaladdr:$func)]>,
490 Requires<[IsThumb, HasV5T, IsDarwin]> {
492 let Inst{25-16} = func{20-11};
495 let Inst{10-1} = func{10-1};
496 let Inst{0} = 0; // func{0} is assumed zero
499 // Also used for Thumb2
500 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
502 [(ARMtcall GPR:$func)]>,
503 Requires<[IsThumb, HasV5T, IsDarwin]>,
504 T1Special<{1,1,1,?}> {
507 let Inst{6-3} = func;
508 let Inst{2-0} = 0b000;
512 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
514 [(ARMcall_nolink tGPR:$func)]>,
515 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
518 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
519 let isPredicable = 1 in
520 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
521 "b\t$target", [(br bb:$target)]>,
522 T1Encoding<{1,1,1,0,0,?}> {
524 let Inst{10-0} = target;
528 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
529 // the clobber of LR.
531 def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
532 Size4Bytes, IIC_Br, []>;
534 def tBR_JTr : tPseudoInst<(outs),
535 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
537 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
538 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
542 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
543 // a two-value operand where a dag node expects two operands. :(
544 let isBranch = 1, isTerminator = 1 in
545 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
547 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
548 T1BranchCond<{1,1,0,1}> {
552 let Inst{7-0} = target;
555 // Compare and branch on zero / non-zero
556 let isBranch = 1, isTerminator = 1 in {
557 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
558 "cbz\t$Rn, $target", []>,
559 T1Misc<{0,0,?,1,?,?,?}> {
563 let Inst{9} = target{5};
564 let Inst{7-3} = target{4-0};
568 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
569 "cbnz\t$cmp, $target", []>,
570 T1Misc<{1,0,?,1,?,?,?}> {
574 let Inst{9} = target{5};
575 let Inst{7-3} = target{4-0};
580 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
581 // A8.6.16 B: Encoding T1
582 // If Inst{11-8} == 0b1111 then SEE SVC
583 let isCall = 1, Uses = [SP] in
584 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
585 "svc", "\t$imm", []>, Encoding16 {
587 let Inst{15-12} = 0b1101;
588 let Inst{11-8} = 0b1111;
592 // The assembler uses 0xDEFE for a trap instruction.
593 let isBarrier = 1, isTerminator = 1 in
594 def tTRAP : TI<(outs), (ins), IIC_Br,
595 "trap", [(trap)]>, Encoding16 {
599 //===----------------------------------------------------------------------===//
600 // Load Store Instructions.
603 // Loads: reg/reg and reg/imm5
604 let canFoldAsLoad = 1, isReMaterializable = 1 in
605 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
606 Operand AddrMode_r, Operand AddrMode_i,
607 AddrMode am, InstrItinClass itin_r,
608 InstrItinClass itin_i, string asm,
611 T1pILdStEncode<reg_opc,
612 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
613 am, itin_r, asm, "\t$Rt, $addr",
614 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
616 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
617 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
618 am, itin_i, asm, "\t$Rt, $addr",
619 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
621 // Stores: reg/reg and reg/imm5
622 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
623 Operand AddrMode_r, Operand AddrMode_i,
624 AddrMode am, InstrItinClass itin_r,
625 InstrItinClass itin_i, string asm,
628 T1pILdStEncode<reg_opc,
629 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
630 am, itin_r, asm, "\t$Rt, $addr",
631 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
633 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
634 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
635 am, itin_i, asm, "\t$Rt, $addr",
636 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
640 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
641 t_addrmode_is4, AddrModeT1_4,
642 IIC_iLoad_r, IIC_iLoad_i, "ldr",
643 UnOpFrag<(load node:$Src)>>;
646 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
647 t_addrmode_is1, AddrModeT1_1,
648 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
649 UnOpFrag<(zextloadi8 node:$Src)>>;
652 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
653 t_addrmode_is2, AddrModeT1_2,
654 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
655 UnOpFrag<(zextloadi16 node:$Src)>>;
657 let AddedComplexity = 10 in
658 def tLDRSB : // A8.6.80
659 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
660 AddrModeT1_1, IIC_iLoad_bh_r,
661 "ldrsb", "\t$dst, $addr",
662 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
664 let AddedComplexity = 10 in
665 def tLDRSH : // A8.6.84
666 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
667 AddrModeT1_2, IIC_iLoad_bh_r,
668 "ldrsh", "\t$dst, $addr",
669 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
671 let canFoldAsLoad = 1 in
672 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
673 "ldr", "\t$Rt, $addr",
674 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
679 let Inst{7-0} = addr;
683 // FIXME: Use ldr.n to work around a Darwin assembler bug.
684 let canFoldAsLoad = 1, isReMaterializable = 1 in
685 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
686 "ldr", ".n\t$Rt, $addr",
687 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
688 T1Encoding<{0,1,0,0,1,?}> {
693 let Inst{7-0} = addr;
696 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
697 // For disassembly use only.
698 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
699 "ldr", "\t$Rt, $addr",
700 [/* disassembly only */]>,
701 T1Encoding<{0,1,0,0,1,?}> {
706 let Inst{7-0} = addr;
709 // A8.6.194 & A8.6.192
710 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
711 t_addrmode_is4, AddrModeT1_4,
712 IIC_iStore_r, IIC_iStore_i, "str",
713 BinOpFrag<(store node:$LHS, node:$RHS)>>;
715 // A8.6.197 & A8.6.195
716 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
717 t_addrmode_is1, AddrModeT1_1,
718 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
719 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
721 // A8.6.207 & A8.6.205
722 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
723 t_addrmode_is2, AddrModeT1_2,
724 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
725 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
728 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
729 "str", "\t$Rt, $addr",
730 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
735 let Inst{7-0} = addr;
738 //===----------------------------------------------------------------------===//
739 // Load / store multiple Instructions.
742 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
743 InstrItinClass itin_upd, bits<6> T1Enc,
746 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
747 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
752 let Inst{7-0} = regs;
755 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
756 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
761 let Inst{7-0} = regs;
765 // These require base address to be written back or one of the loaded regs.
766 let neverHasSideEffects = 1 in {
768 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
769 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
772 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
773 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
776 } // neverHasSideEffects
778 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
779 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
781 "pop${p}\t$regs", []>,
782 T1Misc<{1,1,0,?,?,?,?}> {
784 let Inst{8} = regs{15};
785 let Inst{7-0} = regs{7-0};
788 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
789 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
791 "push${p}\t$regs", []>,
792 T1Misc<{0,1,0,?,?,?,?}> {
794 let Inst{8} = regs{14};
795 let Inst{7-0} = regs{7-0};
798 //===----------------------------------------------------------------------===//
799 // Arithmetic Instructions.
802 // Helper classes for encoding T1pI patterns:
803 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
804 string opc, string asm, list<dag> pattern>
805 : T1pI<oops, iops, itin, opc, asm, pattern>,
806 T1DataProcessing<opA> {
812 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
813 string opc, string asm, list<dag> pattern>
814 : T1pI<oops, iops, itin, opc, asm, pattern>,
822 // Helper classes for encoding T1sI patterns:
823 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
824 string opc, string asm, list<dag> pattern>
825 : T1sI<oops, iops, itin, opc, asm, pattern>,
826 T1DataProcessing<opA> {
832 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
833 string opc, string asm, list<dag> pattern>
834 : T1sI<oops, iops, itin, opc, asm, pattern>,
843 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
844 string opc, string asm, list<dag> pattern>
845 : T1sI<oops, iops, itin, opc, asm, pattern>,
853 // Helper classes for encoding T1sIt patterns:
854 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
855 string opc, string asm, list<dag> pattern>
856 : T1sIt<oops, iops, itin, opc, asm, pattern>,
857 T1DataProcessing<opA> {
863 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
864 string opc, string asm, list<dag> pattern>
865 : T1sIt<oops, iops, itin, opc, asm, pattern>,
869 let Inst{10-8} = Rdn;
870 let Inst{7-0} = imm8;
873 // Add with carry register
874 let isCommutable = 1, Uses = [CPSR] in
876 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
877 "adc", "\t$Rdn, $Rm",
878 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
881 def tADDi3 : // A8.6.4 T1
882 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
884 "add", "\t$Rd, $Rm, $imm3",
885 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
887 let Inst{8-6} = imm3;
890 def tADDi8 : // A8.6.4 T2
891 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
893 "add", "\t$Rdn, $imm8",
894 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
897 let isCommutable = 1 in
898 def tADDrr : // A8.6.6 T1
899 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
901 "add", "\t$Rd, $Rn, $Rm",
902 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
904 let neverHasSideEffects = 1 in
905 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
906 "add", "\t$Rdn, $Rm", []>,
907 T1Special<{0,0,?,?}> {
911 let Inst{7} = Rdn{3};
913 let Inst{2-0} = Rdn{2-0};
917 let isCommutable = 1 in
918 def tAND : // A8.6.12
919 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
921 "and", "\t$Rdn, $Rm",
922 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
925 def tASRri : // A8.6.14
926 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
928 "asr", "\t$Rd, $Rm, $imm5",
929 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
931 let Inst{10-6} = imm5;
935 def tASRrr : // A8.6.15
936 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
938 "asr", "\t$Rdn, $Rm",
939 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
942 def tBIC : // A8.6.20
943 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
945 "bic", "\t$Rdn, $Rm",
946 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
949 let isCompare = 1, Defs = [CPSR] in {
950 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
951 // Compare-to-zero still works out, just not the relationals
952 //def tCMN : // A8.6.33
953 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
955 // "cmn", "\t$lhs, $rhs",
956 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
958 def tCMNz : // A8.6.33
959 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
962 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
964 } // isCompare = 1, Defs = [CPSR]
967 let isCompare = 1, Defs = [CPSR] in {
968 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
969 "cmp", "\t$Rn, $imm8",
970 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
971 T1General<{1,0,1,?,?}> {
976 let Inst{7-0} = imm8;
980 def tCMPr : // A8.6.36 T1
981 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
984 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
986 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
987 "cmp", "\t$Rn, $Rm", []>,
988 T1Special<{0,1,?,?}> {
994 let Inst{2-0} = Rn{2-0};
996 } // isCompare = 1, Defs = [CPSR]
1000 let isCommutable = 1 in
1001 def tEOR : // A8.6.45
1002 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1004 "eor", "\t$Rdn, $Rm",
1005 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1008 def tLSLri : // A8.6.88
1009 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1011 "lsl", "\t$Rd, $Rm, $imm5",
1012 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1014 let Inst{10-6} = imm5;
1018 def tLSLrr : // A8.6.89
1019 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1021 "lsl", "\t$Rdn, $Rm",
1022 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1025 def tLSRri : // A8.6.90
1026 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1028 "lsr", "\t$Rd, $Rm, $imm5",
1029 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1031 let Inst{10-6} = imm5;
1035 def tLSRrr : // A8.6.91
1036 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1038 "lsr", "\t$Rdn, $Rm",
1039 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1042 let isMoveImm = 1 in
1043 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1044 "mov", "\t$Rd, $imm8",
1045 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1046 T1General<{1,0,0,?,?}> {
1050 let Inst{10-8} = Rd;
1051 let Inst{7-0} = imm8;
1054 // A7-73: MOV(2) - mov setting flag.
1056 let neverHasSideEffects = 1 in {
1057 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1058 Size2Bytes, IIC_iMOVr,
1059 "mov", "\t$Rd, $Rm", "", []>,
1060 T1Special<{1,0,?,?}> {
1064 let Inst{7} = Rd{3};
1066 let Inst{2-0} = Rd{2-0};
1068 let Defs = [CPSR] in
1069 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1070 "movs\t$Rd, $Rm", []>, Encoding16 {
1074 let Inst{15-6} = 0b0000000000;
1078 } // neverHasSideEffects
1080 // Multiply register
1081 let isCommutable = 1 in
1082 def tMUL : // A8.6.105 T1
1083 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1085 "mul", "\t$Rdn, $Rm, $Rdn",
1086 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1088 // Move inverse register
1089 def tMVN : // A8.6.107
1090 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1091 "mvn", "\t$Rd, $Rn",
1092 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1094 // Bitwise or register
1095 let isCommutable = 1 in
1096 def tORR : // A8.6.114
1097 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1099 "orr", "\t$Rdn, $Rm",
1100 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1103 def tREV : // A8.6.134
1104 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1106 "rev", "\t$Rd, $Rm",
1107 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1108 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1110 def tREV16 : // A8.6.135
1111 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1113 "rev16", "\t$Rd, $Rm",
1114 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1115 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1117 def tREVSH : // A8.6.136
1118 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1120 "revsh", "\t$Rd, $Rm",
1121 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1122 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1124 // Rotate right register
1125 def tROR : // A8.6.139
1126 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1128 "ror", "\t$Rdn, $Rm",
1129 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1132 def tRSB : // A8.6.141
1133 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1135 "rsb", "\t$Rd, $Rn, #0",
1136 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1138 // Subtract with carry register
1139 let Uses = [CPSR] in
1140 def tSBC : // A8.6.151
1141 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1143 "sbc", "\t$Rdn, $Rm",
1144 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1146 // Subtract immediate
1147 def tSUBi3 : // A8.6.210 T1
1148 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1150 "sub", "\t$Rd, $Rm, $imm3",
1151 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1153 let Inst{8-6} = imm3;
1156 def tSUBi8 : // A8.6.210 T2
1157 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1159 "sub", "\t$Rdn, $imm8",
1160 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1162 // Subtract register
1163 def tSUBrr : // A8.6.212
1164 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1166 "sub", "\t$Rd, $Rn, $Rm",
1167 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1169 // TODO: A7-96: STMIA - store multiple.
1172 def tSXTB : // A8.6.222
1173 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1175 "sxtb", "\t$Rd, $Rm",
1176 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1177 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1179 // Sign-extend short
1180 def tSXTH : // A8.6.224
1181 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1183 "sxth", "\t$Rd, $Rm",
1184 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1185 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1188 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1189 def tTST : // A8.6.230
1190 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1191 "tst", "\t$Rn, $Rm",
1192 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1195 def tUXTB : // A8.6.262
1196 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1198 "uxtb", "\t$Rd, $Rm",
1199 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1200 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1202 // Zero-extend short
1203 def tUXTH : // A8.6.264
1204 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1206 "uxth", "\t$Rd, $Rm",
1207 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1208 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1210 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1211 // Expanded after instruction selection into a branch sequence.
1212 let usesCustomInserter = 1 in // Expanded after instruction selection.
1213 def tMOVCCr_pseudo :
1214 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1216 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1218 // tLEApcrel - Load a pc-relative address into a register without offending the
1221 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1222 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1223 T1Encoding<{1,0,1,0,0,?}> {
1226 let Inst{10-8} = Rd;
1227 let Inst{7-0} = addr;
1230 let neverHasSideEffects = 1, isReMaterializable = 1 in
1231 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1232 Size2Bytes, IIC_iALUi, []>;
1234 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1235 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1236 Size2Bytes, IIC_iALUi, []>;
1238 //===----------------------------------------------------------------------===//
1239 // Move between coprocessor and ARM core register -- for disassembly only
1242 class tMovRCopro<string opc, bit direction, dag oops, dag iops,
1244 : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1246 let Inst{27-24} = 0b1110;
1247 let Inst{20} = direction;
1257 let Inst{15-12} = Rt;
1258 let Inst{11-8} = cop;
1259 let Inst{23-21} = opc1;
1260 let Inst{7-5} = opc2;
1261 let Inst{3-0} = CRm;
1262 let Inst{19-16} = CRn;
1265 def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
1267 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
1268 c_imm:$CRm, i32imm:$opc2),
1269 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
1270 imm:$CRm, imm:$opc2)]>;
1271 def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
1273 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1276 def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
1277 (tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>,
1278 Requires<[IsThumb, HasV6T2]>;
1280 class tMovRRCopro<string opc, bit direction,
1281 list<dag> pattern = [/* For disassembly only */]>
1282 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1283 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
1284 let Inst{27-24} = 0b1100;
1285 let Inst{23-21} = 0b010;
1286 let Inst{20} = direction;
1294 let Inst{15-12} = Rt;
1295 let Inst{19-16} = Rt2;
1296 let Inst{11-8} = cop;
1297 let Inst{7-4} = opc1;
1298 let Inst{3-0} = CRm;
1301 def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
1302 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
1304 def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1306 //===----------------------------------------------------------------------===//
1307 // Other Coprocessor Instructions. For disassembly only.
1309 def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1310 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1311 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1312 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
1313 imm:$CRm, imm:$opc2)]> {
1314 let Inst{27-24} = 0b1110;
1323 let Inst{3-0} = CRm;
1325 let Inst{7-5} = opc2;
1326 let Inst{11-8} = cop;
1327 let Inst{15-12} = CRd;
1328 let Inst{19-16} = CRn;
1329 let Inst{23-20} = opc1;
1332 //===----------------------------------------------------------------------===//
1336 // __aeabi_read_tp preserves the registers r1-r3.
1337 // This is a pseudo inst so that we can get the encoding right,
1338 // complete with fixup for the aeabi_read_tp function.
1339 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1340 def tTPsoft : tPseudoInst<(outs), (ins), Size4Bytes, IIC_Br,
1341 [(set R0, ARMthread_pointer)]>;
1343 //===----------------------------------------------------------------------===//
1344 // SJLJ Exception handling intrinsics
1347 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1348 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1349 // from some other function to get here, and we're using the stack frame for the
1350 // containing function to save/restore registers, we can't keep anything live in
1351 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1352 // tromped upon when we get here from a longjmp(). We force everything out of
1353 // registers except for our own input by listing the relevant registers in
1354 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1355 // preserve all of the callee-saved resgisters, which is exactly what we want.
1356 // $val is a scratch register for our use.
1357 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1358 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1359 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1360 AddrModeNone, SizeSpecial, NoItinerary, "","",
1361 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1363 // FIXME: Non-Darwin version(s)
1364 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1365 Defs = [ R7, LR, SP ] in
1366 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1367 AddrModeNone, SizeSpecial, IndexModeNone,
1368 Pseudo, NoItinerary, "", "",
1369 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1370 Requires<[IsThumb, IsDarwin]>;
1372 //===----------------------------------------------------------------------===//
1373 // Non-Instruction Patterns
1377 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1378 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1379 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1380 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1383 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1384 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1385 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1386 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1387 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1388 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1390 // Subtract with carry
1391 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1392 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1393 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1394 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1395 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1396 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1398 // ConstantPool, GlobalAddress
1399 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1400 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1403 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1404 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1407 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1408 Requires<[IsThumb, IsNotDarwin]>;
1409 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1410 Requires<[IsThumb, IsDarwin]>;
1412 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1413 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1414 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1415 Requires<[IsThumb, HasV5T, IsDarwin]>;
1417 // Indirect calls to ARM routines
1418 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1419 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1420 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1421 Requires<[IsThumb, HasV5T, IsDarwin]>;
1423 // zextload i1 -> zextload i8
1424 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1425 (tLDRBr t_addrmode_rrs1:$addr)>;
1426 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1427 (tLDRBi t_addrmode_is1:$addr)>;
1429 // extload -> zextload
1430 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1431 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1432 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1433 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1434 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1435 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1437 // If it's impossible to use [r,r] address mode for sextload, select to
1438 // ldr{b|h} + sxt{b|h} instead.
1439 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1440 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1441 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1442 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1443 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1444 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1445 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1446 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1447 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1448 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1449 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1450 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1452 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1453 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1454 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1455 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1456 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1457 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1458 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1459 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1461 // Large immediate handling.
1464 def : T1Pat<(i32 thumb_immshifted:$src),
1465 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1466 (thumb_immshifted_shamt imm:$src))>;
1468 def : T1Pat<(i32 imm0_255_comp:$src),
1469 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1471 // Pseudo instruction that combines ldr from constpool and add pc. This should
1472 // be expanded into two instructions late to allow if-conversion and
1474 let isReMaterializable = 1 in
1475 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1477 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1479 Requires<[IsThumb, IsThumb1Only]>;