1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
131 Requires<[IsThumb, IsThumb1Only]>;
133 def tADJCALLSTACKDOWN :
134 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
135 [(ARMcallseq_start imm:$amt)]>,
136 Requires<[IsThumb, IsThumb1Only]>;
139 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
140 [/* For disassembly only; pattern left blank */]>,
141 T1Encoding<0b101111> {
143 let Inst{9-8} = 0b11;
144 let Inst{7-0} = 0x00;
147 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
148 [/* For disassembly only; pattern left blank */]>,
149 T1Encoding<0b101111> {
151 let Inst{9-8} = 0b11;
152 let Inst{7-0} = 0x10;
155 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
156 [/* For disassembly only; pattern left blank */]>,
157 T1Encoding<0b101111> {
159 let Inst{9-8} = 0b11;
160 let Inst{7-0} = 0x20;
163 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
164 [/* For disassembly only; pattern left blank */]>,
165 T1Encoding<0b101111> {
167 let Inst{9-8} = 0b11;
168 let Inst{7-0} = 0x30;
171 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
172 [/* For disassembly only; pattern left blank */]>,
173 T1Encoding<0b101111> {
175 let Inst{9-8} = 0b11;
176 let Inst{7-0} = 0x40;
179 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
180 [/* For disassembly only; pattern left blank */]>,
181 T1Encoding<0b101101> {
183 let Inst{9-5} = 0b10010;
185 let Inst{3} = 1; // Big-Endian
186 let Inst{2-0} = 0b000;
189 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
190 [/* For disassembly only; pattern left blank */]>,
191 T1Encoding<0b101101> {
193 let Inst{9-5} = 0b10010;
195 let Inst{3} = 0; // Little-Endian
196 let Inst{2-0} = 0b000;
199 // The i32imm operand $val can be used by a debugger to store more information
200 // about the breakpoint.
201 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
202 [/* For disassembly only; pattern left blank */]>,
203 T1Encoding<0b101111> {
206 let Inst{9-8} = 0b10;
210 // Change Processor State is a system instruction -- for disassembly only.
211 // The singleton $opt operand contains the following information:
212 // opt{4-0} = mode ==> don't care
213 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
214 // opt{8-6} = AIF from Inst{2-0}
215 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
217 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
218 // CPS which has more options.
219 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
220 [/* For disassembly only; pattern left blank */]>,
223 let Inst{3} = 0; // FIXME: Finish encoding.
226 // For both thumb1 and thumb2.
227 let isNotDuplicable = 1, isCodeGenOnly = 1 in
228 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
229 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
230 T1Special<{0,0,?,?}> {
233 let Inst{6-3} = 0b1111;
238 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
239 "add\t$dst, pc, $rhs", []>,
240 T1Encoding<{1,0,1,0,0,?}> {
244 let Inst{10-8} = dst;
248 // ADD <Rd>, sp, #<imm8>
249 // This is rematerializable, which is particularly useful for taking the
250 // address of locals.
251 let isReMaterializable = 1 in
252 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
253 "add\t$dst, $sp, $rhs", []>,
254 T1Encoding<{1,0,1,0,1,?}> {
258 let Inst{10-8} = dst;
262 // ADD sp, sp, #<imm7>
263 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
264 "add\t$dst, $rhs", []>,
265 T1Misc<{0,0,0,0,0,?,?}> {
271 // SUB sp, sp, #<imm7>
272 // FIXME: The encoding and the ASM string don't match up.
273 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
274 "sub\t$dst, $rhs", []>,
275 T1Misc<{0,0,0,0,1,?,?}> {
282 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
283 "add\t$dst, $rhs", []>,
284 T1Special<{0,0,?,?}> {
285 // A8.6.9 Encoding T1
287 let Inst{7} = dst{3};
288 let Inst{6-3} = 0b1101;
289 let Inst{2-0} = dst{2-0};
293 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
294 "add\t$dst, $rhs", []>,
295 T1Special<{0,0,?,?}> {
296 // A8.6.9 Encoding T2
300 let Inst{2-0} = 0b101;
303 //===----------------------------------------------------------------------===//
304 // Control Flow Instructions.
307 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
308 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
310 T1Special<{1,1,0,?}> {
312 let Inst{6-3} = 0b1110; // Rm = lr
313 let Inst{2-0} = 0b000;
316 // Alternative return instruction used by vararg functions.
317 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
320 T1Special<{1,1,0,?}> {
324 let Inst{2-0} = 0b000;
329 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
330 def tBRIND : TI<(outs), (ins GPR:$Rm), IIC_Br, "mov\tpc, $Rm",
332 T1Special<{1,0,?,?}> {
335 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
337 let Inst{2-0} = 0b111;
341 // FIXME: remove when we have a way to marking a MI with these properties.
342 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
343 hasExtraDefRegAllocReq = 1 in
344 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
346 "pop${p}\t$regs", []>,
347 T1Misc<{1,1,0,?,?,?,?}> {
350 let Inst{8} = regs{15}; // registers = P:'0000000':register_list
351 let Inst{7-0} = regs{7-0};
355 Defs = [R0, R1, R2, R3, R12, LR,
356 D0, D1, D2, D3, D4, D5, D6, D7,
357 D16, D17, D18, D19, D20, D21, D22, D23,
358 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
359 // Also used for Thumb2
360 def tBL : TIx2<0b11110, 0b11, 1,
361 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
363 [(ARMtcall tglobaladdr:$func)]>,
364 Requires<[IsThumb, IsNotDarwin]>;
366 // ARMv5T and above, also used for Thumb2
367 def tBLXi : TIx2<0b11110, 0b11, 0,
368 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
370 [(ARMcall tglobaladdr:$func)]>,
371 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
373 // Also used for Thumb2
374 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
376 [(ARMtcall GPR:$func)]>,
377 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
378 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
381 let isCodeGenOnly = 1 in
382 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
383 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
384 "mov\tlr, pc\n\tbx\t$func",
385 [(ARMcall_nolink tGPR:$func)]>,
386 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
389 // On Darwin R9 is call-clobbered.
391 Defs = [R0, R1, R2, R3, R9, R12, LR,
392 D0, D1, D2, D3, D4, D5, D6, D7,
393 D16, D17, D18, D19, D20, D21, D22, D23,
394 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
395 // Also used for Thumb2
396 def tBLr9 : TIx2<0b11110, 0b11, 1,
397 (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br,
399 [(ARMtcall tglobaladdr:$func)]>,
400 Requires<[IsThumb, IsDarwin]>;
402 // ARMv5T and above, also used for Thumb2
403 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
404 (outs), (ins pred:$p, i32imm:$func, variable_ops), IIC_Br,
406 [(ARMcall tglobaladdr:$func)]>,
407 Requires<[IsThumb, HasV5T, IsDarwin]>;
409 // Also used for Thumb2
410 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
412 [(ARMtcall GPR:$func)]>,
413 Requires<[IsThumb, HasV5T, IsDarwin]>,
414 T1Special<{1,1,1,?}> {
417 let Inst{6-3} = func;
418 let Inst{2-0} = 0b000;
422 let isCodeGenOnly = 1 in
423 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
424 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
425 "mov\tlr, pc\n\tbx\t$func",
426 [(ARMcall_nolink tGPR:$func)]>,
427 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
430 let isBranch = 1, isTerminator = 1 in {
431 let isBarrier = 1 in {
432 let isPredicable = 1 in
433 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
434 "b\t$target", [(br bb:$target)]>,
435 T1Encoding<{1,1,1,0,0,?}>;
439 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
442 def tBR_JTr : tPseudoInst<(outs),
443 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
445 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
446 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
451 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
452 // a two-value operand where a dag node expects two operands. :(
453 let isBranch = 1, isTerminator = 1 in
454 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
456 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
457 T1Encoding<{1,1,0,1,?,?}>;
459 // Compare and branch on zero / non-zero
460 let isBranch = 1, isTerminator = 1 in {
461 def tCBZ : T1I<(outs), (ins tGPR:$Rn, brtarget:$target), IIC_Br,
462 "cbz\t$Rn, $target", []>,
463 T1Misc<{0,0,?,1,?,?,?}> {
467 let Inst{9} = target{5};
468 let Inst{7-3} = target{4-0};
472 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
473 "cbnz\t$cmp, $target", []>,
474 T1Misc<{1,0,?,1,?,?,?}> {
478 let Inst{9} = target{5};
479 let Inst{7-3} = target{4-0};
484 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
485 // A8.6.16 B: Encoding T1
486 // If Inst{11-8} == 0b1111 then SEE SVC
488 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
489 "svc", "\t$imm", []>, Encoding16 {
491 let Inst{15-12} = 0b1101;
492 let Inst{11-8} = 0b1111;
496 // A8.6.16 B: Encoding T1
497 // If Inst{11-8} == 0b1110 then UNDEFINED
498 let isBarrier = 1, isTerminator = 1 in
499 def tTRAP : TI<(outs), (ins), IIC_Br,
500 "trap", [(trap)]>, Encoding16 {
504 //===----------------------------------------------------------------------===//
505 // Load Store Instructions.
508 let canFoldAsLoad = 1, isReMaterializable = 1 in
509 def tLDR : T1pI4<(outs tGPR:$Rt), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
510 "ldr", "\t$Rt, $addr",
511 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>,
514 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
515 "ldr", "\t$dst, $addr",
519 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
520 "ldrb", "\t$dst, $addr",
521 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
523 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
524 "ldrb", "\t$dst, $addr",
528 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
529 "ldrh", "\t$dst, $addr",
530 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
532 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
533 "ldrh", "\t$dst, $addr",
537 let AddedComplexity = 10 in
538 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
539 "ldrsb", "\t$dst, $addr",
540 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
543 let AddedComplexity = 10 in
544 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
545 "ldrsh", "\t$dst, $addr",
546 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
549 let canFoldAsLoad = 1 in
550 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
551 "ldr", "\t$dst, $addr",
552 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
555 // Special instruction for restore. It cannot clobber condition register
556 // when it's expanded by eliminateCallFramePseudoInstr().
557 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
558 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
559 "ldr", "\t$dst, $addr", []>,
563 // FIXME: Use ldr.n to work around a Darwin assembler bug.
564 let canFoldAsLoad = 1, isReMaterializable = 1 in
565 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
566 "ldr", ".n\t$dst, $addr",
567 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
568 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
570 // Special LDR for loads from non-pc-relative constpools.
571 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
572 isReMaterializable = 1 in
573 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
574 "ldr", "\t$dst, $addr", []>,
577 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
578 "str", "\t$src, $addr",
579 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
581 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
582 "str", "\t$src, $addr",
586 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
587 "strb", "\t$src, $addr",
588 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
590 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
591 "strb", "\t$src, $addr",
595 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
596 "strh", "\t$src, $addr",
597 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
599 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
600 "strh", "\t$src, $addr",
604 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
605 "str", "\t$src, $addr",
606 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
609 let mayStore = 1, neverHasSideEffects = 1 in {
610 // Special instruction for spill. It cannot clobber condition register
611 // when it's expanded by eliminateCallFramePseudoInstr().
612 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
613 "str", "\t$src, $addr", []>,
617 //===----------------------------------------------------------------------===//
618 // Load / store multiple Instructions.
621 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
622 InstrItinClass itin_upd, bits<6> T1Enc,
625 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
626 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
631 let Inst{7-0} = regs;
634 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
635 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
640 let Inst{7-0} = regs;
644 // These require base address to be written back or one of the loaded regs.
645 let neverHasSideEffects = 1 in {
647 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
648 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
651 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
652 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
655 } // neverHasSideEffects
657 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
658 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
660 "pop${p}\t$regs", []>,
661 T1Misc<{1,1,0,?,?,?,?}> {
663 let Inst{8} = regs{15};
664 let Inst{7-0} = regs{7-0};
667 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
668 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
670 "push${p}\t$regs", []>,
671 T1Misc<{0,1,0,?,?,?,?}> {
673 let Inst{8} = regs{14};
674 let Inst{7-0} = regs{7-0};
677 //===----------------------------------------------------------------------===//
678 // Arithmetic Instructions.
681 // Add with carry register
682 let isCommutable = 1, Uses = [CPSR] in
683 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
684 "adc", "\t$dst, $rhs",
685 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
686 T1DataProcessing<0b0101> {
695 def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
696 "add", "\t$Rd, $Rn, $imm3",
697 [(set tGPR:$Rd, (add tGPR:$Rn, imm0_7:$imm3))]>,
703 let Inst{8-6} = imm3;
708 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
709 "add", "\t$dst, $rhs",
710 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
711 T1General<{1,1,0,?,?}> {
715 let Inst{10-8} = lhs;
720 let isCommutable = 1 in
721 def tADDrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
722 "add", "\t$Rd, $Rn, $Rm",
723 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>,
734 let neverHasSideEffects = 1 in
735 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
736 "add", "\t$dst, $rhs", []>,
737 T1Special<{0,0,?,?}> {
742 let Inst{7} = dst{3};
743 let Inst{2-0} = dst{2-0};
747 let isCommutable = 1 in
748 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
749 "and", "\t$dst, $rhs",
750 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
751 T1DataProcessing<0b0000> {
760 def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
761 "asr", "\t$Rd, $Rm, $imm5",
762 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]>,
763 T1General<{0,1,0,?,?}> {
768 let Inst{10-6} = imm5;
774 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
775 "asr", "\t$dst, $rhs",
776 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
777 T1DataProcessing<0b0100> {
786 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
787 "bic", "\t$dst, $rhs",
788 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
789 T1DataProcessing<0b1110> {
798 let isCompare = 1, Defs = [CPSR] in {
799 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
800 // Compare-to-zero still works out, just not the relationals
801 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
802 // "cmn", "\t$lhs, $rhs",
803 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
804 // T1DataProcessing<0b1011>;
805 def tCMNz : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
807 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>,
808 T1DataProcessing<0b1011> {
818 let isCompare = 1, Defs = [CPSR] in {
819 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
820 "cmp", "\t$Rn, $imm8",
821 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
822 T1General<{1,0,1,?,?}> {
827 let Inst{7-0} = imm8;
830 def tCMPzi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
831 "cmp", "\t$Rn, $imm8",
832 [(ARMcmpZ tGPR:$Rn, imm0_255:$imm8)]>,
833 T1General<{1,0,1,?,?}> {
837 let Inst{7-0} = 0x00;
841 def tCMPr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
843 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>,
844 T1DataProcessing<0b1010> {
851 def tCMPzr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
853 [(ARMcmpZ tGPR:$Rn, tGPR:$Rm)]>,
854 T1DataProcessing<0b1010> {
862 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
863 "cmp", "\t$Rn, $Rm", []>,
864 T1Special<{0,1,?,?}> {
870 let Inst{2-0} = Rn{2-0};
872 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
873 "cmp", "\t$lhs, $rhs", []>,
874 T1Special<{0,1,?,?}> {
880 let Inst{2-0} = Rn{2-0};
883 } // isCompare = 1, Defs = [CPSR]
887 let isCommutable = 1 in
888 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
889 "eor", "\t$dst, $rhs",
890 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
891 T1DataProcessing<0b0001> {
900 def tLSLri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
901 "lsl", "\t$Rd, $Rm, $imm5",
902 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
903 T1General<{0,0,0,?,?}> {
908 let Inst{10-6} = imm5;
914 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
915 "lsl", "\t$dst, $rhs",
916 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
917 T1DataProcessing<0b0010> {
926 def tLSRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
927 "lsr", "\t$Rd, $Rm, $imm5",
928 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]>,
929 T1General<{0,0,1,?,?}> {
934 let Inst{10-6} = imm5;
940 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
941 "lsr", "\t$dst, $rhs",
942 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
943 T1DataProcessing<0b0011> {
953 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
954 "mov", "\t$Rd, $imm8",
955 [(set tGPR:$Rd, imm0_255:$imm8)]>,
956 T1General<{1,0,0,?,?}> {
961 let Inst{7-0} = imm8;
964 // TODO: A7-73: MOV(2) - mov setting flag.
966 let neverHasSideEffects = 1 in {
967 // FIXME: Make this predicable.
968 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
969 "mov\t$dst, $src", []>,
972 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
973 "movs\t$dst, $src", []>, Encoding16 {
974 let Inst{15-6} = 0b0000000000;
977 // FIXME: Make these predicable.
978 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
979 "mov\t$dst, $src", []>,
980 T1Special<{1,0,0,?}>;
981 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
982 "mov\t$dst, $src", []>,
983 T1Special<{1,0,?,0}>;
984 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
985 "mov\t$dst, $src", []>,
986 T1Special<{1,0,?,?}>;
987 } // neverHasSideEffects
990 let isCommutable = 1 in
991 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
992 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
993 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
994 T1DataProcessing<0b1101> {
1002 // move inverse register
1003 def tMVN : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMVNr,
1004 "mvn", "\t$Rd, $Rm",
1005 [(set tGPR:$Rd, (not tGPR:$Rm))]>,
1006 T1DataProcessing<0b1111> {
1014 // Bitwise or register
1015 let isCommutable = 1 in
1016 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
1017 "orr", "\t$dst, $rhs",
1018 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
1019 T1DataProcessing<0b1100> {
1023 let Inst{5-3} = rhs;
1024 let Inst{2-0} = dst;
1028 def tREV : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1029 "rev", "\t$Rd, $Rm",
1030 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1031 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1032 T1Misc<{1,0,1,0,0,0,?}> {
1040 def tREV16 : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1041 "rev16", "\t$Rd, $Rm",
1043 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1044 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1045 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1046 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1047 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1048 T1Misc<{1,0,1,0,0,1,?}> {
1056 def tREVSH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1057 "revsh", "\t$Rd, $Rm",
1060 (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1061 (shl tGPR:$Rm, (i32 8))), i16))]>,
1062 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1063 T1Misc<{1,0,1,0,1,1,?}> {
1071 // rotate right register
1072 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
1073 "ror", "\t$dst, $rhs",
1074 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
1075 T1DataProcessing<0b0111> {
1079 let Inst{5-3} = rhs;
1080 let Inst{2-0} = dst;
1084 def tRSB : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iALUi,
1085 "rsb", "\t$Rd, $Rn, #0",
1086 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>,
1087 T1DataProcessing<0b1001> {
1095 // Subtract with carry register
1096 let Uses = [CPSR] in
1097 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
1098 "sbc", "\t$dst, $rhs",
1099 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
1100 T1DataProcessing<0b0110> {
1104 let Inst{5-3} = rhs;
1105 let Inst{2-0} = dst;
1108 // Subtract immediate
1109 def tSUBi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
1110 "sub", "\t$Rd, $Rn, $imm3",
1111 [(set tGPR:$Rd, (add tGPR:$Rn, imm0_7_neg:$imm3))]>,
1112 T1General<0b01111> {
1117 let Inst{8-6} = imm3;
1122 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
1123 "sub", "\t$dst, $rhs",
1124 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
1125 T1General<{1,1,1,?,?}> {
1129 let Inst{10-8} = dst;
1130 let Inst{7-0} = rhs;
1133 // subtract register
1134 def tSUBrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
1135 "sub", "\t$Rd, $Rn, $Rm",
1136 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1137 T1General<0b01101> {
1147 // TODO: A7-96: STMIA - store multiple.
1150 def tSXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1151 "sxtb", "\t$Rd, $Rm",
1152 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1153 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1154 T1Misc<{0,0,1,0,0,1,?}> {
1162 // sign-extend short
1163 def tSXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1164 "sxth", "\t$Rd, $Rm",
1165 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1166 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1167 T1Misc<{0,0,1,0,0,0,?}> {
1176 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1177 def tTST : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1178 "tst", "\t$Rn, $Rm",
1179 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1180 T1DataProcessing<0b1000> {
1189 def tUXTB : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1190 "uxtb", "\t$Rd, $Rm",
1191 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1192 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1193 T1Misc<{0,0,1,0,1,1,?}> {
1201 // zero-extend short
1202 def tUXTH : T1pI<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iUNAr,
1203 "uxth", "\t$Rd, $Rm",
1204 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1205 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1206 T1Misc<{0,0,1,0,1,0,?}> {
1215 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1216 // Expanded after instruction selection into a branch sequence.
1217 let usesCustomInserter = 1 in // Expanded after instruction selection.
1218 def tMOVCCr_pseudo :
1219 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1221 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1224 // 16-bit movcc in IT blocks for Thumb2.
1225 let neverHasSideEffects = 1 in {
1226 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
1227 "mov", "\t$dst, $rhs", []>,
1228 T1Special<{1,0,?,?}>;
1230 let isMoveImm = 1 in
1231 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
1232 "mov", "\t$dst, $rhs", []>,
1233 T1General<{1,0,0,?,?}>;
1234 } // neverHasSideEffects
1236 // tLEApcrel - Load a pc-relative address into a register without offending the
1238 let neverHasSideEffects = 1 in {
1239 let isReMaterializable = 1 in
1240 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
1241 "adr$p\t$dst, #$label", []>,
1242 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
1244 } // neverHasSideEffects
1245 def tLEApcrelJT : T1I<(outs tGPR:$dst),
1246 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1247 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
1248 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
1250 //===----------------------------------------------------------------------===//
1254 // __aeabi_read_tp preserves the registers r1-r3.
1256 Defs = [R0, LR] in {
1257 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1258 "bl\t__aeabi_read_tp",
1259 [(set R0, ARMthread_pointer)]>;
1262 // SJLJ Exception handling intrinsics
1263 // eh_sjlj_setjmp() is an instruction sequence to store the return
1264 // address and save #0 in R0 for the non-longjmp case.
1265 // Since by its nature we may be coming from some other function to get
1266 // here, and we're using the stack frame for the containing function to
1267 // save/restore registers, we can't keep anything live in regs across
1268 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1269 // when we get here from a longjmp(). We force everthing out of registers
1270 // except for our own input by listing the relevant registers in Defs. By
1271 // doing so, we also cause the prologue/epilogue code to actively preserve
1272 // all of the callee-saved resgisters, which is exactly what we want.
1273 // $val is a scratch register for our use.
1275 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
1276 isBarrier = 1, isCodeGenOnly = 1 in {
1277 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1278 AddrModeNone, SizeSpecial, NoItinerary, "", "",
1279 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1282 // FIXME: Non-Darwin version(s)
1283 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1284 Defs = [ R7, LR, SP ] in {
1285 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1286 AddrModeNone, SizeSpecial, IndexModeNone,
1287 Pseudo, NoItinerary, "", "",
1288 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1289 Requires<[IsThumb, IsDarwin]>;
1292 //===----------------------------------------------------------------------===//
1293 // Non-Instruction Patterns
1297 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1298 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1299 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1300 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1301 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1302 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1304 // Subtract with carry
1305 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1306 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1307 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1308 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1309 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1310 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1312 // ConstantPool, GlobalAddress
1313 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1314 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1317 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1318 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1321 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1322 Requires<[IsThumb, IsNotDarwin]>;
1323 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1324 Requires<[IsThumb, IsDarwin]>;
1326 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1327 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1328 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1329 Requires<[IsThumb, HasV5T, IsDarwin]>;
1331 // Indirect calls to ARM routines
1332 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1333 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1334 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1335 Requires<[IsThumb, HasV5T, IsDarwin]>;
1337 // zextload i1 -> zextload i8
1338 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
1339 (tLDRB t_addrmode_s1:$addr)>;
1341 // extload -> zextload
1342 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1343 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1344 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
1346 // If it's impossible to use [r,r] address mode for sextload, select to
1347 // ldr{b|h} + sxt{b|h} instead.
1348 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1349 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1350 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1351 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1352 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1353 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1355 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1356 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1357 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1358 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1360 // Large immediate handling.
1363 def : T1Pat<(i32 thumb_immshifted:$src),
1364 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1365 (thumb_immshifted_shamt imm:$src))>;
1367 def : T1Pat<(i32 imm0_255_comp:$src),
1368 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1370 // Pseudo instruction that combines ldr from constpool and add pc. This should
1371 // be expanded into two instructions late to allow if-conversion and
1373 let isReMaterializable = 1 in
1374 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1376 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1378 Requires<[IsThumb, IsThumb1Only]>;