1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 // For both thumb1 and thumb2.
131 let isNotDuplicable = 1 in
132 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALU,
133 "$cp:\n\tadd $dst, pc",
134 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
137 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALU,
138 "add $dst, pc, $rhs * 4", []>;
141 // FIXME: hard code sp?
142 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALU,
143 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
146 // FIXME: hard code sp?
147 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
148 "add $dst, $rhs * 4", []>;
150 // FIXME: Make use of the following?
154 //===----------------------------------------------------------------------===//
155 // Control Flow Instructions.
158 let isReturn = 1, isTerminator = 1 in {
159 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx lr", [(ARMretflag)]>;
160 // Alternative return instruction used by vararg functions.
161 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx $target", []>;
164 // FIXME: remove when we have a way to marking a MI with these properties.
165 let isReturn = 1, isTerminator = 1 in
166 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
170 Defs = [R0, R1, R2, R3, R12, LR,
171 D0, D1, D2, D3, D4, D5, D6, D7,
172 D16, D17, D18, D19, D20, D21, D22, D23,
173 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
174 // Also used for Thumb2
175 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
177 [(ARMtcall tglobaladdr:$func)]>,
178 Requires<[IsThumb, IsNotDarwin]>;
180 // ARMv5T and above, also used for Thumb2
181 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
183 [(ARMcall tglobaladdr:$func)]>,
184 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
186 // Also used for Thumb2
187 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
189 [(ARMtcall GPR:$func)]>,
190 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
193 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
194 "mov lr, pc\n\tbx $func",
195 [(ARMcall_nolink tGPR:$func)]>,
196 Requires<[IsThumb1Only, IsNotDarwin]>;
199 // On Darwin R9 is call-clobbered.
201 Defs = [R0, R1, R2, R3, R9, R12, LR,
202 D0, D1, D2, D3, D4, D5, D6, D7,
203 D16, D17, D18, D19, D20, D21, D22, D23,
204 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
205 // Also used for Thumb2
206 def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
208 [(ARMtcall tglobaladdr:$func)]>,
209 Requires<[IsThumb, IsDarwin]>;
211 // ARMv5T and above, also used for Thumb2
212 def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
214 [(ARMcall tglobaladdr:$func)]>,
215 Requires<[IsThumb, HasV5T, IsDarwin]>;
217 // Also used for Thumb2
218 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
220 [(ARMtcall GPR:$func)]>,
221 Requires<[IsThumb, HasV5T, IsDarwin]>;
224 def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
225 "mov lr, pc\n\tbx $func",
226 [(ARMcall_nolink tGPR:$func)]>,
227 Requires<[IsThumb1Only, IsDarwin]>;
230 let isBranch = 1, isTerminator = 1 in {
231 let isBarrier = 1 in {
232 let isPredicable = 1 in
233 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
234 "b $target", [(br bb:$target)]>;
237 def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br,
238 "bl $target\t@ far jump",[]>;
240 def tBR_JTr : T1JTI<(outs),
241 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
242 IIC_Br, "mov pc, $target\n\t.align\t2\n$jt",
243 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
247 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
248 // a two-value operand where a dag node expects two operands. :(
249 let isBranch = 1, isTerminator = 1 in
250 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
252 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
254 //===----------------------------------------------------------------------===//
255 // Load Store Instructions.
258 let canFoldAsLoad = 1 in
259 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad,
260 "ldr", " $dst, $addr",
261 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
263 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad,
264 "ldrb", " $dst, $addr",
265 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
267 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad,
268 "ldrh", " $dst, $addr",
269 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
271 let AddedComplexity = 10 in
272 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad,
273 "ldrsb", " $dst, $addr",
274 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
276 let AddedComplexity = 10 in
277 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad,
278 "ldrsh", " $dst, $addr",
279 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
281 let canFoldAsLoad = 1 in
282 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad,
283 "ldr", " $dst, $addr",
284 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
286 // Special instruction for restore. It cannot clobber condition register
287 // when it's expanded by eliminateCallFramePseudoInstr().
288 let canFoldAsLoad = 1, mayLoad = 1 in
289 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad,
290 "ldr", " $dst, $addr", []>;
293 let canFoldAsLoad = 1 in
294 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad,
295 "ldr", " $dst, $addr",
296 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
298 // Special LDR for loads from non-pc-relative constpools.
299 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
300 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad,
301 "ldr", " $dst, $addr", []>;
303 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore,
304 "str", " $src, $addr",
305 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
307 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore,
308 "strb", " $src, $addr",
309 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
311 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore,
312 "strh", " $src, $addr",
313 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
315 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
316 "str", " $src, $addr",
317 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
319 let mayStore = 1 in {
320 // Special instruction for spill. It cannot clobber condition register
321 // when it's expanded by eliminateCallFramePseudoInstr().
322 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore,
323 "str", " $src, $addr", []>;
326 //===----------------------------------------------------------------------===//
327 // Load / store multiple Instructions.
330 // TODO: A7-44: LDMIA - load multiple
331 // TODO: Allow these to be predicated
334 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins), IIC_Br,
338 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops), IIC_Br,
341 //===----------------------------------------------------------------------===//
342 // Arithmetic Instructions.
345 // Add with carry register
346 let isCommutable = 1, Uses = [CPSR] in
347 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
348 "adc", " $dst, $rhs",
349 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
352 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
353 "add", " $dst, $lhs, $rhs",
354 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
356 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
357 "add", " $dst, $rhs",
358 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
361 let isCommutable = 1 in
362 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
363 "add", " $dst, $lhs, $rhs",
364 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
366 let neverHasSideEffects = 1 in
367 def tADDhirr : T1pIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
368 "add", " $dst, $rhs @ addhirr", []>;
371 let isCommutable = 1 in
372 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
373 "and", " $dst, $rhs",
374 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
377 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
378 "asr", " $dst, $lhs, $rhs",
379 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
382 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
383 "asr", " $dst, $rhs",
384 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
387 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
388 "bic", " $dst, $rhs",
389 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
392 let Defs = [CPSR] in {
393 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
394 "cmn", " $lhs, $rhs",
395 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
396 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
397 "cmn", " $lhs, $rhs",
398 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
402 let Defs = [CPSR] in {
403 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
404 "cmp", " $lhs, $rhs",
405 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
406 def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
407 "cmp", " $lhs, $rhs",
408 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
413 let Defs = [CPSR] in {
414 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
415 "cmp", " $lhs, $rhs",
416 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
417 def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
418 "cmp", " $lhs, $rhs",
419 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
421 // TODO: Make use of the followings cmp hi regs
422 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
423 "cmp", " $lhs, $rhs", []>;
424 def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iALU,
425 "cmp", " $lhs, $rhs", []>;
430 let isCommutable = 1 in
431 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
432 "eor", " $dst, $rhs",
433 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
436 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
437 "lsl", " $dst, $lhs, $rhs",
438 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
441 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
442 "lsl", " $dst, $rhs",
443 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
446 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
447 "lsr", " $dst, $lhs, $rhs",
448 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
451 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
452 "lsr", " $dst, $rhs",
453 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
456 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iALU,
457 "mov", " $dst, $src",
458 [(set tGPR:$dst, imm0_255:$src)]>;
460 // TODO: A7-73: MOV(2) - mov setting flag.
463 let neverHasSideEffects = 1 in {
464 // FIXME: Make this predicable.
465 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
466 "mov $dst, $src", []>;
468 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
469 "movs $dst, $src", []>;
471 // FIXME: Make these predicable.
472 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iALU,
473 "mov $dst, $src\t@ hir2lor", []>;
474 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iALU,
475 "mov $dst, $src\t@ lor2hir", []>;
476 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iALU,
477 "mov $dst, $src\t@ hir2hir", []>;
478 } // neverHasSideEffects
481 let isCommutable = 1 in
482 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
483 "mul", " $dst, $rhs",
484 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
486 // move inverse register
487 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
488 "mvn", " $dst, $src",
489 [(set tGPR:$dst, (not tGPR:$src))]>;
491 // bitwise or register
492 let isCommutable = 1 in
493 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
494 "orr", " $dst, $rhs",
495 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
498 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
499 "rev", " $dst, $src",
500 [(set tGPR:$dst, (bswap tGPR:$src))]>,
501 Requires<[IsThumb1Only, HasV6]>;
503 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
504 "rev16", " $dst, $src",
506 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
507 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
508 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
509 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
510 Requires<[IsThumb1Only, HasV6]>;
512 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
513 "revsh", " $dst, $src",
516 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
517 (shl tGPR:$src, (i32 8))), i16))]>,
518 Requires<[IsThumb1Only, HasV6]>;
520 // rotate right register
521 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
522 "ror", " $dst, $rhs",
523 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
526 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
527 "rsb", " $dst, $src, #0",
528 [(set tGPR:$dst, (ineg tGPR:$src))]>;
530 // Subtract with carry register
532 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
533 "sbc", " $dst, $rhs",
534 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
536 // Subtract immediate
537 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
538 "sub", " $dst, $lhs, $rhs",
539 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
541 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALU,
542 "sub", " $dst, $rhs",
543 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
546 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
547 "sub", " $dst, $lhs, $rhs",
548 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
550 // TODO: A7-96: STMIA - store multiple.
552 def tSUBspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALU,
553 "sub $dst, $rhs * 4", []>;
556 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
557 "sxtb", " $dst, $src",
558 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
559 Requires<[IsThumb1Only, HasV6]>;
562 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
563 "sxth", " $dst, $src",
564 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
565 Requires<[IsThumb1Only, HasV6]>;
568 let isCommutable = 1, Defs = [CPSR] in
569 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALU,
570 "tst", " $lhs, $rhs",
571 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
574 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
575 "uxtb", " $dst, $src",
576 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
577 Requires<[IsThumb1Only, HasV6]>;
580 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALU,
581 "uxth", " $dst, $src",
582 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
583 Requires<[IsThumb1Only, HasV6]>;
586 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
587 // Expanded by the scheduler into a branch sequence.
588 // FIXME: Add actual movcc in IT blocks for Thumb2.
589 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
591 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), IIC_iALU,
593 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
595 // tLEApcrel - Load a pc-relative address into a register without offending the
597 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label), IIC_iALU,
598 "adr $dst, #$label", []>;
600 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id), IIC_iALU,
601 "adr $dst, #${label}_${id:no_hash}", []>;
603 //===----------------------------------------------------------------------===//
607 // __aeabi_read_tp preserves the registers r1-r3.
610 def tTPsoft : TIx2<(outs), (ins), IIC_Br,
611 "bl __aeabi_read_tp",
612 [(set R0, ARMthread_pointer)]>;
615 //===----------------------------------------------------------------------===//
616 // Non-Instruction Patterns
620 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
621 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
622 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
623 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
624 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
625 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
627 // Subtract with carry
628 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
629 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
630 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
631 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
632 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
633 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
635 // ConstantPool, GlobalAddress
636 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
637 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
640 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
641 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
644 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
645 Requires<[IsThumb, IsNotDarwin]>;
646 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
647 Requires<[IsThumb, IsDarwin]>;
649 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
650 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
651 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
652 Requires<[IsThumb, HasV5T, IsDarwin]>;
654 // Indirect calls to ARM routines
655 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
656 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
657 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
658 Requires<[IsThumb, HasV5T, IsDarwin]>;
660 // zextload i1 -> zextload i8
661 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
662 (tLDRB t_addrmode_s1:$addr)>;
664 // extload -> zextload
665 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
666 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
667 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
669 // If it's possible to use [r,r] address mode for sextload, select to
670 // ldr{b|h} + sxt{b|h} instead.
671 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
672 (tSXTB (tLDRB t_addrmode_s1:$addr))>;
673 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
674 (tSXTH (tLDRH t_addrmode_s2:$addr))>;
677 // Large immediate handling.
680 def : T1Pat<(i32 thumb_immshifted:$src),
681 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
682 (thumb_immshifted_shamt imm:$src))>;
684 def : T1Pat<(i32 imm0_255_comp:$src),
685 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;