1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 // For both thumb1 and thumb2.
131 let isNotDuplicable = 1 in
132 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
133 "\n$cp:\n\tadd\t$dst, pc",
134 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
137 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi,
138 "add\t$dst, pc, $rhs * 4", []>;
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi,
142 "add\t$dst, $sp, $rhs * 4", []>;
145 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
146 "add\t$dst, $rhs * 4", []>;
149 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
150 "sub\t$dst, $rhs * 4", []>;
153 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
154 "add\t$dst, $rhs", []>;
157 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
158 "add\t$dst, $rhs", []>;
160 // Pseudo instruction that will expand into a tSUBspi + a copy.
161 let usesCustomInserter = 1 in { // Expanded after instruction selection.
162 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
163 NoItinerary, "@ sub\t$dst, $rhs * 4", []>;
165 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
166 NoItinerary, "@ add\t$dst, $rhs", []>;
169 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
170 NoItinerary, "@ and\t$dst, $rhs", []>;
171 } // usesCustomInserter
173 //===----------------------------------------------------------------------===//
174 // Control Flow Instructions.
177 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
178 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>;
179 // Alternative return instruction used by vararg functions.
180 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
184 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
185 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "bx\t$dst",
189 // FIXME: remove when we have a way to marking a MI with these properties.
190 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
191 hasExtraDefRegAllocReq = 1 in
192 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
196 Defs = [R0, R1, R2, R3, R12, LR,
197 D0, D1, D2, D3, D4, D5, D6, D7,
198 D16, D17, D18, D19, D20, D21, D22, D23,
199 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
200 // Also used for Thumb2
201 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
203 [(ARMtcall tglobaladdr:$func)]>,
204 Requires<[IsThumb, IsNotDarwin]>;
206 // ARMv5T and above, also used for Thumb2
207 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
209 [(ARMcall tglobaladdr:$func)]>,
210 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
212 // Also used for Thumb2
213 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
215 [(ARMtcall GPR:$func)]>,
216 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
219 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
220 "mov\tlr, pc\n\tbx\t$func",
221 [(ARMcall_nolink tGPR:$func)]>,
222 Requires<[IsThumb1Only, IsNotDarwin]>;
225 // On Darwin R9 is call-clobbered.
227 Defs = [R0, R1, R2, R3, R9, R12, LR,
228 D0, D1, D2, D3, D4, D5, D6, D7,
229 D16, D17, D18, D19, D20, D21, D22, D23,
230 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
231 // Also used for Thumb2
232 def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
234 [(ARMtcall tglobaladdr:$func)]>,
235 Requires<[IsThumb, IsDarwin]>;
237 // ARMv5T and above, also used for Thumb2
238 def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
240 [(ARMcall tglobaladdr:$func)]>,
241 Requires<[IsThumb, HasV5T, IsDarwin]>;
243 // Also used for Thumb2
244 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
246 [(ARMtcall GPR:$func)]>,
247 Requires<[IsThumb, HasV5T, IsDarwin]>;
250 def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
251 "mov\tlr, pc\n\tbx\t$func",
252 [(ARMcall_nolink tGPR:$func)]>,
253 Requires<[IsThumb1Only, IsDarwin]>;
256 let isBranch = 1, isTerminator = 1 in {
257 let isBarrier = 1 in {
258 let isPredicable = 1 in
259 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
260 "b\t$target", [(br bb:$target)]>;
264 def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br,
265 "bl\t$target\t@ far jump",[]>;
267 def tBR_JTr : T1JTI<(outs),
268 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
269 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
270 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
274 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
275 // a two-value operand where a dag node expects two operands. :(
276 let isBranch = 1, isTerminator = 1 in
277 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
279 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
281 // Compare and branch on zero / non-zero
282 let isBranch = 1, isTerminator = 1 in {
283 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
284 "cbz\t$cmp, $target", []>;
286 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
287 "cbnz\t$cmp, $target", []>;
290 //===----------------------------------------------------------------------===//
291 // Load Store Instructions.
294 let canFoldAsLoad = 1 in
295 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
296 "ldr", "\t$dst, $addr",
297 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
299 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
300 "ldrb", "\t$dst, $addr",
301 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
303 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
304 "ldrh", "\t$dst, $addr",
305 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
307 let AddedComplexity = 10 in
308 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
309 "ldrsb", "\t$dst, $addr",
310 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
312 let AddedComplexity = 10 in
313 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
314 "ldrsh", "\t$dst, $addr",
315 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
317 let canFoldAsLoad = 1 in
318 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
319 "ldr", "\t$dst, $addr",
320 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
322 // Special instruction for restore. It cannot clobber condition register
323 // when it's expanded by eliminateCallFramePseudoInstr().
324 let canFoldAsLoad = 1, mayLoad = 1 in
325 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
326 "ldr", "\t$dst, $addr", []>;
329 let canFoldAsLoad = 1 in
330 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
331 "ldr", "\t$dst, $addr",
332 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
334 // Special LDR for loads from non-pc-relative constpools.
335 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
336 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
337 "ldr", "\t$dst, $addr", []>;
339 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
340 "str", "\t$src, $addr",
341 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
343 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
344 "strb", "\t$src, $addr",
345 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
347 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
348 "strh", "\t$src, $addr",
349 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
351 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
352 "str", "\t$src, $addr",
353 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
355 let mayStore = 1 in {
356 // Special instruction for spill. It cannot clobber condition register
357 // when it's expanded by eliminateCallFramePseudoInstr().
358 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
359 "str", "\t$src, $addr", []>;
362 //===----------------------------------------------------------------------===//
363 // Load / store multiple Instructions.
366 // These requires base address to be written back or one of the loaded regs.
367 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
368 def tLDM : T1I<(outs),
369 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
371 "ldm${addr:submode}${p}\t$addr, $wb", []>;
373 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
374 def tSTM : T1I<(outs),
375 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
377 "stm${addr:submode}${p}\t$addr, $wb", []>;
379 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
380 def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
383 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
384 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
385 "push${p}\t$wb", []>;
387 //===----------------------------------------------------------------------===//
388 // Arithmetic Instructions.
391 // Add with carry register
392 let isCommutable = 1, Uses = [CPSR] in
393 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
394 "adc", "\t$dst, $rhs",
395 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
398 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
399 "add", "\t$dst, $lhs, $rhs",
400 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
402 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
403 "add", "\t$dst, $rhs",
404 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
407 let isCommutable = 1 in
408 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
409 "add", "\t$dst, $lhs, $rhs",
410 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
412 let neverHasSideEffects = 1 in
413 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
414 "add", "\t$dst, $rhs", []>;
417 let isCommutable = 1 in
418 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
419 "and", "\t$dst, $rhs",
420 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
423 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
424 "asr", "\t$dst, $lhs, $rhs",
425 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
428 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
429 "asr", "\t$dst, $rhs",
430 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
433 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
434 "bic", "\t$dst, $rhs",
435 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
438 let Defs = [CPSR] in {
439 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
440 "cmn", "\t$lhs, $rhs",
441 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
442 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
443 "cmn", "\t$lhs, $rhs",
444 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
448 let Defs = [CPSR] in {
449 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
450 "cmp", "\t$lhs, $rhs",
451 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
452 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
453 "cmp", "\t$lhs, $rhs",
454 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
459 let Defs = [CPSR] in {
460 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
461 "cmp", "\t$lhs, $rhs",
462 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
463 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
464 "cmp", "\t$lhs, $rhs",
465 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
467 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
468 "cmp", "\t$lhs, $rhs", []>;
469 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
470 "cmp", "\t$lhs, $rhs", []>;
475 let isCommutable = 1 in
476 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
477 "eor", "\t$dst, $rhs",
478 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
481 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
482 "lsl", "\t$dst, $lhs, $rhs",
483 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
486 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
487 "lsl", "\t$dst, $rhs",
488 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
491 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
492 "lsr", "\t$dst, $lhs, $rhs",
493 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
496 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
497 "lsr", "\t$dst, $rhs",
498 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
501 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
502 "mov", "\t$dst, $src",
503 [(set tGPR:$dst, imm0_255:$src)]>;
505 // TODO: A7-73: MOV(2) - mov setting flag.
508 let neverHasSideEffects = 1 in {
509 // FIXME: Make this predicable.
510 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
511 "mov\t$dst, $src", []>;
513 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
514 "movs\t$dst, $src", []>;
516 // FIXME: Make these predicable.
517 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
518 "mov\t$dst, $src", []>;
519 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
520 "mov\t$dst, $src", []>;
521 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
522 "mov\t$dst, $src", []>;
523 } // neverHasSideEffects
526 let isCommutable = 1 in
527 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
528 "mul", "\t$dst, $rhs",
529 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
531 // move inverse register
532 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
533 "mvn", "\t$dst, $src",
534 [(set tGPR:$dst, (not tGPR:$src))]>;
536 // bitwise or register
537 let isCommutable = 1 in
538 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
539 "orr", "\t$dst, $rhs",
540 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
543 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
544 "rev", "\t$dst, $src",
545 [(set tGPR:$dst, (bswap tGPR:$src))]>,
546 Requires<[IsThumb1Only, HasV6]>;
548 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
549 "rev16", "\t$dst, $src",
551 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
552 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
553 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
554 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
555 Requires<[IsThumb1Only, HasV6]>;
557 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
558 "revsh", "\t$dst, $src",
561 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
562 (shl tGPR:$src, (i32 8))), i16))]>,
563 Requires<[IsThumb1Only, HasV6]>;
565 // rotate right register
566 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
567 "ror", "\t$dst, $rhs",
568 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
571 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
572 "rsb", "\t$dst, $src, #0",
573 [(set tGPR:$dst, (ineg tGPR:$src))]>;
575 // Subtract with carry register
577 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
578 "sbc", "\t$dst, $rhs",
579 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
581 // Subtract immediate
582 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
583 "sub", "\t$dst, $lhs, $rhs",
584 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
586 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
587 "sub", "\t$dst, $rhs",
588 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
591 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
592 "sub", "\t$dst, $lhs, $rhs",
593 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
595 // TODO: A7-96: STMIA - store multiple.
598 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
599 "sxtb", "\t$dst, $src",
600 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
601 Requires<[IsThumb1Only, HasV6]>;
604 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
605 "sxth", "\t$dst, $src",
606 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
607 Requires<[IsThumb1Only, HasV6]>;
610 let isCommutable = 1, Defs = [CPSR] in
611 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
612 "tst", "\t$lhs, $rhs",
613 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
616 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
617 "uxtb", "\t$dst, $src",
618 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
619 Requires<[IsThumb1Only, HasV6]>;
622 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
623 "uxth", "\t$dst, $src",
624 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
625 Requires<[IsThumb1Only, HasV6]>;
628 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
629 // Expanded after instruction selection into a branch sequence.
630 let usesCustomInserter = 1 in // Expanded after instruction selection.
632 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
633 NoItinerary, "@ tMOVCCr $cc",
634 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
637 // 16-bit movcc in IT blocks for Thumb2.
638 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
639 "mov", "\t$dst, $rhs", []>;
641 def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
642 "mov", "\t$dst, $rhs", []>;
644 // tLEApcrel - Load a pc-relative address into a register without offending the
646 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
647 "adr$p\t$dst, #$label", []>;
649 def tLEApcrelJT : T1I<(outs tGPR:$dst),
650 (ins i32imm:$label, nohash_imm:$id, pred:$p),
651 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>;
653 //===----------------------------------------------------------------------===//
657 // __aeabi_read_tp preserves the registers r1-r3.
660 def tTPsoft : TIx2<(outs), (ins), IIC_Br,
661 "bl\t__aeabi_read_tp",
662 [(set R0, ARMthread_pointer)]>;
665 //===----------------------------------------------------------------------===//
666 // Non-Instruction Patterns
670 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
671 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
672 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
673 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
674 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
675 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
677 // Subtract with carry
678 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
679 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
680 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
681 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
682 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
683 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
685 // ConstantPool, GlobalAddress
686 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
687 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
688 def : T1Pat<(ARMWrapper tblockaddress:$dst), (tLEApcrel tblockaddress:$dst)>;
691 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
692 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
695 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
696 Requires<[IsThumb, IsNotDarwin]>;
697 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
698 Requires<[IsThumb, IsDarwin]>;
700 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
701 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
702 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
703 Requires<[IsThumb, HasV5T, IsDarwin]>;
705 // Indirect calls to ARM routines
706 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
707 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
708 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
709 Requires<[IsThumb, HasV5T, IsDarwin]>;
711 // zextload i1 -> zextload i8
712 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
713 (tLDRB t_addrmode_s1:$addr)>;
715 // extload -> zextload
716 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
717 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
718 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
720 // If it's impossible to use [r,r] address mode for sextload, select to
721 // ldr{b|h} + sxt{b|h} instead.
722 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
723 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
724 Requires<[IsThumb1Only, HasV6]>;
725 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
726 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
727 Requires<[IsThumb1Only, HasV6]>;
729 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
730 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
731 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
732 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
734 // Large immediate handling.
737 def : T1Pat<(i32 thumb_immshifted:$src),
738 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
739 (thumb_immshifted_shamt imm:$src))>;
741 def : T1Pat<(i32 imm0_255_comp:$src),
742 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;