1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
82 def t_imm0_1020s4 : Operand<i32> {
83 let PrintMethod = "printThumbS4ImmOperand";
84 let ParserMatchClass = t_imm0_1020s4_asmoperand;
85 let OperandType = "OPERAND_IMMEDIATE";
88 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
89 def t_imm0_508s4 : Operand<i32> {
90 let PrintMethod = "printThumbS4ImmOperand";
91 let ParserMatchClass = t_imm0_508s4_asmoperand;
92 let OperandType = "OPERAND_IMMEDIATE";
95 // Define Thumb specific addressing modes.
97 let OperandType = "OPERAND_PCREL" in {
98 def t_brtarget : Operand<OtherVT> {
99 let EncoderMethod = "getThumbBRTargetOpValue";
100 let DecoderMethod = "DecodeThumbBROperand";
103 def t_bcctarget : Operand<i32> {
104 let EncoderMethod = "getThumbBCCTargetOpValue";
105 let DecoderMethod = "DecodeThumbBCCTargetOperand";
108 def t_cbtarget : Operand<i32> {
109 let EncoderMethod = "getThumbCBTargetOpValue";
110 let DecoderMethod = "DecodeThumbCmpBROperand";
113 def t_bltarget : Operand<i32> {
114 let EncoderMethod = "getThumbBLTargetOpValue";
115 let DecoderMethod = "DecodeThumbBLTargetOperand";
118 def t_blxtarget : Operand<i32> {
119 let EncoderMethod = "getThumbBLXTargetOpValue";
120 let DecoderMethod = "DecodeThumbBLXOffset";
124 // t_addrmode_rr := reg + reg
126 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
127 def t_addrmode_rr : Operand<i32>,
128 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
129 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
130 let PrintMethod = "printThumbAddrModeRROperand";
131 let DecoderMethod = "DecodeThumbAddrModeRR";
132 let ParserMatchClass = t_addrmode_rr_asm_operand;
133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
136 // t_addrmode_rrs := reg + reg
138 // We use separate scaled versions because the Select* functions need
139 // to explicitly check for a matching constant and return false here so that
140 // the reg+imm forms will match instead. This is a horrible way to do that,
141 // as it forces tight coupling between the methods, but it's how selectiondag
143 def t_addrmode_rrs1 : Operand<i32>,
144 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
145 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
146 let PrintMethod = "printThumbAddrModeRROperand";
147 let DecoderMethod = "DecodeThumbAddrModeRR";
148 let ParserMatchClass = t_addrmode_rr_asm_operand;
149 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
151 def t_addrmode_rrs2 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
153 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
154 let DecoderMethod = "DecodeThumbAddrModeRR";
155 let PrintMethod = "printThumbAddrModeRROperand";
156 let ParserMatchClass = t_addrmode_rr_asm_operand;
157 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
159 def t_addrmode_rrs4 : Operand<i32>,
160 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
161 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
162 let DecoderMethod = "DecodeThumbAddrModeRR";
163 let PrintMethod = "printThumbAddrModeRROperand";
164 let ParserMatchClass = t_addrmode_rr_asm_operand;
165 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
168 // t_addrmode_is4 := reg + imm5 * 4
170 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
171 def t_addrmode_is4 : Operand<i32>,
172 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
173 let EncoderMethod = "getAddrModeISOpValue";
174 let DecoderMethod = "DecodeThumbAddrModeIS";
175 let PrintMethod = "printThumbAddrModeImm5S4Operand";
176 let ParserMatchClass = t_addrmode_is4_asm_operand;
177 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
180 // t_addrmode_is2 := reg + imm5 * 2
182 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
183 def t_addrmode_is2 : Operand<i32>,
184 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
185 let EncoderMethod = "getAddrModeISOpValue";
186 let DecoderMethod = "DecodeThumbAddrModeIS";
187 let PrintMethod = "printThumbAddrModeImm5S2Operand";
188 let ParserMatchClass = t_addrmode_is2_asm_operand;
189 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
192 // t_addrmode_is1 := reg + imm5
194 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
195 def t_addrmode_is1 : Operand<i32>,
196 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
197 let EncoderMethod = "getAddrModeISOpValue";
198 let DecoderMethod = "DecodeThumbAddrModeIS";
199 let PrintMethod = "printThumbAddrModeImm5S1Operand";
200 let ParserMatchClass = t_addrmode_is1_asm_operand;
201 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
204 // t_addrmode_sp := sp + imm8 * 4
206 // FIXME: This really shouldn't have an explicit SP operand at all. It should
207 // be implicit, just like in the instruction encoding itself.
208 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
209 def t_addrmode_sp : Operand<i32>,
210 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
211 let EncoderMethod = "getAddrModeThumbSPOpValue";
212 let DecoderMethod = "DecodeThumbAddrModeSP";
213 let PrintMethod = "printThumbAddrModeSPOperand";
214 let ParserMatchClass = t_addrmode_sp_asm_operand;
215 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
218 // t_addrmode_pc := <label> => pc + imm8 * 4
220 def t_addrmode_pc : Operand<i32> {
221 let EncoderMethod = "getAddrModePCOpValue";
222 let DecoderMethod = "DecodeThumbAddrModePC";
225 //===----------------------------------------------------------------------===//
226 // Miscellaneous Instructions.
229 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
230 // from removing one half of the matched pairs. That breaks PEI, which assumes
231 // these will always be in pairs, and asserts if it finds otherwise. Better way?
232 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
233 def tADJCALLSTACKUP :
234 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
235 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
236 Requires<[IsThumb, IsThumb1Only]>;
238 def tADJCALLSTACKDOWN :
239 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
240 [(ARMcallseq_start imm:$amt)]>,
241 Requires<[IsThumb, IsThumb1Only]>;
244 class T1SystemEncoding<bits<8> opc>
245 : T1Encoding<0b101111> {
246 let Inst{9-8} = 0b11;
250 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
251 T1SystemEncoding<0x00>, // A8.6.110
252 Requires<[IsThumb2]>;
254 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
255 T1SystemEncoding<0x10>; // A8.6.410
257 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
258 T1SystemEncoding<0x20>; // A8.6.408
260 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
261 T1SystemEncoding<0x30>; // A8.6.409
263 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
264 T1SystemEncoding<0x40>; // A8.6.157
266 // The imm operand $val can be used by a debugger to store more information
267 // about the breakpoint.
268 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
270 T1Encoding<0b101111> {
271 let Inst{9-8} = 0b10;
277 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
278 []>, T1Encoding<0b101101> {
281 let Inst{9-5} = 0b10010;
284 let Inst{2-0} = 0b000;
287 // Change Processor State is a system instruction -- for disassembly only.
288 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
289 NoItinerary, "cps$imod $iflags", []>,
297 let Inst{2-0} = iflags;
298 let DecoderMethod = "DecodeThumbCPS";
301 // For both thumb1 and thumb2.
302 let isNotDuplicable = 1, isCodeGenOnly = 1 in
303 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
304 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
305 T1Special<{0,0,?,?}> {
308 let Inst{6-3} = 0b1111; // Rm = pc
312 // ADD <Rd>, sp, #<imm8>
313 // FIXME: This should not be marked as having side effects, and it should be
314 // rematerializable. Clearing the side effect bit causes miscompilations,
315 // probably because the instruction can be moved around.
316 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
317 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
318 T1Encoding<{1,0,1,0,1,?}> {
322 let Inst{10-8} = dst;
324 let DecoderMethod = "DecodeThumbAddSpecialReg";
327 // ADD sp, sp, #<imm7>
328 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
329 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
330 T1Misc<{0,0,0,0,0,?,?}> {
334 let DecoderMethod = "DecodeThumbAddSPImm";
337 // SUB sp, sp, #<imm7>
338 // FIXME: The encoding and the ASM string don't match up.
339 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
340 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
341 T1Misc<{0,0,0,0,1,?,?}> {
345 let DecoderMethod = "DecodeThumbAddSPImm";
348 // Can optionally specify SP as a three operand instruction.
349 def : tInstAlias<"add${p} sp, sp, $imm",
350 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
351 def : tInstAlias<"sub${p} sp, sp, $imm",
352 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
355 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
356 "add", "\t$Rdn, $sp, $Rn", []>,
357 T1Special<{0,0,?,?}> {
358 // A8.6.9 Encoding T1
360 let Inst{7} = Rdn{3};
361 let Inst{6-3} = 0b1101;
362 let Inst{2-0} = Rdn{2-0};
363 let DecoderMethod = "DecodeThumbAddSPReg";
367 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
368 "add", "\t$Rdn, $Rm", []>,
369 T1Special<{0,0,?,?}> {
370 // A8.6.9 Encoding T2
374 let Inst{2-0} = 0b101;
375 let DecoderMethod = "DecodeThumbAddSPReg";
378 //===----------------------------------------------------------------------===//
379 // Control Flow Instructions.
383 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
384 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
385 T1Special<{1,1,0,?}> {
389 let Inst{2-0} = 0b000;
393 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
394 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
395 [(ARMretflag)], (tBX LR, pred:$p)>;
397 // Alternative return instruction used by vararg functions.
398 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
400 (tBX GPR:$Rm, pred:$p)>;
403 // All calls clobber the non-callee saved registers. SP is marked as a use to
404 // prevent stack-pointer assignments that appear immediately before calls from
405 // potentially appearing dead.
407 // On non-IOS platforms R9 is callee-saved.
408 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
410 // Also used for Thumb2
411 def tBL : TIx2<0b11110, 0b11, 1,
412 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
414 [(ARMtcall tglobaladdr:$func)]>,
415 Requires<[IsThumb, IsNotIOS]> {
417 let Inst{26} = func{21};
418 let Inst{25-16} = func{20-11};
421 let Inst{10-0} = func{10-0};
424 // ARMv5T and above, also used for Thumb2
425 def tBLXi : TIx2<0b11110, 0b11, 0,
426 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
428 [(ARMcall tglobaladdr:$func)]>,
429 Requires<[IsThumb, HasV5T, IsNotIOS]> {
431 let Inst{25-16} = func{20-11};
434 let Inst{10-1} = func{10-1};
435 let Inst{0} = 0; // func{0} is assumed zero
438 // Also used for Thumb2
439 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
441 [(ARMtcall GPR:$func)]>,
442 Requires<[IsThumb, HasV5T, IsNotIOS]>,
443 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
445 let Inst{6-3} = func;
446 let Inst{2-0} = 0b000;
450 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
452 [(ARMcall_nolink tGPR:$func)]>,
453 Requires<[IsThumb, IsThumb1Only, IsNotIOS]>;
457 // On IOS R9 is call-clobbered.
458 // R7 is marked as a use to prevent frame-pointer assignments from being
459 // moved above / below calls.
460 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
462 // Also used for Thumb2
463 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
464 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
465 (tBL pred:$p, t_bltarget:$func)>,
466 Requires<[IsThumb, IsIOS]>;
468 // ARMv5T and above, also used for Thumb2
469 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
470 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
471 (tBLXi pred:$p, t_blxtarget:$func)>,
472 Requires<[IsThumb, HasV5T, IsIOS]>;
474 // Also used for Thumb2
475 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
476 2, IIC_Br, [(ARMtcall GPR:$func)],
477 (tBLXr pred:$p, GPR:$func)>,
478 Requires<[IsThumb, HasV5T, IsIOS]>;
481 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
483 [(ARMcall_nolink tGPR:$func)]>,
484 Requires<[IsThumb, IsThumb1Only, IsIOS]>;
487 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
488 let isPredicable = 1 in
489 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
490 "b", "\t$target", [(br bb:$target)]>,
491 T1Encoding<{1,1,1,0,0,?}> {
493 let Inst{10-0} = target;
497 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
498 // the clobber of LR.
500 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
501 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
503 def tBR_JTr : tPseudoInst<(outs),
504 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
506 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
507 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
511 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
512 // a two-value operand where a dag node expects two operands. :(
513 let isBranch = 1, isTerminator = 1 in
514 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
516 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
517 T1BranchCond<{1,1,0,1}> {
521 let Inst{7-0} = target;
525 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
527 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
529 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
530 // on IOS), so it's in ARMInstrThumb2.td.
531 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
533 (tBX GPR:$dst, (ops 14, zero_reg))>,
534 Requires<[IsThumb, IsIOS]>;
536 // Non-IOS versions (the difference is R9).
537 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
539 def tTAILJMPdND : tPseudoExpand<(outs),
540 (ins t_brtarget:$dst, pred:$p, variable_ops),
542 (tB t_brtarget:$dst, pred:$p)>,
543 Requires<[IsThumb, IsNotIOS]>;
544 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
546 (tBX GPR:$dst, (ops 14, zero_reg))>,
547 Requires<[IsThumb, IsNotIOS]>;
552 // A8.6.218 Supervisor Call (Software Interrupt)
553 // A8.6.16 B: Encoding T1
554 // If Inst{11-8} == 0b1111 then SEE SVC
555 let isCall = 1, Uses = [SP] in
556 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
557 "svc", "\t$imm", []>, Encoding16 {
559 let Inst{15-12} = 0b1101;
560 let Inst{11-8} = 0b1111;
564 // The assembler uses 0xDEFE for a trap instruction.
565 let isBarrier = 1, isTerminator = 1 in
566 def tTRAP : TI<(outs), (ins), IIC_Br,
567 "trap", [(trap)]>, Encoding16 {
571 //===----------------------------------------------------------------------===//
572 // Load Store Instructions.
575 // Loads: reg/reg and reg/imm5
576 let canFoldAsLoad = 1, isReMaterializable = 1 in
577 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
578 Operand AddrMode_r, Operand AddrMode_i,
579 AddrMode am, InstrItinClass itin_r,
580 InstrItinClass itin_i, string asm,
583 T1pILdStEncode<reg_opc,
584 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
585 am, itin_r, asm, "\t$Rt, $addr",
586 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
588 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
589 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
590 am, itin_i, asm, "\t$Rt, $addr",
591 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
593 // Stores: reg/reg and reg/imm5
594 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
595 Operand AddrMode_r, Operand AddrMode_i,
596 AddrMode am, InstrItinClass itin_r,
597 InstrItinClass itin_i, string asm,
600 T1pILdStEncode<reg_opc,
601 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
602 am, itin_r, asm, "\t$Rt, $addr",
603 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
605 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
606 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
607 am, itin_i, asm, "\t$Rt, $addr",
608 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
612 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
613 t_addrmode_is4, AddrModeT1_4,
614 IIC_iLoad_r, IIC_iLoad_i, "ldr",
615 UnOpFrag<(load node:$Src)>>;
618 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
619 t_addrmode_is1, AddrModeT1_1,
620 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
621 UnOpFrag<(zextloadi8 node:$Src)>>;
624 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
625 t_addrmode_is2, AddrModeT1_2,
626 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
627 UnOpFrag<(zextloadi16 node:$Src)>>;
629 let AddedComplexity = 10 in
630 def tLDRSB : // A8.6.80
631 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
632 AddrModeT1_1, IIC_iLoad_bh_r,
633 "ldrsb", "\t$Rt, $addr",
634 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
636 let AddedComplexity = 10 in
637 def tLDRSH : // A8.6.84
638 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
639 AddrModeT1_2, IIC_iLoad_bh_r,
640 "ldrsh", "\t$Rt, $addr",
641 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
643 let canFoldAsLoad = 1 in
644 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
645 "ldr", "\t$Rt, $addr",
646 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
651 let Inst{7-0} = addr;
655 // FIXME: Use ldr.n to work around a darwin assembler bug.
656 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
657 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
658 "ldr", ".n\t$Rt, $addr",
659 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
660 T1Encoding<{0,1,0,0,1,?}> {
665 let Inst{7-0} = addr;
668 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
669 // For disassembly use only.
670 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
671 "ldr", "\t$Rt, $addr",
672 [/* disassembly only */]>,
673 T1Encoding<{0,1,0,0,1,?}> {
678 let Inst{7-0} = addr;
681 // A8.6.194 & A8.6.192
682 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
683 t_addrmode_is4, AddrModeT1_4,
684 IIC_iStore_r, IIC_iStore_i, "str",
685 BinOpFrag<(store node:$LHS, node:$RHS)>>;
687 // A8.6.197 & A8.6.195
688 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
689 t_addrmode_is1, AddrModeT1_1,
690 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
691 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
693 // A8.6.207 & A8.6.205
694 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
695 t_addrmode_is2, AddrModeT1_2,
696 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
697 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
700 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
701 "str", "\t$Rt, $addr",
702 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
707 let Inst{7-0} = addr;
710 //===----------------------------------------------------------------------===//
711 // Load / store multiple Instructions.
714 // These require base address to be written back or one of the loaded regs.
715 let neverHasSideEffects = 1 in {
717 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
718 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
719 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
723 let Inst{7-0} = regs;
726 // Writeback version is just a pseudo, as there's no encoding difference.
727 // Writeback happens iff the base register is not in the destination register
730 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
731 "$Rn = $wb", IIC_iLoad_mu>,
732 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
734 let OutOperandList = (outs GPR:$wb);
735 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
737 let isCodeGenOnly = 1;
739 list<Predicate> Predicates = [IsThumb];
742 // There is no non-writeback version of STM for Thumb.
743 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
744 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
745 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
746 AddrModeNone, 2, IIC_iStore_mu,
747 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
748 T1Encoding<{1,1,0,0,0,?}> {
752 let Inst{7-0} = regs;
755 } // neverHasSideEffects
757 def : InstAlias<"ldm${p} $Rn!, $regs",
758 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
759 Requires<[IsThumb, IsThumb1Only]>;
761 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
762 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
764 "pop${p}\t$regs", []>,
765 T1Misc<{1,1,0,?,?,?,?}> {
767 let Inst{8} = regs{15};
768 let Inst{7-0} = regs{7-0};
771 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
772 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
774 "push${p}\t$regs", []>,
775 T1Misc<{0,1,0,?,?,?,?}> {
777 let Inst{8} = regs{14};
778 let Inst{7-0} = regs{7-0};
781 //===----------------------------------------------------------------------===//
782 // Arithmetic Instructions.
785 // Helper classes for encoding T1pI patterns:
786 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
787 string opc, string asm, list<dag> pattern>
788 : T1pI<oops, iops, itin, opc, asm, pattern>,
789 T1DataProcessing<opA> {
795 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
796 string opc, string asm, list<dag> pattern>
797 : T1pI<oops, iops, itin, opc, asm, pattern>,
805 // Helper classes for encoding T1sI patterns:
806 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
807 string opc, string asm, list<dag> pattern>
808 : T1sI<oops, iops, itin, opc, asm, pattern>,
809 T1DataProcessing<opA> {
815 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
816 string opc, string asm, list<dag> pattern>
817 : T1sI<oops, iops, itin, opc, asm, pattern>,
826 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
827 string opc, string asm, list<dag> pattern>
828 : T1sI<oops, iops, itin, opc, asm, pattern>,
836 // Helper classes for encoding T1sIt patterns:
837 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
838 string opc, string asm, list<dag> pattern>
839 : T1sIt<oops, iops, itin, opc, asm, pattern>,
840 T1DataProcessing<opA> {
846 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
847 string opc, string asm, list<dag> pattern>
848 : T1sIt<oops, iops, itin, opc, asm, pattern>,
852 let Inst{10-8} = Rdn;
853 let Inst{7-0} = imm8;
856 // Add with carry register
857 let isCommutable = 1, Uses = [CPSR] in
859 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
860 "adc", "\t$Rdn, $Rm",
861 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
864 def tADDi3 : // A8.6.4 T1
865 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
867 "add", "\t$Rd, $Rm, $imm3",
868 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
870 let Inst{8-6} = imm3;
873 def tADDi8 : // A8.6.4 T2
874 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
875 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
876 "add", "\t$Rdn, $imm8",
877 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
880 let isCommutable = 1 in
881 def tADDrr : // A8.6.6 T1
882 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
884 "add", "\t$Rd, $Rn, $Rm",
885 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
887 let neverHasSideEffects = 1 in
888 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
889 "add", "\t$Rdn, $Rm", []>,
890 T1Special<{0,0,?,?}> {
894 let Inst{7} = Rdn{3};
896 let Inst{2-0} = Rdn{2-0};
900 let isCommutable = 1 in
901 def tAND : // A8.6.12
902 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
904 "and", "\t$Rdn, $Rm",
905 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
908 def tASRri : // A8.6.14
909 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
911 "asr", "\t$Rd, $Rm, $imm5",
912 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
914 let Inst{10-6} = imm5;
918 def tASRrr : // A8.6.15
919 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
921 "asr", "\t$Rdn, $Rm",
922 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
925 def tBIC : // A8.6.20
926 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
928 "bic", "\t$Rdn, $Rm",
929 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
932 let isCompare = 1, Defs = [CPSR] in {
933 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
934 // Compare-to-zero still works out, just not the relationals
935 //def tCMN : // A8.6.33
936 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
938 // "cmn", "\t$lhs, $rhs",
939 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
941 def tCMNz : // A8.6.33
942 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
945 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
947 } // isCompare = 1, Defs = [CPSR]
950 let isCompare = 1, Defs = [CPSR] in {
951 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
952 "cmp", "\t$Rn, $imm8",
953 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
954 T1General<{1,0,1,?,?}> {
959 let Inst{7-0} = imm8;
963 def tCMPr : // A8.6.36 T1
964 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
967 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
969 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
970 "cmp", "\t$Rn, $Rm", []>,
971 T1Special<{0,1,?,?}> {
977 let Inst{2-0} = Rn{2-0};
979 } // isCompare = 1, Defs = [CPSR]
983 let isCommutable = 1 in
984 def tEOR : // A8.6.45
985 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
987 "eor", "\t$Rdn, $Rm",
988 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
991 def tLSLri : // A8.6.88
992 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
994 "lsl", "\t$Rd, $Rm, $imm5",
995 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
997 let Inst{10-6} = imm5;
1001 def tLSLrr : // A8.6.89
1002 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1004 "lsl", "\t$Rdn, $Rm",
1005 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1008 def tLSRri : // A8.6.90
1009 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1011 "lsr", "\t$Rd, $Rm, $imm5",
1012 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
1014 let Inst{10-6} = imm5;
1018 def tLSRrr : // A8.6.91
1019 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1021 "lsr", "\t$Rdn, $Rm",
1022 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1025 let isMoveImm = 1 in
1026 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1027 "mov", "\t$Rd, $imm8",
1028 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1029 T1General<{1,0,0,?,?}> {
1033 let Inst{10-8} = Rd;
1034 let Inst{7-0} = imm8;
1036 // Because we have an explicit tMOVSr below, we need an alias to handle
1037 // the immediate "movs" form here. Blech.
1038 def : tInstAlias <"movs $Rdn, $imm",
1039 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1041 // A7-73: MOV(2) - mov setting flag.
1043 let neverHasSideEffects = 1 in {
1044 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1046 "mov", "\t$Rd, $Rm", "", []>,
1047 T1Special<{1,0,?,?}> {
1051 let Inst{7} = Rd{3};
1053 let Inst{2-0} = Rd{2-0};
1055 let Defs = [CPSR] in
1056 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1057 "movs\t$Rd, $Rm", []>, Encoding16 {
1061 let Inst{15-6} = 0b0000000000;
1065 } // neverHasSideEffects
1067 // Multiply register
1068 let isCommutable = 1 in
1069 def tMUL : // A8.6.105 T1
1070 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1071 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1072 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1073 T1DataProcessing<0b1101> {
1078 let AsmMatchConverter = "cvtThumbMultiply";
1081 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1084 // Move inverse register
1085 def tMVN : // A8.6.107
1086 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1087 "mvn", "\t$Rd, $Rn",
1088 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1090 // Bitwise or register
1091 let isCommutable = 1 in
1092 def tORR : // A8.6.114
1093 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1095 "orr", "\t$Rdn, $Rm",
1096 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1099 def tREV : // A8.6.134
1100 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1102 "rev", "\t$Rd, $Rm",
1103 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1104 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1106 def tREV16 : // A8.6.135
1107 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1109 "rev16", "\t$Rd, $Rm",
1110 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1111 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1113 def tREVSH : // A8.6.136
1114 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1116 "revsh", "\t$Rd, $Rm",
1117 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1118 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1120 // Rotate right register
1121 def tROR : // A8.6.139
1122 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1124 "ror", "\t$Rdn, $Rm",
1125 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1128 def tRSB : // A8.6.141
1129 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1131 "rsb", "\t$Rd, $Rn, #0",
1132 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1134 // Subtract with carry register
1135 let Uses = [CPSR] in
1136 def tSBC : // A8.6.151
1137 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1139 "sbc", "\t$Rdn, $Rm",
1140 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1142 // Subtract immediate
1143 def tSUBi3 : // A8.6.210 T1
1144 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1146 "sub", "\t$Rd, $Rm, $imm3",
1147 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1149 let Inst{8-6} = imm3;
1152 def tSUBi8 : // A8.6.210 T2
1153 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1154 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1155 "sub", "\t$Rdn, $imm8",
1156 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1158 // Subtract register
1159 def tSUBrr : // A8.6.212
1160 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1162 "sub", "\t$Rd, $Rn, $Rm",
1163 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1166 def tSXTB : // A8.6.222
1167 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1169 "sxtb", "\t$Rd, $Rm",
1170 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1171 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1173 // Sign-extend short
1174 def tSXTH : // A8.6.224
1175 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1177 "sxth", "\t$Rd, $Rm",
1178 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1179 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1182 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1183 def tTST : // A8.6.230
1184 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1185 "tst", "\t$Rn, $Rm",
1186 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1189 def tUXTB : // A8.6.262
1190 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1192 "uxtb", "\t$Rd, $Rm",
1193 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1194 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1196 // Zero-extend short
1197 def tUXTH : // A8.6.264
1198 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1200 "uxth", "\t$Rd, $Rm",
1201 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1202 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1204 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1205 // Expanded after instruction selection into a branch sequence.
1206 let usesCustomInserter = 1 in // Expanded after instruction selection.
1207 def tMOVCCr_pseudo :
1208 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1210 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1212 // tLEApcrel - Load a pc-relative address into a register without offending the
1215 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1216 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1217 T1Encoding<{1,0,1,0,0,?}> {
1220 let Inst{10-8} = Rd;
1221 let Inst{7-0} = addr;
1222 let DecoderMethod = "DecodeThumbAddSpecialReg";
1225 let neverHasSideEffects = 1, isReMaterializable = 1 in
1226 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1229 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1230 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1233 //===----------------------------------------------------------------------===//
1237 // __aeabi_read_tp preserves the registers r1-r3.
1238 // This is a pseudo inst so that we can get the encoding right,
1239 // complete with fixup for the aeabi_read_tp function.
1240 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1241 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1242 [(set R0, ARMthread_pointer)]>;
1244 //===----------------------------------------------------------------------===//
1245 // SJLJ Exception handling intrinsics
1248 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1249 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1250 // from some other function to get here, and we're using the stack frame for the
1251 // containing function to save/restore registers, we can't keep anything live in
1252 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1253 // tromped upon when we get here from a longjmp(). We force everything out of
1254 // registers except for our own input by listing the relevant registers in
1255 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1256 // preserve all of the callee-saved resgisters, which is exactly what we want.
1257 // $val is a scratch register for our use.
1258 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1259 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1260 usesCustomInserter = 1 in
1261 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1262 AddrModeNone, 0, NoItinerary, "","",
1263 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1265 // FIXME: Non-IOS version(s)
1266 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1267 Defs = [ R7, LR, SP ] in
1268 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1269 AddrModeNone, 0, IndexModeNone,
1270 Pseudo, NoItinerary, "", "",
1271 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1272 Requires<[IsThumb, IsIOS]>;
1274 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1276 def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
1278 //===----------------------------------------------------------------------===//
1279 // Non-Instruction Patterns
1283 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1284 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1285 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1286 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1289 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1290 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1291 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1292 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1293 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1294 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1296 // Subtract with carry
1297 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1298 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1299 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1300 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1301 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1302 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1304 // ConstantPool, GlobalAddress
1305 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1306 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1309 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1310 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1313 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1314 Requires<[IsThumb, IsNotIOS]>;
1315 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1316 Requires<[IsThumb, IsIOS]>;
1318 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1319 Requires<[IsThumb, HasV5T, IsNotIOS]>;
1320 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1321 Requires<[IsThumb, HasV5T, IsIOS]>;
1323 // Indirect calls to ARM routines
1324 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1325 Requires<[IsThumb, HasV5T, IsNotIOS]>;
1326 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1327 Requires<[IsThumb, HasV5T, IsIOS]>;
1329 // zextload i1 -> zextload i8
1330 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1331 (tLDRBr t_addrmode_rrs1:$addr)>;
1332 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1333 (tLDRBi t_addrmode_is1:$addr)>;
1335 // extload -> zextload
1336 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1337 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1338 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1339 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1340 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1341 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1343 // If it's impossible to use [r,r] address mode for sextload, select to
1344 // ldr{b|h} + sxt{b|h} instead.
1345 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1346 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1347 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1348 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1349 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1350 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1351 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1352 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1353 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1354 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1355 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1356 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1358 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1359 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1360 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1361 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1362 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1363 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1364 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1365 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1367 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1368 (tLDRBi t_addrmode_is1:$src)>;
1369 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1370 (tLDRBr t_addrmode_rrs1:$src)>;
1371 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1372 (tLDRHi t_addrmode_is2:$src)>;
1373 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1374 (tLDRHr t_addrmode_rrs2:$src)>;
1375 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1376 (tLDRi t_addrmode_is4:$src)>;
1377 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1378 (tLDRr t_addrmode_rrs4:$src)>;
1379 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1380 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1381 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1382 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1383 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1384 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1385 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1386 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1387 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1388 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1389 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1390 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1392 // Large immediate handling.
1395 def : T1Pat<(i32 thumb_immshifted:$src),
1396 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1397 (thumb_immshifted_shamt imm:$src))>;
1399 def : T1Pat<(i32 imm0_255_comp:$src),
1400 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1402 // Pseudo instruction that combines ldr from constpool and add pc. This should
1403 // be expanded into two instructions late to allow if-conversion and
1405 let isReMaterializable = 1 in
1406 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1408 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1410 Requires<[IsThumb, IsThumb1Only]>;
1412 // Pseudo-instruction for merged POP and return.
1413 // FIXME: remove when we have a way to marking a MI with these properties.
1414 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1415 hasExtraDefRegAllocReq = 1 in
1416 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1418 (tPOP pred:$p, reglist:$regs)>;
1420 // Indirect branch using "mov pc, $Rm"
1421 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1422 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1423 2, IIC_Br, [(brind GPR:$Rm)],
1424 (tMOVr PC, GPR:$Rm, pred:$p)>;
1428 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1429 // encoding is available on ARMv6K, but we don't differentiate that finely.
1430 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1433 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1434 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1435 // a useful extention and assembles to defined behaviour (the insn does
1437 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1438 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1440 // "neg" is and alias for "rsb rd, rn, #0"
1441 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1442 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;