1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
130 "${:comment} tADJCALLSTACKUP $amt1",
131 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
133 def tADJCALLSTACKDOWN :
134 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
135 "${:comment} tADJCALLSTACKDOWN $amt",
136 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
139 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
140 [/* For disassembly only; pattern left blank */]>,
141 T1Encoding<0b101111> {
142 let Inst{9-8} = 0b11;
143 let Inst{7-0} = 0b00000000;
146 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
147 [/* For disassembly only; pattern left blank */]>,
148 T1Encoding<0b101111> {
149 let Inst{9-8} = 0b11;
150 let Inst{7-0} = 0b00010000;
153 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
154 [/* For disassembly only; pattern left blank */]>,
155 T1Encoding<0b101111> {
156 let Inst{9-8} = 0b11;
157 let Inst{7-0} = 0b00100000;
160 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
161 [/* For disassembly only; pattern left blank */]>,
162 T1Encoding<0b101111> {
163 let Inst{9-8} = 0b11;
164 let Inst{7-0} = 0b00110000;
167 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
168 [/* For disassembly only; pattern left blank */]>,
169 T1Encoding<0b101111> {
170 let Inst{9-8} = 0b11;
171 let Inst{7-0} = 0b01000000;
174 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
175 [/* For disassembly only; pattern left blank */]>,
176 T1Encoding<0b101101> {
177 let Inst{9-5} = 0b10010;
181 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
182 [/* For disassembly only; pattern left blank */]>,
183 T1Encoding<0b101101> {
184 let Inst{9-5} = 0b10010;
188 // The i32imm operand $val can be used by a debugger to store more information
189 // about the breakpoint.
190 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
191 [/* For disassembly only; pattern left blank */]>,
192 T1Encoding<0b101111> {
193 let Inst{9-8} = 0b10;
196 // Change Processor State is a system instruction -- for disassembly only.
197 // The singleton $opt operand contains the following information:
198 // opt{4-0} = mode ==> don't care
199 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
200 // opt{8-6} = AIF from Inst{2-0}
201 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
203 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
204 // CPS which has more options.
205 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
206 [/* For disassembly only; pattern left blank */]>,
209 // For both thumb1 and thumb2.
210 let isNotDuplicable = 1 in
211 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
212 "\n$cp:\n\tadd\t$dst, pc",
213 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
214 T1Special<{0,0,?,?}> {
215 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
219 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
220 "add\t$dst, pc, $rhs", []>,
221 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
224 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
225 "add\t$dst, $sp, $rhs", []>,
226 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
229 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
230 "add\t$dst, $rhs", []>,
231 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
234 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
235 "sub\t$dst, $rhs", []>,
236 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
239 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
240 "add\t$dst, $rhs", []>,
241 T1Special<{0,0,?,?}> {
242 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
246 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
247 "add\t$dst, $rhs", []>,
248 T1Special<{0,0,?,?}> {
249 // A8.6.9 Encoding T2
251 let Inst{2-0} = 0b101;
254 //===----------------------------------------------------------------------===//
255 // Control Flow Instructions.
258 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
259 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
260 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
261 let Inst{6-3} = 0b1110; // Rm = lr
263 // Alternative return instruction used by vararg functions.
264 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
265 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
269 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
270 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
272 T1Special<{1,0,1,?}> {
273 // <Rd> = Inst{7:2-0} = pc
274 let Inst{2-0} = 0b111;
278 // FIXME: remove when we have a way to marking a MI with these properties.
279 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
280 hasExtraDefRegAllocReq = 1 in
281 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br,
282 "pop${p}\t$dsts", []>,
283 T1Misc<{1,1,0,?,?,?,?}>;
286 Defs = [R0, R1, R2, R3, R12, LR,
287 D0, D1, D2, D3, D4, D5, D6, D7,
288 D16, D17, D18, D19, D20, D21, D22, D23,
289 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
290 // Also used for Thumb2
291 def tBL : TIx2<0b11110, 0b11, 1,
292 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
294 [(ARMtcall tglobaladdr:$func)]>,
295 Requires<[IsThumb, IsNotDarwin]>;
297 // ARMv5T and above, also used for Thumb2
298 def tBLXi : TIx2<0b11110, 0b11, 0,
299 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
301 [(ARMcall tglobaladdr:$func)]>,
302 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
304 // Also used for Thumb2
305 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
307 [(ARMtcall GPR:$func)]>,
308 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
309 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
312 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
313 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
314 "mov\tlr, pc\n\tbx\t$func",
315 [(ARMcall_nolink tGPR:$func)]>,
316 Requires<[IsThumb1Only, IsNotDarwin]>;
319 // On Darwin R9 is call-clobbered.
321 Defs = [R0, R1, R2, R3, R9, R12, LR,
322 D0, D1, D2, D3, D4, D5, D6, D7,
323 D16, D17, D18, D19, D20, D21, D22, D23,
324 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
325 // Also used for Thumb2
326 def tBLr9 : TIx2<0b11110, 0b11, 1,
327 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
329 [(ARMtcall tglobaladdr:$func)]>,
330 Requires<[IsThumb, IsDarwin]>;
332 // ARMv5T and above, also used for Thumb2
333 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
334 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
336 [(ARMcall tglobaladdr:$func)]>,
337 Requires<[IsThumb, HasV5T, IsDarwin]>;
339 // Also used for Thumb2
340 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
342 [(ARMtcall GPR:$func)]>,
343 Requires<[IsThumb, HasV5T, IsDarwin]>,
344 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
347 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
348 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
349 "mov\tlr, pc\n\tbx\t$func",
350 [(ARMcall_nolink tGPR:$func)]>,
351 Requires<[IsThumb1Only, IsDarwin]>;
354 let isBranch = 1, isTerminator = 1 in {
355 let isBarrier = 1 in {
356 let isPredicable = 1 in
357 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
358 "b\t$target", [(br bb:$target)]>,
359 T1Encoding<{1,1,1,0,0,?}>;
363 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
364 "bl\t$target\t${:comment} far jump",[]>;
366 def tBR_JTr : T1JTI<(outs),
367 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
368 IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
369 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
371 let Inst{15-7} = 0b010001101;
372 let Inst{2-0} = 0b111;
377 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
378 // a two-value operand where a dag node expects two operands. :(
379 let isBranch = 1, isTerminator = 1 in
380 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
382 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
383 T1Encoding<{1,1,0,1,?,?}>;
385 // Compare and branch on zero / non-zero
386 let isBranch = 1, isTerminator = 1 in {
387 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
388 "cbz\t$cmp, $target", []>,
389 T1Misc<{0,0,?,1,?,?,?}>;
391 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
392 "cbnz\t$cmp, $target", []>,
393 T1Misc<{1,0,?,1,?,?,?}>;
396 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
397 // A8.6.16 B: Encoding T1
398 // If Inst{11-8} == 0b1111 then SEE SVC
400 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
402 let Inst{15-12} = 0b1101;
403 let Inst{11-8} = 0b1111;
407 // A8.6.16 B: Encoding T1
408 // If Inst{11-8} == 0b1110 then UNDEFINED
409 // FIXME: Temporary emitted as raw bytes until this pseudo-op will be added to
411 let isBarrier = 1, isTerminator = 1 in
412 def tTRAP : TI<(outs), (ins), IIC_Br,
413 ".short 0xdefe ${:comment} trap", [(trap)]>, Encoding16 {
414 let Inst{15-12} = 0b1101;
415 let Inst{11-8} = 0b1110;
418 //===----------------------------------------------------------------------===//
419 // Load Store Instructions.
422 let canFoldAsLoad = 1, isReMaterializable = 1 in
423 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
424 "ldr", "\t$dst, $addr",
425 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
427 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
428 "ldr", "\t$dst, $addr",
432 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
433 "ldrb", "\t$dst, $addr",
434 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
436 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
437 "ldrb", "\t$dst, $addr",
441 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
442 "ldrh", "\t$dst, $addr",
443 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
445 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
446 "ldrh", "\t$dst, $addr",
450 let AddedComplexity = 10 in
451 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
452 "ldrsb", "\t$dst, $addr",
453 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
456 let AddedComplexity = 10 in
457 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
458 "ldrsh", "\t$dst, $addr",
459 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
462 let canFoldAsLoad = 1 in
463 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
464 "ldr", "\t$dst, $addr",
465 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
468 // Special instruction for restore. It cannot clobber condition register
469 // when it's expanded by eliminateCallFramePseudoInstr().
470 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
471 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
472 "ldr", "\t$dst, $addr", []>,
476 // FIXME: Use ldr.n to work around a Darwin assembler bug.
477 let canFoldAsLoad = 1, isReMaterializable = 1 in
478 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
479 "ldr", ".n\t$dst, $addr",
480 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
481 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
483 // Special LDR for loads from non-pc-relative constpools.
484 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
485 isReMaterializable = 1 in
486 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
487 "ldr", "\t$dst, $addr", []>,
490 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
491 "str", "\t$src, $addr",
492 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
494 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
495 "str", "\t$src, $addr",
499 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
500 "strb", "\t$src, $addr",
501 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
503 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
504 "strb", "\t$src, $addr",
508 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
509 "strh", "\t$src, $addr",
510 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
512 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
513 "strh", "\t$src, $addr",
517 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
518 "str", "\t$src, $addr",
519 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
522 let mayStore = 1, neverHasSideEffects = 1 in {
523 // Special instruction for spill. It cannot clobber condition register
524 // when it's expanded by eliminateCallFramePseudoInstr().
525 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
526 "str", "\t$src, $addr", []>,
530 //===----------------------------------------------------------------------===//
531 // Load / store multiple Instructions.
534 // These requires base address to be written back or one of the loaded regs.
535 let mayLoad = 1, neverHasSideEffects = 1, hasExtraDefRegAllocReq = 1 in {
536 def tLDM : T1I<(outs),
537 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
539 "ldm${addr:submode}${p}\t$addr, $dsts", []>,
540 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
542 def tLDM_UPD : T1It<(outs tGPR:$wb),
543 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
545 "ldm${addr:submode}${p}\t$addr!, $dsts",
546 "$addr.addr = $wb", []>,
547 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
548 } // mayLoad, neverHasSideEffects = 1, hasExtraDefRegAllocReq
550 let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1 in
551 def tSTM_UPD : T1It<(outs tGPR:$wb),
552 (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops),
554 "stm${addr:submode}${p}\t$addr!, $srcs",
555 "$addr.addr = $wb", []>,
556 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
558 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
559 def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br,
560 "pop${p}\t$dsts", []>,
561 T1Misc<{1,1,0,?,?,?,?}>;
563 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
564 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops), IIC_Br,
565 "push${p}\t$srcs", []>,
566 T1Misc<{0,1,0,?,?,?,?}>;
568 //===----------------------------------------------------------------------===//
569 // Arithmetic Instructions.
572 // Add with carry register
573 let isCommutable = 1, Uses = [CPSR] in
574 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
575 "adc", "\t$dst, $rhs",
576 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
577 T1DataProcessing<0b0101>;
580 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
581 "add", "\t$dst, $lhs, $rhs",
582 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
585 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
586 "add", "\t$dst, $rhs",
587 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
588 T1General<{1,1,0,?,?}>;
591 let isCommutable = 1 in
592 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
593 "add", "\t$dst, $lhs, $rhs",
594 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
597 let neverHasSideEffects = 1 in
598 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
599 "add", "\t$dst, $rhs", []>,
600 T1Special<{0,0,?,?}>;
603 let isCommutable = 1 in
604 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
605 "and", "\t$dst, $rhs",
606 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
607 T1DataProcessing<0b0000>;
610 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
611 "asr", "\t$dst, $lhs, $rhs",
612 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
613 T1General<{0,1,0,?,?}>;
616 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
617 "asr", "\t$dst, $rhs",
618 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
619 T1DataProcessing<0b0100>;
622 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
623 "bic", "\t$dst, $rhs",
624 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
625 T1DataProcessing<0b1110>;
628 let Defs = [CPSR] in {
629 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
630 // Compare-to-zero still works out, just not the relationals
631 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
632 // "cmn", "\t$lhs, $rhs",
633 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
634 // T1DataProcessing<0b1011>;
635 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
636 "cmn", "\t$lhs, $rhs",
637 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
638 T1DataProcessing<0b1011>;
642 let Defs = [CPSR] in {
643 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
644 "cmp", "\t$lhs, $rhs",
645 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
646 T1General<{1,0,1,?,?}>;
647 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
648 "cmp", "\t$lhs, $rhs",
649 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
650 T1General<{1,0,1,?,?}>;
654 let Defs = [CPSR] in {
655 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
656 "cmp", "\t$lhs, $rhs",
657 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
658 T1DataProcessing<0b1010>;
659 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
660 "cmp", "\t$lhs, $rhs",
661 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
662 T1DataProcessing<0b1010>;
664 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
665 "cmp", "\t$lhs, $rhs", []>,
666 T1Special<{0,1,?,?}>;
667 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
668 "cmp", "\t$lhs, $rhs", []>,
669 T1Special<{0,1,?,?}>;
674 let isCommutable = 1 in
675 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
676 "eor", "\t$dst, $rhs",
677 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
678 T1DataProcessing<0b0001>;
681 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
682 "lsl", "\t$dst, $lhs, $rhs",
683 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
684 T1General<{0,0,0,?,?}>;
687 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
688 "lsl", "\t$dst, $rhs",
689 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
690 T1DataProcessing<0b0010>;
693 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
694 "lsr", "\t$dst, $lhs, $rhs",
695 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
696 T1General<{0,0,1,?,?}>;
699 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
700 "lsr", "\t$dst, $rhs",
701 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
702 T1DataProcessing<0b0011>;
705 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
706 "mov", "\t$dst, $src",
707 [(set tGPR:$dst, imm0_255:$src)]>,
708 T1General<{1,0,0,?,?}>;
710 // TODO: A7-73: MOV(2) - mov setting flag.
713 let neverHasSideEffects = 1 in {
714 // FIXME: Make this predicable.
715 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
716 "mov\t$dst, $src", []>,
719 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
720 "movs\t$dst, $src", []>, Encoding16 {
721 let Inst{15-6} = 0b0000000000;
724 // FIXME: Make these predicable.
725 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
726 "mov\t$dst, $src", []>,
727 T1Special<{1,0,0,?}>;
728 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
729 "mov\t$dst, $src", []>,
730 T1Special<{1,0,?,0}>;
731 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
732 "mov\t$dst, $src", []>,
733 T1Special<{1,0,?,?}>;
734 } // neverHasSideEffects
737 let isCommutable = 1 in
738 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
739 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
740 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
741 T1DataProcessing<0b1101>;
743 // move inverse register
744 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
745 "mvn", "\t$dst, $src",
746 [(set tGPR:$dst, (not tGPR:$src))]>,
747 T1DataProcessing<0b1111>;
749 // bitwise or register
750 let isCommutable = 1 in
751 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
752 "orr", "\t$dst, $rhs",
753 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
754 T1DataProcessing<0b1100>;
757 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
758 "rev", "\t$dst, $src",
759 [(set tGPR:$dst, (bswap tGPR:$src))]>,
760 Requires<[IsThumb1Only, HasV6]>,
761 T1Misc<{1,0,1,0,0,0,?}>;
763 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
764 "rev16", "\t$dst, $src",
766 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
767 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
768 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
769 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
770 Requires<[IsThumb1Only, HasV6]>,
771 T1Misc<{1,0,1,0,0,1,?}>;
773 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
774 "revsh", "\t$dst, $src",
777 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
778 (shl tGPR:$src, (i32 8))), i16))]>,
779 Requires<[IsThumb1Only, HasV6]>,
780 T1Misc<{1,0,1,0,1,1,?}>;
782 // rotate right register
783 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
784 "ror", "\t$dst, $rhs",
785 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
786 T1DataProcessing<0b0111>;
789 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
790 "rsb", "\t$dst, $src, #0",
791 [(set tGPR:$dst, (ineg tGPR:$src))]>,
792 T1DataProcessing<0b1001>;
794 // Subtract with carry register
796 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
797 "sbc", "\t$dst, $rhs",
798 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
799 T1DataProcessing<0b0110>;
801 // Subtract immediate
802 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
803 "sub", "\t$dst, $lhs, $rhs",
804 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
807 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
808 "sub", "\t$dst, $rhs",
809 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
810 T1General<{1,1,1,?,?}>;
813 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
814 "sub", "\t$dst, $lhs, $rhs",
815 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
818 // TODO: A7-96: STMIA - store multiple.
821 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
822 "sxtb", "\t$dst, $src",
823 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
824 Requires<[IsThumb1Only, HasV6]>,
825 T1Misc<{0,0,1,0,0,1,?}>;
828 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
829 "sxth", "\t$dst, $src",
830 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
831 Requires<[IsThumb1Only, HasV6]>,
832 T1Misc<{0,0,1,0,0,0,?}>;
835 let isCommutable = 1, Defs = [CPSR] in
836 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
837 "tst", "\t$lhs, $rhs",
838 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
839 T1DataProcessing<0b1000>;
842 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
843 "uxtb", "\t$dst, $src",
844 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
845 Requires<[IsThumb1Only, HasV6]>,
846 T1Misc<{0,0,1,0,1,1,?}>;
849 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
850 "uxth", "\t$dst, $src",
851 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
852 Requires<[IsThumb1Only, HasV6]>,
853 T1Misc<{0,0,1,0,1,0,?}>;
856 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
857 // Expanded after instruction selection into a branch sequence.
858 let usesCustomInserter = 1 in // Expanded after instruction selection.
860 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
861 NoItinerary, "${:comment} tMOVCCr $cc",
862 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
865 // 16-bit movcc in IT blocks for Thumb2.
866 let neverHasSideEffects = 1 in {
867 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
868 "mov", "\t$dst, $rhs", []>,
869 T1Special<{1,0,?,?}>;
871 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
872 "mov", "\t$dst, $rhs", []>,
873 T1General<{1,0,0,?,?}>;
874 } // neverHasSideEffects
876 // tLEApcrel - Load a pc-relative address into a register without offending the
878 let neverHasSideEffects = 1 in {
879 let isReMaterializable = 1 in
880 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
881 "adr$p\t$dst, #$label", []>,
882 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
884 } // neverHasSideEffects
885 def tLEApcrelJT : T1I<(outs tGPR:$dst),
886 (ins i32imm:$label, nohash_imm:$id, pred:$p),
887 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
888 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
890 //===----------------------------------------------------------------------===//
894 // __aeabi_read_tp preserves the registers r1-r3.
897 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
898 "bl\t__aeabi_read_tp",
899 [(set R0, ARMthread_pointer)]>;
902 // SJLJ Exception handling intrinsics
903 // eh_sjlj_setjmp() is an instruction sequence to store the return
904 // address and save #0 in R0 for the non-longjmp case.
905 // Since by its nature we may be coming from some other function to get
906 // here, and we're using the stack frame for the containing function to
907 // save/restore registers, we can't keep anything live in regs across
908 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
909 // when we get here from a longjmp(). We force everthing out of registers
910 // except for our own input by listing the relevant registers in Defs. By
911 // doing so, we also cause the prologue/epilogue code to actively preserve
912 // all of the callee-saved resgisters, which is exactly what we want.
913 // $val is a scratch register for our use.
915 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
917 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
918 AddrModeNone, SizeSpecial, NoItinerary,
919 "mov\t$val, pc\t${:comment} begin eh.setjmp\n\t"
921 "str\t$val, [$src, #4]\n\t"
924 "movs\tr0, #1\t${:comment} end eh.setjmp\n\t"
926 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
929 // FIXME: Non-Darwin version(s)
930 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1,
931 Defs = [ R7, LR, SP ] in {
932 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
933 AddrModeNone, SizeSpecial, IndexModeNone,
935 "ldr\t$scratch, [$src, #8]\n\t"
936 "mov\tsp, $scratch\n\t"
937 "ldr\t$scratch, [$src, #4]\n\t"
938 "ldr\tr7, [$src]\n\t"
940 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
941 Requires<[IsThumb, IsDarwin]>;
944 //===----------------------------------------------------------------------===//
945 // Non-Instruction Patterns
949 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
950 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
951 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
952 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
953 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
954 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
956 // Subtract with carry
957 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
958 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
959 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
960 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
961 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
962 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
964 // ConstantPool, GlobalAddress
965 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
966 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
969 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
970 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
973 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
974 Requires<[IsThumb, IsNotDarwin]>;
975 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
976 Requires<[IsThumb, IsDarwin]>;
978 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
979 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
980 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
981 Requires<[IsThumb, HasV5T, IsDarwin]>;
983 // Indirect calls to ARM routines
984 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
985 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
986 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
987 Requires<[IsThumb, HasV5T, IsDarwin]>;
989 // zextload i1 -> zextload i8
990 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
991 (tLDRB t_addrmode_s1:$addr)>;
993 // extload -> zextload
994 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
995 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
996 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
998 // If it's impossible to use [r,r] address mode for sextload, select to
999 // ldr{b|h} + sxt{b|h} instead.
1000 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1001 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1002 Requires<[IsThumb1Only, HasV6]>;
1003 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1004 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1005 Requires<[IsThumb1Only, HasV6]>;
1007 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1008 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1009 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1010 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1012 // Large immediate handling.
1015 def : T1Pat<(i32 thumb_immshifted:$src),
1016 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1017 (thumb_immshifted_shamt imm:$src))>;
1019 def : T1Pat<(i32 imm0_255_comp:$src),
1020 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1022 // Pseudo instruction that combines ldr from constpool and add pc. This should
1023 // be expanded into two instructions late to allow if-conversion and
1025 let isReMaterializable = 1 in
1026 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1028 "${:comment} ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
1029 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1031 Requires<[IsThumb1Only]>;