1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
136 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
137 "add $dst, pc, $rhs * 4", []>;
140 // FIXME: hard code sp?
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
142 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
145 // FIXME: hard code sp?
146 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
147 "add $dst, $rhs * 4", []>;
149 // FIXME: Make use of the following?
153 //===----------------------------------------------------------------------===//
154 // Control Flow Instructions.
157 let isReturn = 1, isTerminator = 1 in {
158 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
159 // Alternative return instruction used by vararg functions.
160 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
163 // FIXME: remove when we have a way to marking a MI with these properties.
164 let isReturn = 1, isTerminator = 1 in
165 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
169 Defs = [R0, R1, R2, R3, R12, LR,
170 D0, D1, D2, D3, D4, D5, D6, D7,
171 D16, D17, D18, D19, D20, D21, D22, D23,
172 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
173 // Also used for Thumb2
174 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
176 [(ARMtcall tglobaladdr:$func)]>,
177 Requires<[IsThumb, IsNotDarwin]>;
179 // ARMv5T and above, also used for Thumb2
180 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
182 [(ARMcall tglobaladdr:$func)]>,
183 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
185 // Also used for Thumb2
186 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops),
188 [(ARMtcall GPR:$func)]>,
189 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
192 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops),
193 "mov lr, pc\n\tbx $func",
194 [(ARMcall_nolink tGPR:$func)]>,
195 Requires<[IsThumb1Only, IsNotDarwin]>;
198 // On Darwin R9 is call-clobbered.
200 Defs = [R0, R1, R2, R3, R9, R12, LR,
201 D0, D1, D2, D3, D4, D5, D6, D7,
202 D16, D17, D18, D19, D20, D21, D22, D23,
203 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
204 // Also used for Thumb2
205 def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops),
207 [(ARMtcall tglobaladdr:$func)]>,
208 Requires<[IsThumb, IsDarwin]>;
210 // ARMv5T and above, also used for Thumb2
211 def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops),
213 [(ARMcall tglobaladdr:$func)]>,
214 Requires<[IsThumb, HasV5T, IsDarwin]>;
216 // Also used for Thumb2
217 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops),
219 [(ARMtcall GPR:$func)]>,
220 Requires<[IsThumb, HasV5T, IsDarwin]>;
223 def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops),
224 "mov lr, pc\n\tbx $func",
225 [(ARMcall_nolink tGPR:$func)]>,
226 Requires<[IsThumb1Only, IsDarwin]>;
229 let isBranch = 1, isTerminator = 1 in {
230 let isBarrier = 1 in {
231 let isPredicable = 1 in
232 def tB : T1I<(outs), (ins brtarget:$target), "b $target",
236 def tBfar : TIx2<(outs), (ins brtarget:$target),
237 "bl $target\t@ far jump",[]>;
239 def tBR_JTr : T1JTI<(outs),
240 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
241 "mov pc, $target\n\t.align\t2\n$jt",
242 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
246 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
247 // a two-value operand where a dag node expects two operands. :(
248 let isBranch = 1, isTerminator = 1 in
249 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
250 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
252 //===----------------------------------------------------------------------===//
253 // Load Store Instructions.
256 let canFoldAsLoad = 1 in
257 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
258 "ldr", " $dst, $addr",
259 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
261 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
262 "ldrb", " $dst, $addr",
263 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
265 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
266 "ldrh", " $dst, $addr",
267 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
269 let AddedComplexity = 10 in
270 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
271 "ldrsb", " $dst, $addr",
272 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
274 let AddedComplexity = 10 in
275 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
276 "ldrsh", " $dst, $addr",
277 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
279 let canFoldAsLoad = 1 in
280 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
281 "ldr", " $dst, $addr",
282 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
284 // Special instruction for restore. It cannot clobber condition register
285 // when it's expanded by eliminateCallFramePseudoInstr().
286 let canFoldAsLoad = 1, mayLoad = 1 in
287 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
288 "ldr", " $dst, $addr", []>;
291 let canFoldAsLoad = 1 in
292 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
293 "ldr", " $dst, $addr",
294 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
296 // Special LDR for loads from non-pc-relative constpools.
297 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
298 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
299 "ldr", " $dst, $addr", []>;
301 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
302 "str", " $src, $addr",
303 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
305 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
306 "strb", " $src, $addr",
307 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
309 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
310 "strh", " $src, $addr",
311 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
313 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
314 "str", " $src, $addr",
315 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
317 let mayStore = 1 in {
318 // Special instruction for spill. It cannot clobber condition register
319 // when it's expanded by eliminateCallFramePseudoInstr().
320 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
321 "str", " $src, $addr", []>;
324 //===----------------------------------------------------------------------===//
325 // Load / store multiple Instructions.
328 // TODO: A7-44: LDMIA - load multiple
329 // TODO: Allow these to be predicated
332 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
336 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
339 //===----------------------------------------------------------------------===//
340 // Arithmetic Instructions.
343 // Add with carry register
344 let isCommutable = 1, Uses = [CPSR] in
345 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
346 "adc", " $dst, $rhs",
347 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
350 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
351 "add", " $dst, $lhs, $rhs",
352 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
354 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
355 "add", " $dst, $rhs",
356 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
359 let isCommutable = 1 in
360 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
361 "add", " $dst, $lhs, $rhs",
362 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
364 let neverHasSideEffects = 1 in
365 def tADDhirr : T1pIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
366 "add", " $dst, $rhs @ addhirr", []>;
369 let isCommutable = 1 in
370 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
371 "and", " $dst, $rhs",
372 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
375 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
376 "asr", " $dst, $lhs, $rhs",
377 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
380 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
381 "asr", " $dst, $rhs",
382 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
385 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
386 "bic", " $dst, $rhs",
387 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
390 let Defs = [CPSR] in {
391 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
392 "cmn", " $lhs, $rhs",
393 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
394 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
395 "cmn", " $lhs, $rhs",
396 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
400 let Defs = [CPSR] in {
401 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
402 "cmp", " $lhs, $rhs",
403 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
404 def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
405 "cmp", " $lhs, $rhs",
406 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
411 let Defs = [CPSR] in {
412 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
413 "cmp", " $lhs, $rhs",
414 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
415 def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
416 "cmp", " $lhs, $rhs",
417 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
419 // TODO: Make use of the followings cmp hi regs
420 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
421 "cmp", " $lhs, $rhs", []>;
422 def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
423 "cmp", " $lhs, $rhs", []>;
428 let isCommutable = 1 in
429 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
430 "eor", " $dst, $rhs",
431 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
434 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
435 "lsl", " $dst, $lhs, $rhs",
436 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
439 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
440 "lsl", " $dst, $rhs",
441 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
444 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
445 "lsr", " $dst, $lhs, $rhs",
446 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
449 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
450 "lsr", " $dst, $rhs",
451 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
454 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src),
455 "mov", " $dst, $src",
456 [(set tGPR:$dst, imm0_255:$src)]>;
458 // TODO: A7-73: MOV(2) - mov setting flag.
461 let neverHasSideEffects = 1 in {
462 // FIXME: Make this predicable.
463 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
464 "mov $dst, $src", []>;
466 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
467 "movs $dst, $src", []>;
469 // FIXME: Make these predicable.
470 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src),
471 "mov $dst, $src\t@ hir2lor", []>;
472 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src),
473 "mov $dst, $src\t@ lor2hir", []>;
474 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src),
475 "mov $dst, $src\t@ hir2hir", []>;
476 } // neverHasSideEffects
479 let isCommutable = 1 in
480 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
481 "mul", " $dst, $rhs",
482 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
484 // move inverse register
485 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
486 "mvn", " $dst, $src",
487 [(set tGPR:$dst, (not tGPR:$src))]>;
489 // bitwise or register
490 let isCommutable = 1 in
491 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
492 "orr", " $dst, $rhs",
493 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
496 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
497 "rev", " $dst, $src",
498 [(set tGPR:$dst, (bswap tGPR:$src))]>,
499 Requires<[IsThumb1Only, HasV6]>;
501 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
502 "rev16", " $dst, $src",
504 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
505 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
506 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
507 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
508 Requires<[IsThumb1Only, HasV6]>;
510 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
511 "revsh", " $dst, $src",
514 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
515 (shl tGPR:$src, (i32 8))), i16))]>,
516 Requires<[IsThumb1Only, HasV6]>;
518 // rotate right register
519 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
520 "ror", " $dst, $rhs",
521 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
524 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
525 "rsb", " $dst, $src, #0",
526 [(set tGPR:$dst, (ineg tGPR:$src))]>;
528 // Subtract with carry register
530 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
531 "sbc", " $dst, $rhs",
532 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
534 // Subtract immediate
535 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
536 "sub", " $dst, $lhs, $rhs",
537 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
539 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
540 "sub", " $dst, $rhs",
541 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
544 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
545 "sub", " $dst, $lhs, $rhs",
546 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
548 // TODO: A7-96: STMIA - store multiple.
550 def tSUBspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
551 "sub $dst, $rhs * 4", []>;
554 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
555 "sxtb", " $dst, $src",
556 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
557 Requires<[IsThumb1Only, HasV6]>;
560 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
561 "sxth", " $dst, $src",
562 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
563 Requires<[IsThumb1Only, HasV6]>;
566 let isCommutable = 1, Defs = [CPSR] in
567 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
568 "tst", " $lhs, $rhs",
569 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
572 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
573 "uxtb", " $dst, $src",
574 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
575 Requires<[IsThumb1Only, HasV6]>;
578 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
579 "uxth", " $dst, $src",
580 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
581 Requires<[IsThumb1Only, HasV6]>;
584 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
585 // Expanded by the scheduler into a branch sequence.
586 // FIXME: Add actual movcc in IT blocks for Thumb2.
587 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
589 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
591 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
593 // tLEApcrel - Load a pc-relative address into a register without offending the
595 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label),
596 "adr $dst, #$label", []>;
598 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
599 "adr $dst, #${label}_${id:no_hash}", []>;
601 //===----------------------------------------------------------------------===//
605 // __aeabi_read_tp preserves the registers r1-r3.
608 def tTPsoft : TIx2<(outs), (ins),
609 "bl __aeabi_read_tp",
610 [(set R0, ARMthread_pointer)]>;
613 //===----------------------------------------------------------------------===//
614 // Non-Instruction Patterns
618 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
619 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
620 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
621 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
622 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
623 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
625 // Subtract with carry
626 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
627 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
628 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
629 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
630 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
631 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
633 // ConstantPool, GlobalAddress
634 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
635 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
638 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
639 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
642 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
643 Requires<[IsThumb, IsNotDarwin]>;
644 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
645 Requires<[IsThumb, IsDarwin]>;
647 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
648 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
649 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
650 Requires<[IsThumb, HasV5T, IsDarwin]>;
652 // Indirect calls to ARM routines
653 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
654 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
655 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
656 Requires<[IsThumb, HasV5T, IsDarwin]>;
658 // zextload i1 -> zextload i8
659 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
660 (tLDRB t_addrmode_s1:$addr)>;
662 // extload -> zextload
663 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
664 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
665 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
667 // If it's possible to use [r,r] address mode for sextload, select to
668 // ldr{b|h} + sxt{b|h} instead.
669 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
670 (tSXTB (tLDRB t_addrmode_s1:$addr))>;
671 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
672 (tSXTH (tLDRH t_addrmode_s2:$addr))>;
675 // Large immediate handling.
678 def : T1Pat<(i32 thumb_immshifted:$src),
679 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
680 (thumb_immshifted_shamt imm:$src))>;
682 def : T1Pat<(i32 imm0_255_comp:$src),
683 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;