1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_comp_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 def imm0_7_neg : PatLeaf<(i32 imm), [{
40 return (uint32_t)-N->getZExtValue() < 8;
43 def imm0_255_comp : PatLeaf<(i32 imm), [{
44 return ~((uint32_t)N->getZExtValue()) < 256;
47 def imm8_255 : ImmLeaf<i32, [{
48 return Imm >= 8 && Imm < 256;
50 def imm8_255_neg : PatLeaf<(i32 imm), [{
51 unsigned Val = -N->getZExtValue();
52 return Val >= 8 && Val < 256;
55 // Break imm's up into two pieces: an immediate + a left shift. This uses
56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
57 // to get the val/shift pieces.
58 def thumb_immshifted : PatLeaf<(imm), [{
59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
62 def thumb_immshifted_val : SDNodeXForm<imm, [{
63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
64 return CurDAG->getTargetConstant(V, MVT::i32);
67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
69 return CurDAG->getTargetConstant(V, MVT::i32);
72 // Scaled 4 immediate.
73 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
74 def t_imm0_1020s4 : Operand<i32> {
75 let PrintMethod = "printThumbS4ImmOperand";
76 let ParserMatchClass = t_imm0_1020s4_asmoperand;
77 let OperandType = "OPERAND_IMMEDIATE";
80 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
81 def t_imm0_508s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let ParserMatchClass = t_imm0_508s4_asmoperand;
84 let OperandType = "OPERAND_IMMEDIATE";
86 // Alias use only, so no printer is necessary.
87 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
88 def t_imm0_508s4_neg : Operand<i32> {
89 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
90 let OperandType = "OPERAND_IMMEDIATE";
93 // Define Thumb specific addressing modes.
95 // unsigned 8-bit, 2-scaled memory offset
96 class OperandUnsignedOffset_b8s2 : AsmOperandClass {
97 let Name = "UnsignedOffset_b8s2";
98 let PredicateMethod = "isUnsignedOffset<8, 2>";
101 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
103 let OperandType = "OPERAND_PCREL" in {
104 def t_brtarget : Operand<OtherVT> {
105 let EncoderMethod = "getThumbBRTargetOpValue";
106 let DecoderMethod = "DecodeThumbBROperand";
109 // ADR instruction labels.
110 def t_adrlabel : Operand<i32> {
111 let EncoderMethod = "getThumbAdrLabelOpValue";
112 let PrintMethod = "printAdrLabelOperand<2>";
113 let ParserMatchClass = UnsignedOffset_b8s2;
116 def t_bcctarget : Operand<i32> {
117 let EncoderMethod = "getThumbBCCTargetOpValue";
118 let DecoderMethod = "DecodeThumbBCCTargetOperand";
121 def t_cbtarget : Operand<i32> {
122 let EncoderMethod = "getThumbCBTargetOpValue";
123 let DecoderMethod = "DecodeThumbCmpBROperand";
126 def t_bltarget : Operand<i32> {
127 let EncoderMethod = "getThumbBLTargetOpValue";
128 let DecoderMethod = "DecodeThumbBLTargetOperand";
131 def t_blxtarget : Operand<i32> {
132 let EncoderMethod = "getThumbBLXTargetOpValue";
133 let DecoderMethod = "DecodeThumbBLXOffset";
137 // t_addrmode_rr := reg + reg
139 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
140 def t_addrmode_rr : Operand<i32>,
141 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
142 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
143 let PrintMethod = "printThumbAddrModeRROperand";
144 let DecoderMethod = "DecodeThumbAddrModeRR";
145 let ParserMatchClass = t_addrmode_rr_asm_operand;
146 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
149 // t_addrmode_rrs := reg + reg
151 // We use separate scaled versions because the Select* functions need
152 // to explicitly check for a matching constant and return false here so that
153 // the reg+imm forms will match instead. This is a horrible way to do that,
154 // as it forces tight coupling between the methods, but it's how selectiondag
156 def t_addrmode_rrs1 : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
158 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
159 let PrintMethod = "printThumbAddrModeRROperand";
160 let DecoderMethod = "DecodeThumbAddrModeRR";
161 let ParserMatchClass = t_addrmode_rr_asm_operand;
162 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
164 def t_addrmode_rrs2 : Operand<i32>,
165 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
166 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
167 let DecoderMethod = "DecodeThumbAddrModeRR";
168 let PrintMethod = "printThumbAddrModeRROperand";
169 let ParserMatchClass = t_addrmode_rr_asm_operand;
170 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
172 def t_addrmode_rrs4 : Operand<i32>,
173 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
174 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
175 let DecoderMethod = "DecodeThumbAddrModeRR";
176 let PrintMethod = "printThumbAddrModeRROperand";
177 let ParserMatchClass = t_addrmode_rr_asm_operand;
178 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
181 // t_addrmode_is4 := reg + imm5 * 4
183 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
184 def t_addrmode_is4 : Operand<i32>,
185 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
186 let EncoderMethod = "getAddrModeISOpValue";
187 let DecoderMethod = "DecodeThumbAddrModeIS";
188 let PrintMethod = "printThumbAddrModeImm5S4Operand";
189 let ParserMatchClass = t_addrmode_is4_asm_operand;
190 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
193 // t_addrmode_is2 := reg + imm5 * 2
195 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
196 def t_addrmode_is2 : Operand<i32>,
197 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
198 let EncoderMethod = "getAddrModeISOpValue";
199 let DecoderMethod = "DecodeThumbAddrModeIS";
200 let PrintMethod = "printThumbAddrModeImm5S2Operand";
201 let ParserMatchClass = t_addrmode_is2_asm_operand;
202 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
205 // t_addrmode_is1 := reg + imm5
207 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
208 def t_addrmode_is1 : Operand<i32>,
209 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
210 let EncoderMethod = "getAddrModeISOpValue";
211 let DecoderMethod = "DecodeThumbAddrModeIS";
212 let PrintMethod = "printThumbAddrModeImm5S1Operand";
213 let ParserMatchClass = t_addrmode_is1_asm_operand;
214 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
217 // t_addrmode_sp := sp + imm8 * 4
219 // FIXME: This really shouldn't have an explicit SP operand at all. It should
220 // be implicit, just like in the instruction encoding itself.
221 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
222 def t_addrmode_sp : Operand<i32>,
223 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
224 let EncoderMethod = "getAddrModeThumbSPOpValue";
225 let DecoderMethod = "DecodeThumbAddrModeSP";
226 let PrintMethod = "printThumbAddrModeSPOperand";
227 let ParserMatchClass = t_addrmode_sp_asm_operand;
228 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
231 // t_addrmode_pc := <label> => pc + imm8 * 4
233 def t_addrmode_pc : Operand<i32> {
234 let EncoderMethod = "getAddrModePCOpValue";
235 let DecoderMethod = "DecodeThumbAddrModePC";
236 let PrintMethod = "printThumbLdrLabelOperand";
239 //===----------------------------------------------------------------------===//
240 // Miscellaneous Instructions.
243 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
244 // from removing one half of the matched pairs. That breaks PEI, which assumes
245 // these will always be in pairs, and asserts if it finds otherwise. Better way?
246 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
247 def tADJCALLSTACKUP :
248 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
249 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
250 Requires<[IsThumb, IsThumb1Only]>;
252 def tADJCALLSTACKDOWN :
253 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
254 [(ARMcallseq_start imm:$amt)]>,
255 Requires<[IsThumb, IsThumb1Only]>;
258 class T1SystemEncoding<bits<8> opc>
259 : T1Encoding<0b101111> {
260 let Inst{9-8} = 0b11;
264 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
265 T1SystemEncoding<0x00>, // A8.6.110
266 Requires<[IsThumb2]>;
268 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
269 T1SystemEncoding<0x10>, // A8.6.410
270 Requires<[IsThumb2]>;
272 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
273 T1SystemEncoding<0x20>, // A8.6.408
274 Requires<[IsThumb2]>;
276 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
277 T1SystemEncoding<0x30>, // A8.6.409
278 Requires<[IsThumb2]>;
280 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
281 T1SystemEncoding<0x40>, // A8.6.157
282 Requires<[IsThumb2]>;
284 // The imm operand $val can be used by a debugger to store more information
285 // about the breakpoint.
286 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
288 T1Encoding<0b101111> {
289 let Inst{9-8} = 0b10;
295 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
296 []>, T1Encoding<0b101101> {
299 let Inst{9-5} = 0b10010;
302 let Inst{2-0} = 0b000;
305 // Change Processor State is a system instruction -- for disassembly only.
306 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
307 NoItinerary, "cps$imod $iflags", []>,
315 let Inst{2-0} = iflags;
316 let DecoderMethod = "DecodeThumbCPS";
319 // For both thumb1 and thumb2.
320 let isNotDuplicable = 1, isCodeGenOnly = 1 in
321 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
322 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
323 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
326 let Inst{6-3} = 0b1111; // Rm = pc
330 // ADD <Rd>, sp, #<imm8>
331 // FIXME: This should not be marked as having side effects, and it should be
332 // rematerializable. Clearing the side effect bit causes miscompilations,
333 // probably because the instruction can be moved around.
334 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
335 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
336 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
340 let Inst{10-8} = dst;
342 let DecoderMethod = "DecodeThumbAddSpecialReg";
345 // ADD sp, sp, #<imm7>
346 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
347 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
348 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
352 let DecoderMethod = "DecodeThumbAddSPImm";
355 // SUB sp, sp, #<imm7>
356 // FIXME: The encoding and the ASM string don't match up.
357 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
358 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
359 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
363 let DecoderMethod = "DecodeThumbAddSPImm";
366 def : tInstAlias<"add${p} sp, $imm",
367 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
368 def : tInstAlias<"add${p} sp, sp, $imm",
369 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
371 // Can optionally specify SP as a three operand instruction.
372 def : tInstAlias<"add${p} sp, sp, $imm",
373 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
374 def : tInstAlias<"sub${p} sp, sp, $imm",
375 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
378 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
379 "add", "\t$Rdn, $sp, $Rn", []>,
380 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
381 // A8.6.9 Encoding T1
383 let Inst{7} = Rdn{3};
384 let Inst{6-3} = 0b1101;
385 let Inst{2-0} = Rdn{2-0};
386 let DecoderMethod = "DecodeThumbAddSPReg";
390 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
391 "add", "\t$Rdn, $Rm", []>,
392 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
393 // A8.6.9 Encoding T2
397 let Inst{2-0} = 0b101;
398 let DecoderMethod = "DecodeThumbAddSPReg";
401 //===----------------------------------------------------------------------===//
402 // Control Flow Instructions.
406 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
407 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
408 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
412 let Inst{2-0} = 0b000;
413 let Unpredictable{2-0} = 0b111;
417 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
418 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
419 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
421 // Alternative return instruction used by vararg functions.
422 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
424 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
427 // All calls clobber the non-callee saved registers. SP is marked as a use to
428 // prevent stack-pointer assignments that appear immediately before calls from
429 // potentially appearing dead.
431 Defs = [LR], Uses = [SP] in {
432 // Also used for Thumb2
433 def tBL : TIx2<0b11110, 0b11, 1,
434 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
436 [(ARMtcall tglobaladdr:$func)]>,
437 Requires<[IsThumb]>, Sched<[WriteBrL]> {
439 let Inst{26} = func{23};
440 let Inst{25-16} = func{20-11};
441 let Inst{13} = func{22};
442 let Inst{11} = func{21};
443 let Inst{10-0} = func{10-0};
446 // ARMv5T and above, also used for Thumb2
447 def tBLXi : TIx2<0b11110, 0b11, 0,
448 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
450 [(ARMcall tglobaladdr:$func)]>,
451 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> {
453 let Inst{26} = func{23};
454 let Inst{25-16} = func{20-11};
455 let Inst{13} = func{22};
456 let Inst{11} = func{21};
457 let Inst{10-1} = func{10-1};
458 let Inst{0} = 0; // func{0} is assumed zero
461 // Also used for Thumb2
462 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
464 [(ARMtcall GPR:$func)]>,
465 Requires<[IsThumb, HasV5T]>,
466 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
468 let Inst{6-3} = func;
469 let Inst{2-0} = 0b000;
473 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
475 [(ARMcall_nolink tGPR:$func)]>,
476 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
479 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
480 let isPredicable = 1 in
481 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
482 "b", "\t$target", [(br bb:$target)]>,
483 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
485 let Inst{10-0} = target;
489 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
490 // the clobber of LR.
492 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
493 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
496 def tBR_JTr : tPseudoInst<(outs),
497 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
499 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
500 Sched<[WriteBrTbl]> {
501 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
505 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
506 // a two-value operand where a dag node expects two operands. :(
507 let isBranch = 1, isTerminator = 1 in
508 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
510 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
511 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
515 let Inst{7-0} = target;
520 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
523 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
525 (tBX GPR:$dst, (ops 14, zero_reg))>,
526 Requires<[IsThumb]>, Sched<[WriteBr]>;
528 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
529 // on IOS), so it's in ARMInstrThumb2.td.
532 def tTAILJMPdND : tPseudoExpand<(outs),
533 (ins t_brtarget:$dst, pred:$p),
535 (tB t_brtarget:$dst, pred:$p)>,
536 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>;
541 // A8.6.218 Supervisor Call (Software Interrupt)
542 // A8.6.16 B: Encoding T1
543 // If Inst{11-8} == 0b1111 then SEE SVC
544 let isCall = 1, Uses = [SP] in
545 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
546 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
548 let Inst{15-12} = 0b1101;
549 let Inst{11-8} = 0b1111;
553 // The assembler uses 0xDEFE for a trap instruction.
554 let isBarrier = 1, isTerminator = 1 in
555 def tTRAP : TI<(outs), (ins), IIC_Br,
556 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
560 //===----------------------------------------------------------------------===//
561 // Load Store Instructions.
564 // Loads: reg/reg and reg/imm5
565 let canFoldAsLoad = 1, isReMaterializable = 1 in
566 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
567 Operand AddrMode_r, Operand AddrMode_i,
568 AddrMode am, InstrItinClass itin_r,
569 InstrItinClass itin_i, string asm,
572 T1pILdStEncode<reg_opc,
573 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
574 am, itin_r, asm, "\t$Rt, $addr",
575 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
577 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
578 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
579 am, itin_i, asm, "\t$Rt, $addr",
580 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
582 // Stores: reg/reg and reg/imm5
583 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
584 Operand AddrMode_r, Operand AddrMode_i,
585 AddrMode am, InstrItinClass itin_r,
586 InstrItinClass itin_i, string asm,
589 T1pILdStEncode<reg_opc,
590 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
591 am, itin_r, asm, "\t$Rt, $addr",
592 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
594 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
595 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
596 am, itin_i, asm, "\t$Rt, $addr",
597 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
601 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
602 t_addrmode_is4, AddrModeT1_4,
603 IIC_iLoad_r, IIC_iLoad_i, "ldr",
604 UnOpFrag<(load node:$Src)>>;
607 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
608 t_addrmode_is1, AddrModeT1_1,
609 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
610 UnOpFrag<(zextloadi8 node:$Src)>>;
613 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
614 t_addrmode_is2, AddrModeT1_2,
615 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
616 UnOpFrag<(zextloadi16 node:$Src)>>;
618 let AddedComplexity = 10 in
619 def tLDRSB : // A8.6.80
620 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
621 AddrModeT1_1, IIC_iLoad_bh_r,
622 "ldrsb", "\t$Rt, $addr",
623 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
625 let AddedComplexity = 10 in
626 def tLDRSH : // A8.6.84
627 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
628 AddrModeT1_2, IIC_iLoad_bh_r,
629 "ldrsh", "\t$Rt, $addr",
630 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
632 let canFoldAsLoad = 1 in
633 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
634 "ldr", "\t$Rt, $addr",
635 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
640 let Inst{7-0} = addr;
644 // FIXME: Use ldr.n to work around a darwin assembler bug.
645 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
646 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
647 "ldr", ".n\t$Rt, $addr",
648 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
649 T1Encoding<{0,1,0,0,1,?}> {
654 let Inst{7-0} = addr;
657 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
658 // For assembly/disassembly use only.
659 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
660 "ldr", "\t$Rt, $addr", []>,
661 T1Encoding<{0,1,0,0,1,?}> {
666 let Inst{7-0} = addr;
669 // A8.6.194 & A8.6.192
670 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
671 t_addrmode_is4, AddrModeT1_4,
672 IIC_iStore_r, IIC_iStore_i, "str",
673 BinOpFrag<(store node:$LHS, node:$RHS)>>;
675 // A8.6.197 & A8.6.195
676 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
677 t_addrmode_is1, AddrModeT1_1,
678 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
679 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
681 // A8.6.207 & A8.6.205
682 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
683 t_addrmode_is2, AddrModeT1_2,
684 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
685 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
688 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
689 "str", "\t$Rt, $addr",
690 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
695 let Inst{7-0} = addr;
698 //===----------------------------------------------------------------------===//
699 // Load / store multiple Instructions.
702 // These require base address to be written back or one of the loaded regs.
703 let neverHasSideEffects = 1 in {
705 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
706 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
707 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
711 let Inst{7-0} = regs;
714 // Writeback version is just a pseudo, as there's no encoding difference.
715 // Writeback happens iff the base register is not in the destination register
718 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
719 "$Rn = $wb", IIC_iLoad_mu>,
720 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
722 let OutOperandList = (outs GPR:$wb);
723 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
725 let isCodeGenOnly = 1;
727 list<Predicate> Predicates = [IsThumb];
730 // There is no non-writeback version of STM for Thumb.
731 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
732 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
733 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
734 AddrModeNone, 2, IIC_iStore_mu,
735 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
736 T1Encoding<{1,1,0,0,0,?}> {
740 let Inst{7-0} = regs;
743 } // neverHasSideEffects
745 def : InstAlias<"ldm${p} $Rn!, $regs",
746 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
747 Requires<[IsThumb, IsThumb1Only]>;
749 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
750 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
752 "pop${p}\t$regs", []>,
753 T1Misc<{1,1,0,?,?,?,?}> {
755 let Inst{8} = regs{15};
756 let Inst{7-0} = regs{7-0};
759 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
760 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
762 "push${p}\t$regs", []>,
763 T1Misc<{0,1,0,?,?,?,?}> {
765 let Inst{8} = regs{14};
766 let Inst{7-0} = regs{7-0};
769 //===----------------------------------------------------------------------===//
770 // Arithmetic Instructions.
773 // Helper classes for encoding T1pI patterns:
774 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
775 string opc, string asm, list<dag> pattern>
776 : T1pI<oops, iops, itin, opc, asm, pattern>,
777 T1DataProcessing<opA> {
783 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
784 string opc, string asm, list<dag> pattern>
785 : T1pI<oops, iops, itin, opc, asm, pattern>,
793 // Helper classes for encoding T1sI patterns:
794 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
795 string opc, string asm, list<dag> pattern>
796 : T1sI<oops, iops, itin, opc, asm, pattern>,
797 T1DataProcessing<opA> {
803 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
804 string opc, string asm, list<dag> pattern>
805 : T1sI<oops, iops, itin, opc, asm, pattern>,
814 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
815 string opc, string asm, list<dag> pattern>
816 : T1sI<oops, iops, itin, opc, asm, pattern>,
824 // Helper classes for encoding T1sIt patterns:
825 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
826 string opc, string asm, list<dag> pattern>
827 : T1sIt<oops, iops, itin, opc, asm, pattern>,
828 T1DataProcessing<opA> {
834 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
835 string opc, string asm, list<dag> pattern>
836 : T1sIt<oops, iops, itin, opc, asm, pattern>,
840 let Inst{10-8} = Rdn;
841 let Inst{7-0} = imm8;
844 // Add with carry register
845 let isCommutable = 1, Uses = [CPSR] in
847 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
848 "adc", "\t$Rdn, $Rm",
849 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
852 def tADDi3 : // A8.6.4 T1
853 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
855 "add", "\t$Rd, $Rm, $imm3",
856 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
859 let Inst{8-6} = imm3;
862 def tADDi8 : // A8.6.4 T2
863 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
864 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
865 "add", "\t$Rdn, $imm8",
866 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
870 let isCommutable = 1 in
871 def tADDrr : // A8.6.6 T1
872 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
874 "add", "\t$Rd, $Rn, $Rm",
875 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
877 let neverHasSideEffects = 1 in
878 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
879 "add", "\t$Rdn, $Rm", []>,
880 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
884 let Inst{7} = Rdn{3};
886 let Inst{2-0} = Rdn{2-0};
890 let isCommutable = 1 in
891 def tAND : // A8.6.12
892 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
894 "and", "\t$Rdn, $Rm",
895 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
898 def tASRri : // A8.6.14
899 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
901 "asr", "\t$Rd, $Rm, $imm5",
902 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
905 let Inst{10-6} = imm5;
909 def tASRrr : // A8.6.15
910 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
912 "asr", "\t$Rdn, $Rm",
913 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
916 def tBIC : // A8.6.20
917 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
919 "bic", "\t$Rdn, $Rm",
920 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
924 let isCompare = 1, Defs = [CPSR] in {
925 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
926 // Compare-to-zero still works out, just not the relationals
927 //def tCMN : // A8.6.33
928 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
930 // "cmn", "\t$lhs, $rhs",
931 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
933 def tCMNz : // A8.6.33
934 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
937 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
939 } // isCompare = 1, Defs = [CPSR]
942 let isCompare = 1, Defs = [CPSR] in {
943 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
944 "cmp", "\t$Rn, $imm8",
945 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
946 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
951 let Inst{7-0} = imm8;
955 def tCMPr : // A8.6.36 T1
956 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
959 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
961 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
962 "cmp", "\t$Rn, $Rm", []>,
963 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
969 let Inst{2-0} = Rn{2-0};
971 } // isCompare = 1, Defs = [CPSR]
975 let isCommutable = 1 in
976 def tEOR : // A8.6.45
977 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
979 "eor", "\t$Rdn, $Rm",
980 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
983 def tLSLri : // A8.6.88
984 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
986 "lsl", "\t$Rd, $Rm, $imm5",
987 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
990 let Inst{10-6} = imm5;
994 def tLSLrr : // A8.6.89
995 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
997 "lsl", "\t$Rdn, $Rm",
998 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1001 def tLSRri : // A8.6.90
1002 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1004 "lsr", "\t$Rd, $Rm, $imm5",
1005 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1008 let Inst{10-6} = imm5;
1012 def tLSRrr : // A8.6.91
1013 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1015 "lsr", "\t$Rdn, $Rm",
1016 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1019 let isMoveImm = 1 in
1020 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1021 "mov", "\t$Rd, $imm8",
1022 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1023 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1027 let Inst{10-8} = Rd;
1028 let Inst{7-0} = imm8;
1030 // Because we have an explicit tMOVSr below, we need an alias to handle
1031 // the immediate "movs" form here. Blech.
1032 def : tInstAlias <"movs $Rdn, $imm",
1033 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1035 // A7-73: MOV(2) - mov setting flag.
1037 let neverHasSideEffects = 1 in {
1038 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1040 "mov", "\t$Rd, $Rm", "", []>,
1041 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1045 let Inst{7} = Rd{3};
1047 let Inst{2-0} = Rd{2-0};
1049 let Defs = [CPSR] in
1050 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1051 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1055 let Inst{15-6} = 0b0000000000;
1059 } // neverHasSideEffects
1061 // Multiply register
1062 let isCommutable = 1 in
1063 def tMUL : // A8.6.105 T1
1064 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1065 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1066 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1067 T1DataProcessing<0b1101> {
1072 let AsmMatchConverter = "cvtThumbMultiply";
1075 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1078 // Move inverse register
1079 def tMVN : // A8.6.107
1080 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1081 "mvn", "\t$Rd, $Rn",
1082 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1084 // Bitwise or register
1085 let isCommutable = 1 in
1086 def tORR : // A8.6.114
1087 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1089 "orr", "\t$Rdn, $Rm",
1090 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1093 def tREV : // A8.6.134
1094 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1096 "rev", "\t$Rd, $Rm",
1097 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1098 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1100 def tREV16 : // A8.6.135
1101 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1103 "rev16", "\t$Rd, $Rm",
1104 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1105 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1107 def tREVSH : // A8.6.136
1108 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1110 "revsh", "\t$Rd, $Rm",
1111 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1112 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1114 // Rotate right register
1115 def tROR : // A8.6.139
1116 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1118 "ror", "\t$Rdn, $Rm",
1119 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1123 def tRSB : // A8.6.141
1124 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1126 "rsb", "\t$Rd, $Rn, #0",
1127 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1129 // Subtract with carry register
1130 let Uses = [CPSR] in
1131 def tSBC : // A8.6.151
1132 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1134 "sbc", "\t$Rdn, $Rm",
1135 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
1138 // Subtract immediate
1139 def tSUBi3 : // A8.6.210 T1
1140 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1142 "sub", "\t$Rd, $Rm, $imm3",
1143 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1146 let Inst{8-6} = imm3;
1149 def tSUBi8 : // A8.6.210 T2
1150 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1151 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1152 "sub", "\t$Rdn, $imm8",
1153 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1156 // Subtract register
1157 def tSUBrr : // A8.6.212
1158 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1160 "sub", "\t$Rd, $Rn, $Rm",
1161 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1165 def tSXTB : // A8.6.222
1166 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1168 "sxtb", "\t$Rd, $Rm",
1169 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1170 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1173 // Sign-extend short
1174 def tSXTH : // A8.6.224
1175 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1177 "sxth", "\t$Rd, $Rm",
1178 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1179 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1183 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1184 def tTST : // A8.6.230
1185 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1186 "tst", "\t$Rn, $Rm",
1187 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1191 def tUXTB : // A8.6.262
1192 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1194 "uxtb", "\t$Rd, $Rm",
1195 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1196 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1199 // Zero-extend short
1200 def tUXTH : // A8.6.264
1201 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1203 "uxth", "\t$Rd, $Rm",
1204 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1205 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1207 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1208 // Expanded after instruction selection into a branch sequence.
1209 let usesCustomInserter = 1 in // Expanded after instruction selection.
1210 def tMOVCCr_pseudo :
1211 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1213 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1215 // tLEApcrel - Load a pc-relative address into a register without offending the
1218 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1219 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1220 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1223 let Inst{10-8} = Rd;
1224 let Inst{7-0} = addr;
1225 let DecoderMethod = "DecodeThumbAddSpecialReg";
1228 let neverHasSideEffects = 1, isReMaterializable = 1 in
1229 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1230 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1232 let hasSideEffects = 1 in
1233 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1234 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1235 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1237 //===----------------------------------------------------------------------===//
1241 // __aeabi_read_tp preserves the registers r1-r3.
1242 // This is a pseudo inst so that we can get the encoding right,
1243 // complete with fixup for the aeabi_read_tp function.
1244 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1245 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1246 [(set R0, ARMthread_pointer)]>,
1249 //===----------------------------------------------------------------------===//
1250 // SJLJ Exception handling intrinsics
1253 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1254 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1255 // from some other function to get here, and we're using the stack frame for the
1256 // containing function to save/restore registers, we can't keep anything live in
1257 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1258 // tromped upon when we get here from a longjmp(). We force everything out of
1259 // registers except for our own input by listing the relevant registers in
1260 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1261 // preserve all of the callee-saved resgisters, which is exactly what we want.
1262 // $val is a scratch register for our use.
1263 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1264 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1265 usesCustomInserter = 1 in
1266 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1267 AddrModeNone, 0, NoItinerary, "","",
1268 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1270 // FIXME: Non-IOS version(s)
1271 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1272 Defs = [ R7, LR, SP ] in
1273 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1274 AddrModeNone, 0, IndexModeNone,
1275 Pseudo, NoItinerary, "", "",
1276 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1277 Requires<[IsThumb, IsIOS]>;
1279 //===----------------------------------------------------------------------===//
1280 // Non-Instruction Patterns
1284 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1285 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1286 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1287 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1290 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1291 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1292 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1293 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1294 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1295 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1297 // Subtract with carry
1298 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1299 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1300 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1301 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1302 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1303 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1305 // ConstantPool, GlobalAddress
1306 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1307 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1310 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1311 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1314 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1315 Requires<[IsThumb]>;
1317 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1318 Requires<[IsThumb, HasV5T]>;
1320 // Indirect calls to ARM routines
1321 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1322 Requires<[IsThumb, HasV5T]>;
1324 // zextload i1 -> zextload i8
1325 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1326 (tLDRBr t_addrmode_rrs1:$addr)>;
1327 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1328 (tLDRBi t_addrmode_is1:$addr)>;
1330 // extload -> zextload
1331 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1332 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1333 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1334 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1335 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1336 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1338 // If it's impossible to use [r,r] address mode for sextload, select to
1339 // ldr{b|h} + sxt{b|h} instead.
1340 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1341 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1342 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1343 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1344 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1345 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1346 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1347 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1348 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1349 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1350 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1351 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1353 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1354 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1355 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1356 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1357 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1358 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1359 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1360 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1362 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1363 (tLDRBi t_addrmode_is1:$src)>;
1364 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1365 (tLDRBr t_addrmode_rrs1:$src)>;
1366 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1367 (tLDRHi t_addrmode_is2:$src)>;
1368 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1369 (tLDRHr t_addrmode_rrs2:$src)>;
1370 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1371 (tLDRi t_addrmode_is4:$src)>;
1372 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1373 (tLDRr t_addrmode_rrs4:$src)>;
1374 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1375 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1376 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1377 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1378 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1379 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1380 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1381 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1382 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1383 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1384 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1385 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1387 // Large immediate handling.
1390 def : T1Pat<(i32 thumb_immshifted:$src),
1391 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1392 (thumb_immshifted_shamt imm:$src))>;
1394 def : T1Pat<(i32 imm0_255_comp:$src),
1395 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1397 // Pseudo instruction that combines ldr from constpool and add pc. This should
1398 // be expanded into two instructions late to allow if-conversion and
1400 let isReMaterializable = 1 in
1401 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1403 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1405 Requires<[IsThumb, IsThumb1Only]>;
1407 // Pseudo-instruction for merged POP and return.
1408 // FIXME: remove when we have a way to marking a MI with these properties.
1409 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1410 hasExtraDefRegAllocReq = 1 in
1411 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1413 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1415 // Indirect branch using "mov pc, $Rm"
1416 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1417 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1418 2, IIC_Br, [(brind GPR:$Rm)],
1419 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1423 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1424 // encoding is available on ARMv6K, but we don't differentiate that finely.
1425 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1428 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1429 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1430 // a useful extension and assembles to defined behaviour (the insn does
1432 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1433 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1435 // "neg" is and alias for "rsb rd, rn, #0"
1436 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1437 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1440 // Implied destination operand forms for shifts.
1441 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1442 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1443 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1444 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1445 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1446 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;