1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), SDLoc(N), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_comp_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), SDLoc(N),
40 def imm0_7_neg : PatLeaf<(i32 imm), [{
41 return (uint32_t)-N->getZExtValue() < 8;
44 def imm0_255_comp : PatLeaf<(i32 imm), [{
45 return ~((uint32_t)N->getZExtValue()) < 256;
48 def imm8_255 : ImmLeaf<i32, [{
49 return Imm >= 8 && Imm < 256;
51 def imm8_255_neg : PatLeaf<(i32 imm), [{
52 unsigned Val = -N->getZExtValue();
53 return Val >= 8 && Val < 256;
56 // Break imm's up into two pieces: an immediate + a left shift. This uses
57 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
58 // to get the val/shift pieces.
59 def thumb_immshifted : PatLeaf<(imm), [{
60 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
63 def thumb_immshifted_val : SDNodeXForm<imm, [{
64 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
65 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
68 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
69 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
70 return CurDAG->getTargetConstant(V, SDLoc(N), MVT::i32);
73 // Scaled 4 immediate.
74 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
75 def t_imm0_1020s4 : Operand<i32> {
76 let PrintMethod = "printThumbS4ImmOperand";
77 let ParserMatchClass = t_imm0_1020s4_asmoperand;
78 let OperandType = "OPERAND_IMMEDIATE";
81 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
82 def t_imm0_508s4 : Operand<i32> {
83 let PrintMethod = "printThumbS4ImmOperand";
84 let ParserMatchClass = t_imm0_508s4_asmoperand;
85 let OperandType = "OPERAND_IMMEDIATE";
87 // Alias use only, so no printer is necessary.
88 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
89 def t_imm0_508s4_neg : Operand<i32> {
90 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
91 let OperandType = "OPERAND_IMMEDIATE";
94 // Define Thumb specific addressing modes.
96 // unsigned 8-bit, 2-scaled memory offset
97 class OperandUnsignedOffset_b8s2 : AsmOperandClass {
98 let Name = "UnsignedOffset_b8s2";
99 let PredicateMethod = "isUnsignedOffset<8, 2>";
102 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
104 // thumb style PC relative operand. signed, 8 bits magnitude,
105 // two bits shift. can be represented as either [pc, #imm], #imm,
106 // or relocatable expression...
107 def ThumbMemPC : AsmOperandClass {
108 let Name = "ThumbMemPC";
111 let OperandType = "OPERAND_PCREL" in {
112 def t_brtarget : Operand<OtherVT> {
113 let EncoderMethod = "getThumbBRTargetOpValue";
114 let DecoderMethod = "DecodeThumbBROperand";
117 // ADR instruction labels.
118 def t_adrlabel : Operand<i32> {
119 let EncoderMethod = "getThumbAdrLabelOpValue";
120 let PrintMethod = "printAdrLabelOperand<2>";
121 let ParserMatchClass = UnsignedOffset_b8s2;
124 def t_bcctarget : Operand<i32> {
125 let EncoderMethod = "getThumbBCCTargetOpValue";
126 let DecoderMethod = "DecodeThumbBCCTargetOperand";
129 def t_cbtarget : Operand<i32> {
130 let EncoderMethod = "getThumbCBTargetOpValue";
131 let DecoderMethod = "DecodeThumbCmpBROperand";
134 def t_bltarget : Operand<i32> {
135 let EncoderMethod = "getThumbBLTargetOpValue";
136 let DecoderMethod = "DecodeThumbBLTargetOperand";
139 def t_blxtarget : Operand<i32> {
140 let EncoderMethod = "getThumbBLXTargetOpValue";
141 let DecoderMethod = "DecodeThumbBLXOffset";
144 // t_addrmode_pc := <label> => pc + imm8 * 4
146 def t_addrmode_pc : MemOperand {
147 let EncoderMethod = "getAddrModePCOpValue";
148 let DecoderMethod = "DecodeThumbAddrModePC";
149 let PrintMethod = "printThumbLdrLabelOperand";
150 let ParserMatchClass = ThumbMemPC;
154 // t_addrmode_rr := reg + reg
156 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
157 def t_addrmode_rr : MemOperand,
158 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
159 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
160 let PrintMethod = "printThumbAddrModeRROperand";
161 let DecoderMethod = "DecodeThumbAddrModeRR";
162 let ParserMatchClass = t_addrmode_rr_asm_operand;
163 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
166 // t_addrmode_rrs := reg + reg
168 // We use separate scaled versions because the Select* functions need
169 // to explicitly check for a matching constant and return false here so that
170 // the reg+imm forms will match instead. This is a horrible way to do that,
171 // as it forces tight coupling between the methods, but it's how selectiondag
173 def t_addrmode_rrs1 : MemOperand,
174 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
175 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
176 let PrintMethod = "printThumbAddrModeRROperand";
177 let DecoderMethod = "DecodeThumbAddrModeRR";
178 let ParserMatchClass = t_addrmode_rr_asm_operand;
179 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
181 def t_addrmode_rrs2 : MemOperand,
182 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
183 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
184 let DecoderMethod = "DecodeThumbAddrModeRR";
185 let PrintMethod = "printThumbAddrModeRROperand";
186 let ParserMatchClass = t_addrmode_rr_asm_operand;
187 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
189 def t_addrmode_rrs4 : MemOperand,
190 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
191 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
192 let DecoderMethod = "DecodeThumbAddrModeRR";
193 let PrintMethod = "printThumbAddrModeRROperand";
194 let ParserMatchClass = t_addrmode_rr_asm_operand;
195 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
198 // t_addrmode_is4 := reg + imm5 * 4
200 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
201 def t_addrmode_is4 : MemOperand,
202 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
203 let EncoderMethod = "getAddrModeISOpValue";
204 let DecoderMethod = "DecodeThumbAddrModeIS";
205 let PrintMethod = "printThumbAddrModeImm5S4Operand";
206 let ParserMatchClass = t_addrmode_is4_asm_operand;
207 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
210 // t_addrmode_is2 := reg + imm5 * 2
212 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
213 def t_addrmode_is2 : MemOperand,
214 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
215 let EncoderMethod = "getAddrModeISOpValue";
216 let DecoderMethod = "DecodeThumbAddrModeIS";
217 let PrintMethod = "printThumbAddrModeImm5S2Operand";
218 let ParserMatchClass = t_addrmode_is2_asm_operand;
219 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
222 // t_addrmode_is1 := reg + imm5
224 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
225 def t_addrmode_is1 : MemOperand,
226 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
227 let EncoderMethod = "getAddrModeISOpValue";
228 let DecoderMethod = "DecodeThumbAddrModeIS";
229 let PrintMethod = "printThumbAddrModeImm5S1Operand";
230 let ParserMatchClass = t_addrmode_is1_asm_operand;
231 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
234 // t_addrmode_sp := sp + imm8 * 4
236 // FIXME: This really shouldn't have an explicit SP operand at all. It should
237 // be implicit, just like in the instruction encoding itself.
238 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
239 def t_addrmode_sp : MemOperand,
240 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
241 let EncoderMethod = "getAddrModeThumbSPOpValue";
242 let DecoderMethod = "DecodeThumbAddrModeSP";
243 let PrintMethod = "printThumbAddrModeSPOperand";
244 let ParserMatchClass = t_addrmode_sp_asm_operand;
245 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
248 //===----------------------------------------------------------------------===//
249 // Miscellaneous Instructions.
252 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
253 // from removing one half of the matched pairs. That breaks PEI, which assumes
254 // these will always be in pairs, and asserts if it finds otherwise. Better way?
255 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
256 def tADJCALLSTACKUP :
257 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
258 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
259 Requires<[IsThumb, IsThumb1Only]>;
261 def tADJCALLSTACKDOWN :
262 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
263 [(ARMcallseq_start imm:$amt)]>,
264 Requires<[IsThumb, IsThumb1Only]>;
267 class T1SystemEncoding<bits<8> opc>
268 : T1Encoding<0b101111> {
269 let Inst{9-8} = 0b11;
273 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
274 [(int_arm_hint imm0_15:$imm)]>,
275 T1SystemEncoding<0x00>,
276 Requires<[IsThumb, HasV6M]> {
281 class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> {
282 let Predicates = [IsThumb, HasV6M];
285 def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110
286 def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410
287 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408
288 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409
289 def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
290 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
291 let Predicates = [IsThumb2, HasV8];
294 // The imm operand $val can be used by a debugger to store more information
295 // about the breakpoint.
296 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
298 T1Encoding<0b101111> {
299 let Inst{9-8} = 0b10;
304 // default immediate for breakpoint mnemonic
305 def : InstAlias<"bkpt", (tBKPT 0)>, Requires<[IsThumb]>;
307 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
308 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
309 let Inst{9-6} = 0b1010;
314 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
315 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> {
318 let Inst{9-5} = 0b10010;
321 let Inst{2-0} = 0b000;
324 // Change Processor State is a system instruction -- for disassembly only.
325 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
326 NoItinerary, "cps$imod $iflags", []>,
334 let Inst{2-0} = iflags;
335 let DecoderMethod = "DecodeThumbCPS";
338 // For both thumb1 and thumb2.
339 let isNotDuplicable = 1, isCodeGenOnly = 1 in
340 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
341 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
342 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
345 let Inst{6-3} = 0b1111; // Rm = pc
349 // ADD <Rd>, sp, #<imm8>
350 // FIXME: This should not be marked as having side effects, and it should be
351 // rematerializable. Clearing the side effect bit causes miscompilations,
352 // probably because the instruction can be moved around.
353 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
354 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
355 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
359 let Inst{10-8} = dst;
361 let DecoderMethod = "DecodeThumbAddSpecialReg";
364 // Thumb1 frame lowering is rather fragile, we hope to be able to use
365 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
366 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),
368 Requires<[IsThumb, IsThumb1Only]> {
372 // ADD sp, sp, #<imm7>
373 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
374 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
375 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
379 let DecoderMethod = "DecodeThumbAddSPImm";
382 // SUB sp, sp, #<imm7>
383 // FIXME: The encoding and the ASM string don't match up.
384 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
385 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
386 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
390 let DecoderMethod = "DecodeThumbAddSPImm";
393 def : tInstAlias<"add${p} sp, $imm",
394 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
395 def : tInstAlias<"add${p} sp, sp, $imm",
396 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
398 // Can optionally specify SP as a three operand instruction.
399 def : tInstAlias<"add${p} sp, sp, $imm",
400 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
401 def : tInstAlias<"sub${p} sp, sp, $imm",
402 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
405 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
406 "add", "\t$Rdn, $sp, $Rn", []>,
407 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
408 // A8.6.9 Encoding T1
410 let Inst{7} = Rdn{3};
411 let Inst{6-3} = 0b1101;
412 let Inst{2-0} = Rdn{2-0};
413 let DecoderMethod = "DecodeThumbAddSPReg";
417 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
418 "add", "\t$Rdn, $Rm", []>,
419 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
420 // A8.6.9 Encoding T2
424 let Inst{2-0} = 0b101;
425 let DecoderMethod = "DecodeThumbAddSPReg";
428 //===----------------------------------------------------------------------===//
429 // Control Flow Instructions.
433 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
434 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
435 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
439 let Inst{2-0} = 0b000;
440 let Unpredictable{2-0} = 0b111;
444 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
445 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
446 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
448 // Alternative return instruction used by vararg functions.
449 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
451 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
454 // All calls clobber the non-callee saved registers. SP is marked as a use to
455 // prevent stack-pointer assignments that appear immediately before calls from
456 // potentially appearing dead.
458 Defs = [LR], Uses = [SP] in {
459 // Also used for Thumb2
460 def tBL : TIx2<0b11110, 0b11, 1,
461 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
463 [(ARMtcall tglobaladdr:$func)]>,
464 Requires<[IsThumb]>, Sched<[WriteBrL]> {
466 let Inst{26} = func{23};
467 let Inst{25-16} = func{20-11};
468 let Inst{13} = func{22};
469 let Inst{11} = func{21};
470 let Inst{10-0} = func{10-0};
473 // ARMv5T and above, also used for Thumb2
474 def tBLXi : TIx2<0b11110, 0b11, 0,
475 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
477 [(ARMcall tglobaladdr:$func)]>,
478 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
480 let Inst{26} = func{23};
481 let Inst{25-16} = func{20-11};
482 let Inst{13} = func{22};
483 let Inst{11} = func{21};
484 let Inst{10-1} = func{10-1};
485 let Inst{0} = 0; // func{0} is assumed zero
488 // Also used for Thumb2
489 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
491 [(ARMtcall GPR:$func)]>,
492 Requires<[IsThumb, HasV5T]>,
493 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
495 let Inst{6-3} = func;
496 let Inst{2-0} = 0b000;
500 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
502 [(ARMcall_nolink tGPR:$func)]>,
503 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
506 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
507 let isPredicable = 1 in
508 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
509 "b", "\t$target", [(br bb:$target)]>,
510 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
512 let Inst{10-0} = target;
513 let AsmMatchConverter = "cvtThumbBranches";
517 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
518 // the clobber of LR.
520 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
521 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
524 def tBR_JTr : tPseudoInst<(outs),
525 (ins tGPR:$target, i32imm:$jt),
527 [(ARMbrjt tGPR:$target, tjumptable:$jt)]>,
528 Sched<[WriteBrTbl]> {
530 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
534 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
535 // a two-value operand where a dag node expects two operands. :(
536 let isBranch = 1, isTerminator = 1 in
537 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
539 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
540 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
544 let Inst{7-0} = target;
545 let AsmMatchConverter = "cvtThumbBranches";
550 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
553 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
555 (tBX GPR:$dst, (ops 14, zero_reg))>,
556 Requires<[IsThumb]>, Sched<[WriteBr]>;
558 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls
559 // on MachO), so it's in ARMInstrThumb2.td.
560 // Non-MachO version:
562 def tTAILJMPdND : tPseudoExpand<(outs),
563 (ins t_brtarget:$dst, pred:$p),
565 (tB t_brtarget:$dst, pred:$p)>,
566 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
571 // A8.6.218 Supervisor Call (Software Interrupt)
572 // A8.6.16 B: Encoding T1
573 // If Inst{11-8} == 0b1111 then SEE SVC
574 let isCall = 1, Uses = [SP] in
575 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
576 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
578 let Inst{15-12} = 0b1101;
579 let Inst{11-8} = 0b1111;
583 // The assembler uses 0xDEFE for a trap instruction.
584 let isBarrier = 1, isTerminator = 1 in
585 def tTRAP : TI<(outs), (ins), IIC_Br,
586 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
590 //===----------------------------------------------------------------------===//
591 // Load Store Instructions.
594 // PC-relative loads need to be matched first as constant pool accesses need to
595 // always be PC-relative. We do this using AddedComplexity, as the pattern is
596 // simpler than the patterns of the other load instructions.
597 let canFoldAsLoad = 1, isReMaterializable = 1, AddedComplexity = 10 in
598 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
599 "ldr", "\t$Rt, $addr",
600 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
601 T1Encoding<{0,1,0,0,1,?}> {
606 let Inst{7-0} = addr;
609 // SP-relative loads should be matched before standard immediate-offset loads as
610 // it means we avoid having to move SP to another register.
611 let canFoldAsLoad = 1 in
612 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
613 "ldr", "\t$Rt, $addr",
614 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
619 let Inst{7-0} = addr;
622 // Loads: reg/reg and reg/imm5
623 let canFoldAsLoad = 1, isReMaterializable = 1 in
624 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
625 Operand AddrMode_r, Operand AddrMode_i,
626 AddrMode am, InstrItinClass itin_r,
627 InstrItinClass itin_i, string asm,
629 // Immediate-offset loads should be matched before register-offset loads as
630 // when the offset is a constant it's simpler to first check if it fits in the
631 // immediate offset field then fall back to register-offset if it doesn't.
633 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
634 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
635 am, itin_i, asm, "\t$Rt, $addr",
636 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
637 // Register-offset loads are matched last.
639 T1pILdStEncode<reg_opc,
640 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
641 am, itin_r, asm, "\t$Rt, $addr",
642 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
644 // Stores: reg/reg and reg/imm5
645 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
646 Operand AddrMode_r, Operand AddrMode_i,
647 AddrMode am, InstrItinClass itin_r,
648 InstrItinClass itin_i, string asm,
651 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
652 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
653 am, itin_i, asm, "\t$Rt, $addr",
654 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
656 T1pILdStEncode<reg_opc,
657 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
658 am, itin_r, asm, "\t$Rt, $addr",
659 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
663 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rr,
664 t_addrmode_is4, AddrModeT1_4,
665 IIC_iLoad_r, IIC_iLoad_i, "ldr",
666 UnOpFrag<(load node:$Src)>>;
669 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rr,
670 t_addrmode_is1, AddrModeT1_1,
671 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
672 UnOpFrag<(zextloadi8 node:$Src)>>;
675 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rr,
676 t_addrmode_is2, AddrModeT1_2,
677 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
678 UnOpFrag<(zextloadi16 node:$Src)>>;
680 let AddedComplexity = 10 in
681 def tLDRSB : // A8.6.80
682 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
683 AddrModeT1_1, IIC_iLoad_bh_r,
684 "ldrsb", "\t$Rt, $addr",
685 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
687 let AddedComplexity = 10 in
688 def tLDRSH : // A8.6.84
689 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
690 AddrModeT1_2, IIC_iLoad_bh_r,
691 "ldrsh", "\t$Rt, $addr",
692 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
695 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
696 "str", "\t$Rt, $addr",
697 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
702 let Inst{7-0} = addr;
705 // A8.6.194 & A8.6.192
706 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rr,
707 t_addrmode_is4, AddrModeT1_4,
708 IIC_iStore_r, IIC_iStore_i, "str",
709 BinOpFrag<(store node:$LHS, node:$RHS)>>;
711 // A8.6.197 & A8.6.195
712 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rr,
713 t_addrmode_is1, AddrModeT1_1,
714 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
715 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
717 // A8.6.207 & A8.6.205
718 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rr,
719 t_addrmode_is2, AddrModeT1_2,
720 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
721 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
724 //===----------------------------------------------------------------------===//
725 // Load / store multiple Instructions.
728 // These require base address to be written back or one of the loaded regs.
729 let hasSideEffects = 0 in {
731 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
732 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
733 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
737 let Inst{7-0} = regs;
740 // Writeback version is just a pseudo, as there's no encoding difference.
741 // Writeback happens iff the base register is not in the destination register
744 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
745 "$Rn = $wb", IIC_iLoad_mu>,
746 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
748 let OutOperandList = (outs GPR:$wb);
749 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
751 let isCodeGenOnly = 1;
753 list<Predicate> Predicates = [IsThumb];
756 // There is no non-writeback version of STM for Thumb.
757 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
758 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
759 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
760 AddrModeNone, 2, IIC_iStore_mu,
761 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
762 T1Encoding<{1,1,0,0,0,?}> {
766 let Inst{7-0} = regs;
771 def : InstAlias<"ldm${p} $Rn!, $regs",
772 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
773 Requires<[IsThumb, IsThumb1Only]>;
775 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
776 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
778 "pop${p}\t$regs", []>,
779 T1Misc<{1,1,0,?,?,?,?}> {
781 let Inst{8} = regs{15};
782 let Inst{7-0} = regs{7-0};
785 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
786 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
788 "push${p}\t$regs", []>,
789 T1Misc<{0,1,0,?,?,?,?}> {
791 let Inst{8} = regs{14};
792 let Inst{7-0} = regs{7-0};
795 //===----------------------------------------------------------------------===//
796 // Arithmetic Instructions.
799 // Helper classes for encoding T1pI patterns:
800 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
801 string opc, string asm, list<dag> pattern>
802 : T1pI<oops, iops, itin, opc, asm, pattern>,
803 T1DataProcessing<opA> {
809 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
810 string opc, string asm, list<dag> pattern>
811 : T1pI<oops, iops, itin, opc, asm, pattern>,
819 // Helper classes for encoding T1sI patterns:
820 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
821 string opc, string asm, list<dag> pattern>
822 : T1sI<oops, iops, itin, opc, asm, pattern>,
823 T1DataProcessing<opA> {
829 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
830 string opc, string asm, list<dag> pattern>
831 : T1sI<oops, iops, itin, opc, asm, pattern>,
840 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
841 string opc, string asm, list<dag> pattern>
842 : T1sI<oops, iops, itin, opc, asm, pattern>,
850 // Helper classes for encoding T1sIt patterns:
851 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
852 string opc, string asm, list<dag> pattern>
853 : T1sIt<oops, iops, itin, opc, asm, pattern>,
854 T1DataProcessing<opA> {
860 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
861 string opc, string asm, list<dag> pattern>
862 : T1sIt<oops, iops, itin, opc, asm, pattern>,
866 let Inst{10-8} = Rdn;
867 let Inst{7-0} = imm8;
870 // Add with carry register
871 let isCommutable = 1, Uses = [CPSR] in
873 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
874 "adc", "\t$Rdn, $Rm",
875 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
878 def tADDi3 : // A8.6.4 T1
879 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
881 "add", "\t$Rd, $Rm, $imm3",
882 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
885 let Inst{8-6} = imm3;
888 def tADDi8 : // A8.6.4 T2
889 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
890 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
891 "add", "\t$Rdn, $imm8",
892 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
896 let isCommutable = 1 in
897 def tADDrr : // A8.6.6 T1
898 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
900 "add", "\t$Rd, $Rn, $Rm",
901 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
903 let hasSideEffects = 0 in
904 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
905 "add", "\t$Rdn, $Rm", []>,
906 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
910 let Inst{7} = Rdn{3};
912 let Inst{2-0} = Rdn{2-0};
916 let isCommutable = 1 in
917 def tAND : // A8.6.12
918 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
920 "and", "\t$Rdn, $Rm",
921 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
924 def tASRri : // A8.6.14
925 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
927 "asr", "\t$Rd, $Rm, $imm5",
928 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
931 let Inst{10-6} = imm5;
935 def tASRrr : // A8.6.15
936 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
938 "asr", "\t$Rdn, $Rm",
939 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
942 def tBIC : // A8.6.20
943 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
945 "bic", "\t$Rdn, $Rm",
946 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
950 let isCompare = 1, Defs = [CPSR] in {
951 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
952 // Compare-to-zero still works out, just not the relationals
953 //def tCMN : // A8.6.33
954 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
956 // "cmn", "\t$lhs, $rhs",
957 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
959 def tCMNz : // A8.6.33
960 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
963 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
965 } // isCompare = 1, Defs = [CPSR]
968 let isCompare = 1, Defs = [CPSR] in {
969 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
970 "cmp", "\t$Rn, $imm8",
971 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
972 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
977 let Inst{7-0} = imm8;
981 def tCMPr : // A8.6.36 T1
982 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
985 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
987 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
988 "cmp", "\t$Rn, $Rm", []>,
989 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
995 let Inst{2-0} = Rn{2-0};
997 } // isCompare = 1, Defs = [CPSR]
1001 let isCommutable = 1 in
1002 def tEOR : // A8.6.45
1003 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1005 "eor", "\t$Rdn, $Rm",
1006 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1009 def tLSLri : // A8.6.88
1010 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1012 "lsl", "\t$Rd, $Rm, $imm5",
1013 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1016 let Inst{10-6} = imm5;
1020 def tLSLrr : // A8.6.89
1021 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1023 "lsl", "\t$Rdn, $Rm",
1024 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1027 def tLSRri : // A8.6.90
1028 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1030 "lsr", "\t$Rd, $Rm, $imm5",
1031 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1034 let Inst{10-6} = imm5;
1038 def tLSRrr : // A8.6.91
1039 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1041 "lsr", "\t$Rdn, $Rm",
1042 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1045 let isMoveImm = 1 in
1046 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1047 "mov", "\t$Rd, $imm8",
1048 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1049 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1053 let Inst{10-8} = Rd;
1054 let Inst{7-0} = imm8;
1056 // Because we have an explicit tMOVSr below, we need an alias to handle
1057 // the immediate "movs" form here. Blech.
1058 def : tInstAlias <"movs $Rdn, $imm",
1059 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1061 // A7-73: MOV(2) - mov setting flag.
1063 let hasSideEffects = 0 in {
1064 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1066 "mov", "\t$Rd, $Rm", "", []>,
1067 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1071 let Inst{7} = Rd{3};
1073 let Inst{2-0} = Rd{2-0};
1075 let Defs = [CPSR] in
1076 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1077 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1081 let Inst{15-6} = 0b0000000000;
1087 // Multiply register
1088 let isCommutable = 1 in
1089 def tMUL : // A8.6.105 T1
1090 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1091 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1092 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1093 T1DataProcessing<0b1101> {
1098 let AsmMatchConverter = "cvtThumbMultiply";
1101 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1104 // Move inverse register
1105 def tMVN : // A8.6.107
1106 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1107 "mvn", "\t$Rd, $Rn",
1108 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1110 // Bitwise or register
1111 let isCommutable = 1 in
1112 def tORR : // A8.6.114
1113 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1115 "orr", "\t$Rdn, $Rm",
1116 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1119 def tREV : // A8.6.134
1120 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1122 "rev", "\t$Rd, $Rm",
1123 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1124 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1126 def tREV16 : // A8.6.135
1127 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1129 "rev16", "\t$Rd, $Rm",
1130 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1131 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1133 def tREVSH : // A8.6.136
1134 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1136 "revsh", "\t$Rd, $Rm",
1137 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1138 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1140 // Rotate right register
1141 def tROR : // A8.6.139
1142 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1144 "ror", "\t$Rdn, $Rm",
1145 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1149 def tRSB : // A8.6.141
1150 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1152 "rsb", "\t$Rd, $Rn, #0",
1153 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1155 // Subtract with carry register
1156 let Uses = [CPSR] in
1157 def tSBC : // A8.6.151
1158 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1160 "sbc", "\t$Rdn, $Rm",
1161 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
1164 // Subtract immediate
1165 def tSUBi3 : // A8.6.210 T1
1166 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1168 "sub", "\t$Rd, $Rm, $imm3",
1169 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1172 let Inst{8-6} = imm3;
1175 def tSUBi8 : // A8.6.210 T2
1176 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1177 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1178 "sub", "\t$Rdn, $imm8",
1179 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1182 // Subtract register
1183 def tSUBrr : // A8.6.212
1184 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1186 "sub", "\t$Rd, $Rn, $Rm",
1187 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1191 def tSXTB : // A8.6.222
1192 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1194 "sxtb", "\t$Rd, $Rm",
1195 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1196 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1199 // Sign-extend short
1200 def tSXTH : // A8.6.224
1201 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1203 "sxth", "\t$Rd, $Rm",
1204 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1205 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1209 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1210 def tTST : // A8.6.230
1211 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1212 "tst", "\t$Rn, $Rm",
1213 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1216 // A8.8.247 UDF - Undefined (Encoding T1)
1217 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
1218 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 {
1220 let Inst{15-12} = 0b1101;
1221 let Inst{11-8} = 0b1110;
1222 let Inst{7-0} = imm8;
1226 def tUXTB : // A8.6.262
1227 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1229 "uxtb", "\t$Rd, $Rm",
1230 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1231 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1234 // Zero-extend short
1235 def tUXTH : // A8.6.264
1236 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1238 "uxth", "\t$Rd, $Rm",
1239 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1240 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1242 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1243 // Expanded after instruction selection into a branch sequence.
1244 let usesCustomInserter = 1 in // Expanded after instruction selection.
1245 def tMOVCCr_pseudo :
1246 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p),
1248 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>;
1250 // tLEApcrel - Load a pc-relative address into a register without offending the
1253 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1254 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1255 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1258 let Inst{10-8} = Rd;
1259 let Inst{7-0} = addr;
1260 let DecoderMethod = "DecodeThumbAddSpecialReg";
1263 let hasSideEffects = 0, isReMaterializable = 1 in
1264 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1265 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1267 let hasSideEffects = 1 in
1268 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1269 (ins i32imm:$label, pred:$p),
1270 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1272 //===----------------------------------------------------------------------===//
1276 // __aeabi_read_tp preserves the registers r1-r3.
1277 // This is a pseudo inst so that we can get the encoding right,
1278 // complete with fixup for the aeabi_read_tp function.
1279 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1280 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1281 [(set R0, ARMthread_pointer)]>,
1284 //===----------------------------------------------------------------------===//
1285 // SJLJ Exception handling intrinsics
1288 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1289 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1290 // from some other function to get here, and we're using the stack frame for the
1291 // containing function to save/restore registers, we can't keep anything live in
1292 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1293 // tromped upon when we get here from a longjmp(). We force everything out of
1294 // registers except for our own input by listing the relevant registers in
1295 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1296 // preserve all of the callee-saved resgisters, which is exactly what we want.
1297 // $val is a scratch register for our use.
1298 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1299 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1300 usesCustomInserter = 1 in
1301 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1302 AddrModeNone, 0, NoItinerary, "","",
1303 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1305 // FIXME: Non-IOS version(s)
1306 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1307 Defs = [ R7, LR, SP ] in
1308 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1309 AddrModeNone, 0, IndexModeNone,
1310 Pseudo, NoItinerary, "", "",
1311 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1312 Requires<[IsThumb]>;
1314 //===----------------------------------------------------------------------===//
1315 // Non-Instruction Patterns
1319 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1320 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1321 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1322 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1325 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1326 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1327 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1328 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1329 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1330 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1332 // Subtract with carry
1333 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1334 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1335 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1336 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1337 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1338 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1340 // Bswap 16 with load/store
1341 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
1342 (tREV16 (tLDRHi t_addrmode_is2:$addr))>;
1343 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rr:$addr)), (i32 16)),
1344 (tREV16 (tLDRHr t_addrmode_rr:$addr))>;
1345 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1346 t_addrmode_is2:$addr),
1347 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;
1348 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1349 t_addrmode_rr:$addr),
1350 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rr:$addr)>;
1353 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1356 def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),
1359 (ARMWrapperPIC tglobaladdr:$addr))]>,
1360 Requires<[IsThumb, DontUseMovt]>;
1362 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
1365 (ARMWrapper tglobaladdr:$src))]>,
1366 Requires<[IsThumb, DontUseMovt]>;
1370 def : T1Pat<(ARMWrapperJT tjumptable:$dst),
1371 (tLEApcrelJT tjumptable:$dst)>;
1374 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1375 Requires<[IsThumb]>;
1377 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1378 Requires<[IsThumb, HasV5T, IsNotMClass]>;
1380 // Indirect calls to ARM routines
1381 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1382 Requires<[IsThumb, HasV5T]>;
1384 // zextload i1 -> zextload i8
1385 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1386 (tLDRBi t_addrmode_is1:$addr)>;
1387 def : T1Pat<(zextloadi1 t_addrmode_rr:$addr),
1388 (tLDRBr t_addrmode_rr:$addr)>;
1390 // extload from the stack -> word load from the stack, as it avoids having to
1391 // materialize the base in a separate register. This only works when a word
1392 // load puts the byte/halfword value in the same place in the register that the
1393 // byte/halfword load would, i.e. when little-endian.
1394 def : T1Pat<(extloadi1 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1395 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1396 def : T1Pat<(extloadi8 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1397 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1398 def : T1Pat<(extloadi16 t_addrmode_sp:$addr), (tLDRspi t_addrmode_sp:$addr)>,
1399 Requires<[IsThumb, IsThumb1Only, IsLE]>;
1401 // extload -> zextload
1402 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1403 def : T1Pat<(extloadi1 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1404 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1405 def : T1Pat<(extloadi8 t_addrmode_rr:$addr), (tLDRBr t_addrmode_rr:$addr)>;
1406 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1407 def : T1Pat<(extloadi16 t_addrmode_rr:$addr), (tLDRHr t_addrmode_rr:$addr)>;
1409 // If it's impossible to use [r,r] address mode for sextload, select to
1410 // ldr{b|h} + sxt{b|h} instead.
1411 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1412 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1413 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1414 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1415 (tSXTB (tLDRBr t_addrmode_rr:$addr))>,
1416 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1417 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1418 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1419 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1420 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1421 (tSXTH (tLDRHr t_addrmode_rr:$addr))>,
1422 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1424 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1425 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1426 def : T1Pat<(sextloadi8 t_addrmode_rr:$addr),
1427 (tASRri (tLSLri (tLDRBr t_addrmode_rr:$addr), 24), 24)>;
1428 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1429 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1430 def : T1Pat<(sextloadi16 t_addrmode_rr:$addr),
1431 (tASRri (tLSLri (tLDRHr t_addrmode_rr:$addr), 16), 16)>;
1433 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1434 (tLDRBi t_addrmode_is1:$src)>;
1435 def : T1Pat<(atomic_load_8 t_addrmode_rr:$src),
1436 (tLDRBr t_addrmode_rr:$src)>;
1437 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1438 (tLDRHi t_addrmode_is2:$src)>;
1439 def : T1Pat<(atomic_load_16 t_addrmode_rr:$src),
1440 (tLDRHr t_addrmode_rr:$src)>;
1441 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1442 (tLDRi t_addrmode_is4:$src)>;
1443 def : T1Pat<(atomic_load_32 t_addrmode_rr:$src),
1444 (tLDRr t_addrmode_rr:$src)>;
1445 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1446 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1447 def : T1Pat<(atomic_store_8 t_addrmode_rr:$ptr, tGPR:$val),
1448 (tSTRBr tGPR:$val, t_addrmode_rr:$ptr)>;
1449 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1450 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1451 def : T1Pat<(atomic_store_16 t_addrmode_rr:$ptr, tGPR:$val),
1452 (tSTRHr tGPR:$val, t_addrmode_rr:$ptr)>;
1453 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1454 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1455 def : T1Pat<(atomic_store_32 t_addrmode_rr:$ptr, tGPR:$val),
1456 (tSTRr tGPR:$val, t_addrmode_rr:$ptr)>;
1458 // Large immediate handling.
1461 def : T1Pat<(i32 thumb_immshifted:$src),
1462 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1463 (thumb_immshifted_shamt imm:$src))>;
1465 def : T1Pat<(i32 imm0_255_comp:$src),
1466 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1468 // Pseudo instruction that combines ldr from constpool and add pc. This should
1469 // be expanded into two instructions late to allow if-conversion and
1471 let isReMaterializable = 1 in
1472 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1474 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1476 Requires<[IsThumb, IsThumb1Only]>;
1478 // Pseudo-instruction for merged POP and return.
1479 // FIXME: remove when we have a way to marking a MI with these properties.
1480 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1481 hasExtraDefRegAllocReq = 1 in
1482 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1484 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1486 // Indirect branch using "mov pc, $Rm"
1487 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1488 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1489 2, IIC_Br, [(brind GPR:$Rm)],
1490 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1494 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1495 // encoding is available on ARMv6K, but we don't differentiate that finely.
1496 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1499 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1500 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1501 // a useful extension and assembles to defined behaviour (the insn does
1503 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1504 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1506 // "neg" is and alias for "rsb rd, rn, #0"
1507 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1508 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1511 // Implied destination operand forms for shifts.
1512 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1513 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1514 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1515 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1516 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1517 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;