1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
135 //===----------------------------------------------------------------------===//
136 // Control Flow Instructions.
139 let isReturn = 1, isTerminator = 1 in {
140 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
141 // Alternative return instruction used by vararg functions.
142 def tBX_RET_vararg : TI<(outs), (ins GPR:$target), "bx $target", []>;
145 // FIXME: remove when we have a way to marking a MI with these properties.
146 let isReturn = 1, isTerminator = 1 in
147 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
151 Defs = [R0, R1, R2, R3, LR,
152 D0, D1, D2, D3, D4, D5, D6, D7] in {
153 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
155 [(ARMtcall tglobaladdr:$func)]>;
157 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
159 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
160 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops),
162 [(ARMtcall GPR:$func)]>, Requires<[HasV5T]>;
164 def tBX : TIx2<(outs), (ins GPR:$func, variable_ops),
165 "cpy lr, pc\n\tbx $func",
166 [(ARMcall_nolink GPR:$func)]>;
169 let isBranch = 1, isTerminator = 1 in {
170 let isBarrier = 1 in {
171 let isPredicable = 1 in
172 def tB : TI<(outs), (ins brtarget:$target), "b $target",
176 def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
178 def tBR_JTr : TJTI<(outs),
179 (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
180 "cpy pc, $target \n\t.align\t2\n$jt",
181 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
185 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
186 // a two-value operand where a dag node expects two operands. :(
187 let isBranch = 1, isTerminator = 1 in
188 def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
189 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
191 //===----------------------------------------------------------------------===//
192 // Load Store Instructions.
195 let canFoldAsLoad = 1 in
196 def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
198 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
200 def tLDRB : TI1<(outs GPR:$dst), (ins t_addrmode_s1:$addr),
202 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
204 def tLDRH : TI2<(outs GPR:$dst), (ins t_addrmode_s2:$addr),
206 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
208 def tLDRSB : TI1<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
210 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
212 def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
214 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
216 let canFoldAsLoad = 1 in
217 def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
219 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
221 // Special instruction for restore. It cannot clobber condition register
222 // when it's expanded by eliminateCallFramePseudoInstr().
223 let canFoldAsLoad = 1, mayLoad = 1 in
224 def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
225 "ldr $dst, $addr", []>;
228 let canFoldAsLoad = 1 in
229 def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
231 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
233 // Special LDR for loads from non-pc-relative constpools.
234 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
235 def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
236 "ldr $dst, $addr", []>;
238 def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
240 [(store GPR:$src, t_addrmode_s4:$addr)]>;
242 def tSTRB : TI1<(outs), (ins GPR:$src, t_addrmode_s1:$addr),
244 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
246 def tSTRH : TI2<(outs), (ins GPR:$src, t_addrmode_s2:$addr),
248 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
250 def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
252 [(store GPR:$src, t_addrmode_sp:$addr)]>;
254 let mayStore = 1 in {
255 // Special instruction for spill. It cannot clobber condition register
256 // when it's expanded by eliminateCallFramePseudoInstr().
257 def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
258 "str $src, $addr", []>;
261 //===----------------------------------------------------------------------===//
262 // Load / store multiple Instructions.
265 // TODO: A7-44: LDMIA - load multiple
268 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
272 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
275 //===----------------------------------------------------------------------===//
276 // Arithmetic Instructions.
280 def tADC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
282 [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
284 def tADDS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
285 "add $dst, $lhs, $rhs",
286 [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
289 def tADDi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
290 "add $dst, $lhs, $rhs",
291 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
293 def tADDi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
295 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
297 def tADDrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
298 "add $dst, $lhs, $rhs",
299 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
301 def tADDhirr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
302 "add $dst, $rhs", []>;
304 def tADDrPCi : TI<(outs GPR:$dst), (ins i32imm:$rhs),
305 "add $dst, pc, $rhs * 4", []>;
306 def tADDrSPi : TI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$rhs),
307 "add $dst, $sp, $rhs * 4", []>;
308 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
309 "add $dst, $rhs * 4", []>;
311 def tAND : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
313 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
315 def tASRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
316 "asr $dst, $lhs, $rhs",
317 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
319 def tASRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
321 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
323 def tBIC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
325 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
328 def tCMN : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
330 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
332 def tCMPi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
334 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
336 def tCMPr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
338 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
340 def tTST : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
342 [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
344 def tCMNNZ : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
346 [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
348 def tCMPNZi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
350 [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
352 def tCMPNZr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
354 [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
356 // TODO: A7-37: CMP(3) - cmp hi regs
358 def tEOR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
360 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
362 def tLSLri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
363 "lsl $dst, $lhs, $rhs",
364 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
366 def tLSLrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
368 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
370 def tLSRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
371 "lsr $dst, $lhs, $rhs",
372 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
374 def tLSRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
376 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
378 // FIXME: This is not rematerializable because mov changes the condition code.
379 def tMOVi8 : TI<(outs GPR:$dst), (ins i32imm:$src),
381 [(set GPR:$dst, imm0_255:$src)]>;
383 // TODO: A7-73: MOV(2) - mov setting flag.
386 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
387 // which is MOV(3). This also supports high registers.
388 def tMOVr : TI<(outs GPR:$dst), (ins GPR:$src),
389 "cpy $dst, $src", []>;
391 def tMUL : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
393 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
395 def tMVN : TI<(outs GPR:$dst), (ins GPR:$src),
397 [(set GPR:$dst, (not GPR:$src))]>;
399 def tNEG : TI<(outs GPR:$dst), (ins GPR:$src),
401 [(set GPR:$dst, (ineg GPR:$src))]>;
403 def tORR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
405 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
408 def tREV : TI<(outs GPR:$dst), (ins GPR:$src),
410 [(set GPR:$dst, (bswap GPR:$src))]>,
411 Requires<[IsThumb, HasV6]>;
413 def tREV16 : TI<(outs GPR:$dst), (ins GPR:$src),
416 (or (and (srl GPR:$src, 8), 0xFF),
417 (or (and (shl GPR:$src, 8), 0xFF00),
418 (or (and (srl GPR:$src, 8), 0xFF0000),
419 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
420 Requires<[IsThumb, HasV6]>;
422 def tREVSH : TI<(outs GPR:$dst), (ins GPR:$src),
426 (or (srl (and GPR:$src, 0xFFFF), 8),
427 (shl GPR:$src, 8)), i16))]>,
428 Requires<[IsThumb, HasV6]>;
430 def tROR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
432 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
435 // Subtract with carry
436 def tSBC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
438 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
440 def tSUBS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
441 "sub $dst, $lhs, $rhs",
442 [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
445 // TODO: A7-96: STMIA - store multiple.
447 def tSUBi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
448 "sub $dst, $lhs, $rhs",
449 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
451 def tSUBi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
453 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
455 def tSUBrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
456 "sub $dst, $lhs, $rhs",
457 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
459 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
460 "sub $dst, $rhs * 4", []>;
462 def tSXTB : TI<(outs GPR:$dst), (ins GPR:$src),
464 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
465 Requires<[IsThumb, HasV6]>;
466 def tSXTH : TI<(outs GPR:$dst), (ins GPR:$src),
468 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
469 Requires<[IsThumb, HasV6]>;
472 def tUXTB : TI<(outs GPR:$dst), (ins GPR:$src),
474 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
475 Requires<[IsThumb, HasV6]>;
476 def tUXTH : TI<(outs GPR:$dst), (ins GPR:$src),
478 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
479 Requires<[IsThumb, HasV6]>;
482 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
483 // Expanded by the scheduler into a branch sequence.
484 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
486 PseudoInst<(outs GPR:$dst), (ins GPR:$false, GPR:$true, pred:$cc),
488 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
490 // tLEApcrel - Load a pc-relative address into a register without offending the
492 def tLEApcrel : TIx2<(outs GPR:$dst), (ins i32imm:$label),
493 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
494 "${:private}PCRELL${:uid}+4))\n"),
495 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
496 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
499 def tLEApcrelJT : TIx2<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id),
500 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
501 "${:private}PCRELL${:uid}+4))\n"),
502 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
503 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
506 //===----------------------------------------------------------------------===//
510 // __aeabi_read_tp preserves the registers r1-r3.
513 def tTPsoft : TIx2<(outs), (ins),
514 "bl __aeabi_read_tp",
515 [(set R0, ARMthread_pointer)]>;
518 //===----------------------------------------------------------------------===//
519 // Non-Instruction Patterns
522 // ConstantPool, GlobalAddress
523 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
524 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
527 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
528 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
531 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
532 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
534 // Indirect calls to ARM routines
535 def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
537 // zextload i1 -> zextload i8
538 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
539 (tLDRB t_addrmode_s1:$addr)>;
541 // extload -> zextload
542 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
543 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
544 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
546 // Large immediate handling.
549 def : ThumbPat<(i32 thumb_immshifted:$src),
550 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
551 (thumb_immshifted_shamt imm:$src))>;
553 def : ThumbPat<(i32 imm0_255_comp:$src),
554 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;