1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
136 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
137 "add $dst, pc, $rhs * 4", []>;
140 // FIXME: hard code sp?
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
142 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
145 // FIXME: hard code sp?
146 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
147 "add $dst, $rhs * 4", []>;
149 // FIXME: Make use of the following?
153 //===----------------------------------------------------------------------===//
154 // Control Flow Instructions.
157 let isReturn = 1, isTerminator = 1 in {
158 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
159 // Alternative return instruction used by vararg functions.
160 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
163 // FIXME: remove when we have a way to marking a MI with these properties.
164 let isReturn = 1, isTerminator = 1 in
165 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
169 Defs = [R0, R1, R2, R3, R12, LR,
170 D0, D1, D2, D3, D4, D5, D6, D7,
171 D16, D17, D18, D19, D20, D21, D22, D23,
172 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
173 def tBL : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
175 [(ARMtcall tglobaladdr:$func)]>,
176 Requires<[IsThumb1Only, IsNotDarwin]>;
179 def tBLXi : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
181 [(ARMcall tglobaladdr:$func)]>,
182 Requires<[IsThumb1Only, HasV5T, IsNotDarwin]>;
184 def tBLXr : T1I<(outs), (ins tGPR:$func, variable_ops),
186 [(ARMtcall tGPR:$func)]>,
187 Requires<[IsThumb1Only, HasV5T, IsNotDarwin]>;
190 def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
191 "mov lr, pc\n\tbx $func",
192 [(ARMcall_nolink tGPR:$func)]>,
193 Requires<[IsThumb1Only, IsNotDarwin]>;
196 // On Darwin R9 is call-clobbered.
198 Defs = [R0, R1, R2, R3, R9, R12, LR,
199 D0, D1, D2, D3, D4, D5, D6, D7,
200 D16, D17, D18, D19, D20, D21, D22, D23,
201 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
202 def tBLr9 : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
204 [(ARMtcall tglobaladdr:$func)]>,
205 Requires<[IsThumb1Only, IsDarwin]>;
208 def tBLXi_r9 : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
210 [(ARMcall tglobaladdr:$func)]>,
211 Requires<[IsThumb1Only, HasV5T, IsDarwin]>;
213 def tBLXr_r9 : T1I<(outs), (ins tGPR:$func, variable_ops),
215 [(ARMtcall tGPR:$func)]>,
216 Requires<[IsThumb1Only, HasV5T, IsDarwin]>;
219 def tBXr9 : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
220 "mov lr, pc\n\tbx $func",
221 [(ARMcall_nolink tGPR:$func)]>,
222 Requires<[IsThumb1Only, IsDarwin]>;
225 let isBranch = 1, isTerminator = 1 in {
226 let isBarrier = 1 in {
227 let isPredicable = 1 in
228 def tB : T1I<(outs), (ins brtarget:$target), "b $target",
232 def tBfar : T1Ix2<(outs), (ins brtarget:$target),
233 "bl $target\t@ far jump",[]>;
235 def tBR_JTr : T1JTI<(outs),
236 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
237 "mov pc, $target\n\t.align\t2\n$jt",
238 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
242 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
243 // a two-value operand where a dag node expects two operands. :(
244 let isBranch = 1, isTerminator = 1 in
245 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
246 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
248 //===----------------------------------------------------------------------===//
249 // Load Store Instructions.
252 let canFoldAsLoad = 1 in
253 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
254 "ldr", " $dst, $addr",
255 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
257 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
258 "ldrb", " $dst, $addr",
259 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
261 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
262 "ldrh", " $dst, $addr",
263 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
265 let AddedComplexity = 10 in
266 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
267 "ldrsb", " $dst, $addr",
268 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
270 let AddedComplexity = 10 in
271 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
272 "ldrsh", " $dst, $addr",
273 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
275 let canFoldAsLoad = 1 in
276 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
277 "ldr", " $dst, $addr",
278 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
280 // Special instruction for restore. It cannot clobber condition register
281 // when it's expanded by eliminateCallFramePseudoInstr().
282 let canFoldAsLoad = 1, mayLoad = 1 in
283 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
284 "ldr", " $dst, $addr", []>;
287 let canFoldAsLoad = 1 in
288 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
289 "ldr", " $dst, $addr",
290 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
292 // Special LDR for loads from non-pc-relative constpools.
293 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
294 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
295 "ldr", " $dst, $addr", []>;
297 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
298 "str", " $src, $addr",
299 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
301 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
302 "strb", " $src, $addr",
303 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
305 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
306 "strh", " $src, $addr",
307 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
309 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
310 "str", " $src, $addr",
311 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
313 let mayStore = 1 in {
314 // Special instruction for spill. It cannot clobber condition register
315 // when it's expanded by eliminateCallFramePseudoInstr().
316 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
317 "str", " $src, $addr", []>;
320 //===----------------------------------------------------------------------===//
321 // Load / store multiple Instructions.
324 // TODO: A7-44: LDMIA - load multiple
325 // TODO: Allow these to be predicated
328 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
332 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
335 //===----------------------------------------------------------------------===//
336 // Arithmetic Instructions.
339 // Add with carry register
340 let isCommutable = 1, Uses = [CPSR] in
341 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
342 "adc", " $dst, $rhs",
343 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
346 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
347 "add", " $dst, $lhs, $rhs",
348 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
350 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
351 "add", " $dst, $rhs",
352 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
355 let isCommutable = 1 in
356 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
357 "add", " $dst, $lhs, $rhs",
358 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
360 let neverHasSideEffects = 1 in
361 def tADDhirr : T1pIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
362 "add", " $dst, $rhs @ addhirr", []>;
365 let isCommutable = 1 in
366 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
367 "and", " $dst, $rhs",
368 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
371 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
372 "asr", " $dst, $lhs, $rhs",
373 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
376 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
377 "asr", " $dst, $rhs",
378 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
381 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
382 "bic", " $dst, $rhs",
383 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
386 let Defs = [CPSR] in {
387 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
388 "cmn", " $lhs, $rhs",
389 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
390 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
391 "cmn", " $lhs, $rhs",
392 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
396 let Defs = [CPSR] in {
397 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
398 "cmp", " $lhs, $rhs",
399 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
400 def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
401 "cmp", " $lhs, $rhs",
402 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
407 let Defs = [CPSR] in {
408 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
409 "cmp", " $lhs, $rhs",
410 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
411 def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
412 "cmp", " $lhs, $rhs",
413 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
415 // TODO: Make use of the followings cmp hi regs
416 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
417 "cmp", " $lhs, $rhs", []>;
418 def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
419 "cmp", " $lhs, $rhs", []>;
424 let isCommutable = 1 in
425 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
426 "eor", " $dst, $rhs",
427 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
430 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
431 "lsl", " $dst, $lhs, $rhs",
432 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
435 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
436 "lsl", " $dst, $rhs",
437 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
440 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
441 "lsr", " $dst, $lhs, $rhs",
442 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
445 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
446 "lsr", " $dst, $rhs",
447 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
450 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src),
451 "mov", " $dst, $src",
452 [(set tGPR:$dst, imm0_255:$src)]>;
454 // TODO: A7-73: MOV(2) - mov setting flag.
457 let neverHasSideEffects = 1 in {
458 // FIXME: Make this predicable.
459 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
460 "mov $dst, $src", []>;
462 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
463 "movs $dst, $src", []>;
465 // FIXME: Make these predicable.
466 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src),
467 "mov $dst, $src\t@ hir2lor", []>;
468 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src),
469 "mov $dst, $src\t@ lor2hir", []>;
470 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src),
471 "mov $dst, $src\t@ hir2hir", []>;
472 } // neverHasSideEffects
475 let isCommutable = 1 in
476 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
477 "mul", " $dst, $rhs",
478 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
480 // move inverse register
481 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
482 "mvn", " $dst, $src",
483 [(set tGPR:$dst, (not tGPR:$src))]>;
485 // bitwise or register
486 let isCommutable = 1 in
487 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
488 "orr", " $dst, $rhs",
489 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
492 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
493 "rev", " $dst, $src",
494 [(set tGPR:$dst, (bswap tGPR:$src))]>,
495 Requires<[IsThumb1Only, HasV6]>;
497 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
498 "rev16", " $dst, $src",
500 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
501 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
502 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
503 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
504 Requires<[IsThumb1Only, HasV6]>;
506 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
507 "revsh", " $dst, $src",
510 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
511 (shl tGPR:$src, (i32 8))), i16))]>,
512 Requires<[IsThumb1Only, HasV6]>;
514 // rotate right register
515 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
516 "ror", " $dst, $rhs",
517 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
520 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
521 "rsb", " $dst, $src, #0",
522 [(set tGPR:$dst, (ineg tGPR:$src))]>;
524 // Subtract with carry register
526 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
527 "sbc", " $dst, $rhs",
528 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
530 // Subtract immediate
531 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
532 "sub", " $dst, $lhs, $rhs",
533 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
535 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
536 "sub", " $dst, $rhs",
537 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
540 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
541 "sub", " $dst, $lhs, $rhs",
542 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
544 // TODO: A7-96: STMIA - store multiple.
546 def tSUBspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
547 "sub $dst, $rhs * 4", []>;
550 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
551 "sxtb", " $dst, $src",
552 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
553 Requires<[IsThumb1Only, HasV6]>;
556 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
557 "sxth", " $dst, $src",
558 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
559 Requires<[IsThumb1Only, HasV6]>;
562 let isCommutable = 1, Defs = [CPSR] in
563 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
564 "tst", " $lhs, $rhs",
565 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
568 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
569 "uxtb", " $dst, $src",
570 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
571 Requires<[IsThumb1Only, HasV6]>;
574 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
575 "uxth", " $dst, $src",
576 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
577 Requires<[IsThumb1Only, HasV6]>;
580 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
581 // Expanded by the scheduler into a branch sequence.
582 // FIXME: Add actual movcc in IT blocks for Thumb2.
583 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
585 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
587 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
589 // tLEApcrel - Load a pc-relative address into a register without offending the
591 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label),
592 "adr $dst, #$label", []>;
594 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
595 "adr $dst, #${label}_${id:no_hash}", []>;
597 //===----------------------------------------------------------------------===//
601 // __aeabi_read_tp preserves the registers r1-r3.
604 def tTPsoft : T1Ix2<(outs), (ins),
605 "bl __aeabi_read_tp",
606 [(set R0, ARMthread_pointer)]>;
609 //===----------------------------------------------------------------------===//
610 // Non-Instruction Patterns
614 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
615 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
616 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
617 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
618 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
619 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
621 // Subtract with carry
622 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
623 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
624 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
625 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
626 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
627 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
629 // ConstantPool, GlobalAddress
630 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
631 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
634 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
635 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
638 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
639 Requires<[IsThumb1Only, IsNotDarwin]>;
640 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
641 Requires<[IsThumb1Only, IsDarwin]>;
643 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
644 Requires<[IsThumb1Only, HasV5T, IsNotDarwin]>;
645 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
646 Requires<[IsThumb1Only, HasV5T, IsDarwin]>;
648 // Indirect calls to ARM routines
649 def : Tv5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>,
650 Requires<[IsThumb1Only, HasV5T, IsNotDarwin]>;
651 def : Tv5Pat<(ARMcall tGPR:$dst), (tBLXr_r9 tGPR:$dst)>,
652 Requires<[IsThumb1Only, HasV5T, IsDarwin]>;
654 // zextload i1 -> zextload i8
655 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
656 (tLDRB t_addrmode_s1:$addr)>;
658 // extload -> zextload
659 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
660 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
661 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
663 // If it's possible to use [r,r] address mode for sextload, select to
664 // ldr{b|h} + sxt{b|h} instead.
665 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
666 (tSXTB (tLDRB t_addrmode_s1:$addr))>;
667 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
668 (tSXTH (tLDRH t_addrmode_s2:$addr))>;
671 // Large immediate handling.
674 def : T1Pat<(i32 thumb_immshifted:$src),
675 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
676 (thumb_immshifted_shamt imm:$src))>;
678 def : T1Pat<(i32 imm0_255_comp:$src),
679 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;