1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 // TI - Thumb instruction.
23 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
28 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
32 class ThumbI<dag outs, dag ins, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, ThumbFrm, cstr> {
36 let OutOperandList = outs;
37 let InOperandList = ins;
39 let Pattern = pattern;
40 list<Predicate> Predicates = [IsThumb];
43 class TI<dag outs, dag ins, string asm, list<dag> pattern>
44 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "", pattern>;
45 class TI1<dag outs, dag ins, string asm, list<dag> pattern>
46 : ThumbI<outs, ins, AddrModeT1, Size2Bytes, asm, "", pattern>;
47 class TI2<dag outs, dag ins, string asm, list<dag> pattern>
48 : ThumbI<outs, ins, AddrModeT2, Size2Bytes, asm, "", pattern>;
49 class TI4<dag outs, dag ins, string asm, list<dag> pattern>
50 : ThumbI<outs, ins, AddrModeT4, Size2Bytes, asm, "", pattern>;
51 class TIs<dag outs, dag ins, string asm, list<dag> pattern>
52 : ThumbI<outs, ins, AddrModeTs, Size2Bytes, asm, "", pattern>;
54 // Two-address instructions
55 class TIt<dag outs, dag ins, string asm, list<dag> pattern>
56 : ThumbI<outs, ins, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
58 // BL, BLX(1) are translated by assembler into two instructions
59 class TIx2<dag outs, dag ins, string asm, list<dag> pattern>
60 : ThumbI<outs, ins, AddrModeNone, Size4Bytes, asm, "", pattern>;
63 class TJTI<dag outs, dag ins, string asm, list<dag> pattern>
64 : ThumbI<outs, ins, AddrModeNone, SizeSpecial, asm, "", pattern>;
66 def imm_neg_XFORM : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
69 def imm_comp_XFORM : SDNodeXForm<imm, [{
70 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
74 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
75 def imm0_7 : PatLeaf<(i32 imm), [{
76 return (uint32_t)N->getValue() < 8;
78 def imm0_7_neg : PatLeaf<(i32 imm), [{
79 return (uint32_t)-N->getValue() < 8;
82 def imm0_255 : PatLeaf<(i32 imm), [{
83 return (uint32_t)N->getValue() < 256;
85 def imm0_255_comp : PatLeaf<(i32 imm), [{
86 return ~((uint32_t)N->getValue()) < 256;
89 def imm8_255 : PatLeaf<(i32 imm), [{
90 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
92 def imm8_255_neg : PatLeaf<(i32 imm), [{
93 unsigned Val = -N->getValue();
94 return Val >= 8 && Val < 256;
97 // Break imm's up into two pieces: an immediate + a left shift.
98 // This uses thumb_immshifted to match and thumb_immshifted_val and
99 // thumb_immshifted_shamt to get the val/shift pieces.
100 def thumb_immshifted : PatLeaf<(imm), [{
101 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
104 def thumb_immshifted_val : SDNodeXForm<imm, [{
105 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
106 return CurDAG->getTargetConstant(V, MVT::i32);
109 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
110 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
111 return CurDAG->getTargetConstant(V, MVT::i32);
114 // Define Thumb specific addressing modes.
116 // t_addrmode_rr := reg + reg
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let PrintMethod = "printThumbAddrModeRROperand";
121 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
124 // t_addrmode_s4 := reg + reg
127 def t_addrmode_s4 : Operand<i32>,
128 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
129 let PrintMethod = "printThumbAddrModeS4Operand";
130 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
133 // t_addrmode_s2 := reg + reg
136 def t_addrmode_s2 : Operand<i32>,
137 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
138 let PrintMethod = "printThumbAddrModeS2Operand";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
142 // t_addrmode_s1 := reg + reg
145 def t_addrmode_s1 : Operand<i32>,
146 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
147 let PrintMethod = "printThumbAddrModeS1Operand";
148 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
151 // t_addrmode_sp := sp + imm8 * 4
153 def t_addrmode_sp : Operand<i32>,
154 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
155 let PrintMethod = "printThumbAddrModeSPOperand";
156 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
159 //===----------------------------------------------------------------------===//
160 // Miscellaneous Instructions.
163 let Defs = [SP], Uses = [SP] in {
164 def tADJCALLSTACKUP :
165 PseudoInst<(outs), (ins i32imm:$amt),
166 "@ tADJCALLSTACKUP $amt",
167 [(ARMcallseq_end imm:$amt)]>, Requires<[IsThumb]>;
169 def tADJCALLSTACKDOWN :
170 PseudoInst<(outs), (ins i32imm:$amt),
171 "@ tADJCALLSTACKDOWN $amt",
172 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb]>;
175 let isNotDuplicable = 1 in
176 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
177 "$cp:\n\tadd $dst, pc",
178 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
180 //===----------------------------------------------------------------------===//
181 // Control Flow Instructions.
184 let isReturn = 1, isTerminator = 1 in {
185 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
186 // Alternative return instruction used by vararg functions.
187 def tBX_RET_vararg : TI<(outs), (ins GPR:$target), "bx $target", []>;
190 // FIXME: remove when we have a way to marking a MI with these properties.
191 let isLoad = 1, isReturn = 1, isTerminator = 1 in
192 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
196 Defs = [R0, R1, R2, R3, LR,
197 D0, D1, D2, D3, D4, D5, D6, D7] in {
198 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
200 [(ARMtcall tglobaladdr:$func)]>;
202 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
204 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
205 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops),
207 [(ARMtcall GPR:$func)]>, Requires<[HasV5T]>;
209 def tBX : TIx2<(outs), (ins GPR:$func, variable_ops),
210 "cpy lr, pc\n\tbx $func",
211 [(ARMcall_nolink GPR:$func)]>;
214 let isBranch = 1, isTerminator = 1 in {
215 let isBarrier = 1 in {
216 let isPredicable = 1 in
217 def tB : TI<(outs), (ins brtarget:$target), "b $target",
221 def tBfar : TIx2<(outs), (ins brtarget:$target), "bl $target\t@ far jump",[]>;
223 def tBR_JTr : TJTI<(outs),
224 (ins GPR:$target, jtblock_operand:$jt, i32imm:$id),
225 "cpy pc, $target \n\t.align\t2\n$jt",
226 [(ARMbrjt GPR:$target, tjumptable:$jt, imm:$id)]>;
230 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
231 // a two-value operand where a dag node expects two operands. :(
232 let isBranch = 1, isTerminator = 1 in
233 def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
234 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
236 //===----------------------------------------------------------------------===//
237 // Load Store Instructions.
241 def tLDR : TI4<(outs GPR:$dst), (ins t_addrmode_s4:$addr),
243 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
245 def tLDRB : TI1<(outs GPR:$dst), (ins t_addrmode_s1:$addr),
247 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
249 def tLDRH : TI2<(outs GPR:$dst), (ins t_addrmode_s2:$addr),
251 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
253 def tLDRSB : TI1<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
255 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
257 def tLDRSH : TI2<(outs GPR:$dst), (ins t_addrmode_rr:$addr),
259 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
261 def tLDRspi : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
263 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
265 // Special instruction for restore. It cannot clobber condition register
266 // when it's expanded by eliminateCallFramePseudoInstr().
267 def tRestore : TIs<(outs GPR:$dst), (ins t_addrmode_sp:$addr),
268 "ldr $dst, $addr", []>;
271 def tLDRpci : TIs<(outs GPR:$dst), (ins i32imm:$addr),
273 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
275 // Special LDR for loads from non-pc-relative constpools.
276 let isReMaterializable = 1 in
277 def tLDRcp : TIs<(outs GPR:$dst), (ins i32imm:$addr),
278 "ldr $dst, $addr", []>;
282 def tSTR : TI4<(outs), (ins GPR:$src, t_addrmode_s4:$addr),
284 [(store GPR:$src, t_addrmode_s4:$addr)]>;
286 def tSTRB : TI1<(outs), (ins GPR:$src, t_addrmode_s1:$addr),
288 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
290 def tSTRH : TI2<(outs), (ins GPR:$src, t_addrmode_s2:$addr),
292 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
294 def tSTRspi : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
296 [(store GPR:$src, t_addrmode_sp:$addr)]>;
298 // Special instruction for spill. It cannot clobber condition register
299 // when it's expanded by eliminateCallFramePseudoInstr().
300 def tSpill : TIs<(outs), (ins GPR:$src, t_addrmode_sp:$addr),
301 "str $src, $addr", []>;
304 //===----------------------------------------------------------------------===//
305 // Load / store multiple Instructions.
308 // TODO: A7-44: LDMIA - load multiple
311 def tPOP : TI<(outs reglist:$dst1, variable_ops), (ins),
315 def tPUSH : TI<(outs), (ins reglist:$src1, variable_ops),
318 //===----------------------------------------------------------------------===//
319 // Arithmetic Instructions.
323 def tADC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
325 [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
327 def tADDS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
328 "add $dst, $lhs, $rhs",
329 [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
332 def tADDi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
333 "add $dst, $lhs, $rhs",
334 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
336 def tADDi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
338 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
340 def tADDrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
341 "add $dst, $lhs, $rhs",
342 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
344 def tADDhirr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
345 "add $dst, $rhs", []>;
347 def tADDrPCi : TI<(outs GPR:$dst), (ins i32imm:$rhs),
348 "add $dst, pc, $rhs * 4", []>;
349 def tADDrSPi : TI<(outs GPR:$dst), (ins GPR:$sp, i32imm:$rhs),
350 "add $dst, $sp, $rhs * 4", []>;
351 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
352 "add $dst, $rhs * 4", []>;
354 def tAND : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
356 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
358 def tASRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
359 "asr $dst, $lhs, $rhs",
360 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
362 def tASRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
364 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
366 def tBIC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
368 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
371 def tCMN : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
373 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
375 def tCMPi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
377 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
379 def tCMPr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
381 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
383 def tTST : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
385 [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
387 def tCMNNZ : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
389 [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
391 def tCMPNZi8 : TI<(outs), (ins GPR:$lhs, i32imm:$rhs),
393 [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
395 def tCMPNZr : TI<(outs), (ins GPR:$lhs, GPR:$rhs),
397 [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
399 // TODO: A7-37: CMP(3) - cmp hi regs
401 def tEOR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
403 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
405 def tLSLri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
406 "lsl $dst, $lhs, $rhs",
407 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
409 def tLSLrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
411 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
413 def tLSRri : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
414 "lsr $dst, $lhs, $rhs",
415 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
417 def tLSRrr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
419 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
421 // FIXME: This is not rematerializable because mov changes the condition code.
422 def tMOVi8 : TI<(outs GPR:$dst), (ins i32imm:$src),
424 [(set GPR:$dst, imm0_255:$src)]>;
426 // TODO: A7-73: MOV(2) - mov setting flag.
429 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
430 // which is MOV(3). This also supports high registers.
431 def tMOVr : TI<(outs GPR:$dst), (ins GPR:$src),
432 "cpy $dst, $src", []>;
434 def tMUL : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
436 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
438 def tMVN : TI<(outs GPR:$dst), (ins GPR:$src),
440 [(set GPR:$dst, (not GPR:$src))]>;
442 def tNEG : TI<(outs GPR:$dst), (ins GPR:$src),
444 [(set GPR:$dst, (ineg GPR:$src))]>;
446 def tORR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
448 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
451 def tREV : TI<(outs GPR:$dst), (ins GPR:$src),
453 [(set GPR:$dst, (bswap GPR:$src))]>,
454 Requires<[IsThumb, HasV6]>;
456 def tREV16 : TI<(outs GPR:$dst), (ins GPR:$src),
459 (or (and (srl GPR:$src, 8), 0xFF),
460 (or (and (shl GPR:$src, 8), 0xFF00),
461 (or (and (srl GPR:$src, 8), 0xFF0000),
462 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
463 Requires<[IsThumb, HasV6]>;
465 def tREVSH : TI<(outs GPR:$dst), (ins GPR:$src),
469 (or (srl (and GPR:$src, 0xFFFF), 8),
470 (shl GPR:$src, 8)), i16))]>,
471 Requires<[IsThumb, HasV6]>;
473 def tROR : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
475 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
478 // Subtract with carry
479 def tSBC : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
481 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
483 def tSUBS : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
484 "sub $dst, $lhs, $rhs",
485 [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
488 // TODO: A7-96: STMIA - store multiple.
490 def tSUBi3 : TI<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
491 "sub $dst, $lhs, $rhs",
492 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
494 def tSUBi8 : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
496 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
498 def tSUBrr : TI<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
499 "sub $dst, $lhs, $rhs",
500 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
502 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
503 "sub $dst, $rhs * 4", []>;
505 def tSXTB : TI<(outs GPR:$dst), (ins GPR:$src),
507 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
508 Requires<[IsThumb, HasV6]>;
509 def tSXTH : TI<(outs GPR:$dst), (ins GPR:$src),
511 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
512 Requires<[IsThumb, HasV6]>;
515 def tUXTB : TI<(outs GPR:$dst), (ins GPR:$src),
517 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
518 Requires<[IsThumb, HasV6]>;
519 def tUXTH : TI<(outs GPR:$dst), (ins GPR:$src),
521 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
522 Requires<[IsThumb, HasV6]>;
525 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
526 // Expanded by the scheduler into a branch sequence.
527 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
529 PseudoInst<(outs GPR:$dst), (ins GPR:$false, GPR:$true, pred:$cc),
531 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
533 // tLEApcrel - Load a pc-relative address into a register without offending the
535 def tLEApcrel : TIx2<(outs GPR:$dst), (ins i32imm:$label),
536 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
537 "${:private}PCRELL${:uid}+4))\n"),
538 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
539 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
542 def tLEApcrelJT : TIx2<(outs GPR:$dst), (ins i32imm:$label, i32imm:$id),
543 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
544 "${:private}PCRELL${:uid}+4))\n"),
545 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
546 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
549 //===----------------------------------------------------------------------===//
553 // __aeabi_read_tp preserves the registers r1-r3.
556 def tTPsoft : TIx2<(outs), (ins),
557 "bl __aeabi_read_tp",
558 [(set R0, ARMthread_pointer)]>;
561 //===----------------------------------------------------------------------===//
562 // Non-Instruction Patterns
565 // ConstantPool, GlobalAddress
566 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
567 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
570 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
571 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
574 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
575 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
577 // Indirect calls to ARM routines
578 def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
580 // zextload i1 -> zextload i8
581 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
582 (tLDRB t_addrmode_s1:$addr)>;
584 // extload -> zextload
585 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
586 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
587 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
589 // truncstore i1 -> truncstore i8
590 def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
591 (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
593 // Large immediate handling.
596 def : ThumbPat<(i32 thumb_immshifted:$src),
597 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
598 (thumb_immshifted_shamt imm:$src))>;
600 def : ThumbPat<(i32 imm0_255_comp:$src),
601 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;