1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 def imm0_7_neg : PatLeaf<(i32 imm), [{
30 return (uint32_t)-N->getZExtValue() < 8;
33 def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; }
34 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
35 let ParserMatchClass = imm0_255_asmoperand;
37 def imm0_255_comp : PatLeaf<(i32 imm), [{
38 return ~((uint32_t)N->getZExtValue()) < 256;
41 def imm8_255 : ImmLeaf<i32, [{
42 return Imm >= 8 && Imm < 256;
44 def imm8_255_neg : PatLeaf<(i32 imm), [{
45 unsigned Val = -N->getZExtValue();
46 return Val >= 8 && Val < 256;
49 // Break imm's up into two pieces: an immediate + a left shift. This uses
50 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
51 // to get the val/shift pieces.
52 def thumb_immshifted : PatLeaf<(imm), [{
53 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
56 def thumb_immshifted_val : SDNodeXForm<imm, [{
57 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
58 return CurDAG->getTargetConstant(V, MVT::i32);
61 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
62 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
63 return CurDAG->getTargetConstant(V, MVT::i32);
66 // ADR instruction labels.
67 def t_adrlabel : Operand<i32> {
68 let EncoderMethod = "getThumbAdrLabelOpValue";
71 // Scaled 4 immediate.
72 def t_imm_s4 : Operand<i32> {
73 let PrintMethod = "printThumbS4ImmOperand";
74 let OperandType = "OPERAND_IMMEDIATE";
77 // Define Thumb specific addressing modes.
79 let OperandType = "OPERAND_PCREL" in {
80 def t_brtarget : Operand<OtherVT> {
81 let EncoderMethod = "getThumbBRTargetOpValue";
84 def t_bcctarget : Operand<i32> {
85 let EncoderMethod = "getThumbBCCTargetOpValue";
88 def t_cbtarget : Operand<i32> {
89 let EncoderMethod = "getThumbCBTargetOpValue";
92 def t_bltarget : Operand<i32> {
93 let EncoderMethod = "getThumbBLTargetOpValue";
96 def t_blxtarget : Operand<i32> {
97 let EncoderMethod = "getThumbBLXTargetOpValue";
101 def MemModeRegThumbAsmOperand : AsmOperandClass {
102 let Name = "MemModeRegThumb";
103 let SuperClasses = [];
106 def MemModeImmThumbAsmOperand : AsmOperandClass {
107 let Name = "MemModeImmThumb";
108 let SuperClasses = [];
111 // t_addrmode_rr := reg + reg
113 def t_addrmode_rr : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
115 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
116 let PrintMethod = "printThumbAddrModeRROperand";
117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
120 // t_addrmode_rrs := reg + reg
122 def t_addrmode_rrs1 : Operand<i32>,
123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125 let PrintMethod = "printThumbAddrModeRROperand";
126 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127 let ParserMatchClass = MemModeRegThumbAsmOperand;
129 def t_addrmode_rrs2 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132 let PrintMethod = "printThumbAddrModeRROperand";
133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
134 let ParserMatchClass = MemModeRegThumbAsmOperand;
136 def t_addrmode_rrs4 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
138 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139 let PrintMethod = "printThumbAddrModeRROperand";
140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141 let ParserMatchClass = MemModeRegThumbAsmOperand;
144 // t_addrmode_is4 := reg + imm5 * 4
146 def t_addrmode_is4 : Operand<i32>,
147 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
148 let EncoderMethod = "getAddrModeISOpValue";
149 let PrintMethod = "printThumbAddrModeImm5S4Operand";
150 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
151 let ParserMatchClass = MemModeImmThumbAsmOperand;
154 // t_addrmode_is2 := reg + imm5 * 2
156 def t_addrmode_is2 : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
158 let EncoderMethod = "getAddrModeISOpValue";
159 let PrintMethod = "printThumbAddrModeImm5S2Operand";
160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
161 let ParserMatchClass = MemModeImmThumbAsmOperand;
164 // t_addrmode_is1 := reg + imm5
166 def t_addrmode_is1 : Operand<i32>,
167 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
168 let EncoderMethod = "getAddrModeISOpValue";
169 let PrintMethod = "printThumbAddrModeImm5S1Operand";
170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171 let ParserMatchClass = MemModeImmThumbAsmOperand;
174 // t_addrmode_sp := sp + imm8 * 4
176 def t_addrmode_sp : Operand<i32>,
177 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
178 let EncoderMethod = "getAddrModeThumbSPOpValue";
179 let PrintMethod = "printThumbAddrModeSPOperand";
180 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
181 let ParserMatchClass = MemModeImmThumbAsmOperand;
184 // t_addrmode_pc := <label> => pc + imm8 * 4
186 def t_addrmode_pc : Operand<i32> {
187 let EncoderMethod = "getAddrModePCOpValue";
188 let ParserMatchClass = MemModeImmThumbAsmOperand;
191 //===----------------------------------------------------------------------===//
192 // Miscellaneous Instructions.
195 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
196 // from removing one half of the matched pairs. That breaks PEI, which assumes
197 // these will always be in pairs, and asserts if it finds otherwise. Better way?
198 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
199 def tADJCALLSTACKUP :
200 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
201 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
202 Requires<[IsThumb, IsThumb1Only]>;
204 def tADJCALLSTACKDOWN :
205 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
206 [(ARMcallseq_start imm:$amt)]>,
207 Requires<[IsThumb, IsThumb1Only]>;
210 // T1Disassembly - A simple class to make encoding some disassembly patterns
211 // easier and less verbose.
212 class T1Disassembly<bits<2> op1, bits<8> op2>
213 : T1Encoding<0b101111> {
218 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
219 [/* For disassembly only; pattern left blank */]>,
220 T1Disassembly<0b11, 0x00>; // A8.6.110
222 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
223 [/* For disassembly only; pattern left blank */]>,
224 T1Disassembly<0b11, 0x10>; // A8.6.410
226 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
227 [/* For disassembly only; pattern left blank */]>,
228 T1Disassembly<0b11, 0x20>; // A8.6.408
230 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
231 [/* For disassembly only; pattern left blank */]>,
232 T1Disassembly<0b11, 0x30>; // A8.6.409
234 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
235 [/* For disassembly only; pattern left blank */]>,
236 T1Disassembly<0b11, 0x40>; // A8.6.157
238 // The i32imm operand $val can be used by a debugger to store more information
239 // about the breakpoint.
240 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
241 [/* For disassembly only; pattern left blank */]>,
242 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
248 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
249 []>, T1Encoding<0b101101> {
252 let Inst{9-5} = 0b10010;
255 let Inst{2-0} = 0b000;
258 // Change Processor State is a system instruction -- for disassembly only.
259 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
260 NoItinerary, "cps$imod $iflags",
261 [/* For disassembly only; pattern left blank */]>,
269 let Inst{2-0} = iflags;
272 // For both thumb1 and thumb2.
273 let isNotDuplicable = 1, isCodeGenOnly = 1 in
274 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
275 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
276 T1Special<{0,0,?,?}> {
279 let Inst{6-3} = 0b1111; // Rm = pc
283 // PC relative add (ADR).
284 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
285 "add\t$dst, pc, $rhs", []>,
286 T1Encoding<{1,0,1,0,0,?}> {
290 let Inst{10-8} = dst;
294 // ADD <Rd>, sp, #<imm8>
295 // This is rematerializable, which is particularly useful for taking the
296 // address of locals.
297 let isReMaterializable = 1 in
298 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
299 "add\t$dst, $sp, $rhs", []>,
300 T1Encoding<{1,0,1,0,1,?}> {
304 let Inst{10-8} = dst;
308 // ADD sp, sp, #<imm7>
309 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
310 "add\t$dst, $rhs", []>,
311 T1Misc<{0,0,0,0,0,?,?}> {
317 // SUB sp, sp, #<imm7>
318 // FIXME: The encoding and the ASM string don't match up.
319 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
320 "sub\t$dst, $rhs", []>,
321 T1Misc<{0,0,0,0,1,?,?}> {
328 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
329 "add\t$dst, $rhs", []>,
330 T1Special<{0,0,?,?}> {
331 // A8.6.9 Encoding T1
333 let Inst{7} = dst{3};
334 let Inst{6-3} = 0b1101;
335 let Inst{2-0} = dst{2-0};
339 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
340 "add\t$dst, $rhs", []>,
341 T1Special<{0,0,?,?}> {
342 // A8.6.9 Encoding T2
346 let Inst{2-0} = 0b101;
349 //===----------------------------------------------------------------------===//
350 // Control Flow Instructions.
354 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
355 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
356 T1Special<{1,1,0,?}> {
360 let Inst{2-0} = 0b000;
364 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
365 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
366 [(ARMretflag)], (tBX LR, pred:$p)>;
368 // Alternative return instruction used by vararg functions.
369 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
371 (tBX GPR:$Rm, pred:$p)>;
374 // All calls clobber the non-callee saved registers. SP is marked as a use to
375 // prevent stack-pointer assignments that appear immediately before calls from
376 // potentially appearing dead.
378 // On non-Darwin platforms R9 is callee-saved.
379 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
381 // Also used for Thumb2
382 def tBL : TIx2<0b11110, 0b11, 1,
383 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
385 [(ARMtcall tglobaladdr:$func)]>,
386 Requires<[IsThumb, IsNotDarwin]> {
388 let Inst{25-16} = func{20-11};
391 let Inst{10-0} = func{10-0};
394 // ARMv5T and above, also used for Thumb2
395 def tBLXi : TIx2<0b11110, 0b11, 0,
396 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
398 [(ARMcall tglobaladdr:$func)]>,
399 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
401 let Inst{25-16} = func{20-11};
404 let Inst{10-1} = func{10-1};
405 let Inst{0} = 0; // func{0} is assumed zero
408 // Also used for Thumb2
409 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
411 [(ARMtcall GPR:$func)]>,
412 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
413 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
415 let Inst{6-3} = func;
416 let Inst{2-0} = 0b000;
420 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
422 [(ARMcall_nolink tGPR:$func)]>,
423 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
427 // On Darwin R9 is call-clobbered.
428 // R7 is marked as a use to prevent frame-pointer assignments from being
429 // moved above / below calls.
430 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
432 // Also used for Thumb2
433 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
434 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
435 (tBL pred:$p, t_bltarget:$func)>,
436 Requires<[IsThumb, IsDarwin]>;
438 // ARMv5T and above, also used for Thumb2
439 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
440 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
441 (tBLXi pred:$p, t_blxtarget:$func)>,
442 Requires<[IsThumb, HasV5T, IsDarwin]>;
444 // Also used for Thumb2
445 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
446 2, IIC_Br, [(ARMtcall GPR:$func)],
447 (tBLXr pred:$p, GPR:$func)>,
448 Requires<[IsThumb, HasV5T, IsDarwin]>;
451 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
453 [(ARMcall_nolink tGPR:$func)]>,
454 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
457 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
458 let isPredicable = 1 in
459 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
460 "b\t$target", [(br bb:$target)]>,
461 T1Encoding<{1,1,1,0,0,?}> {
463 let Inst{10-0} = target;
467 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
468 // the clobber of LR.
470 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
471 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
473 def tBR_JTr : tPseudoInst<(outs),
474 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
476 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
477 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
481 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
482 // a two-value operand where a dag node expects two operands. :(
483 let isBranch = 1, isTerminator = 1 in
484 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
486 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
487 T1BranchCond<{1,1,0,1}> {
491 let Inst{7-0} = target;
494 // Compare and branch on zero / non-zero
495 let isBranch = 1, isTerminator = 1 in {
496 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
497 "cbz\t$Rn, $target", []>,
498 T1Misc<{0,0,?,1,?,?,?}> {
502 let Inst{9} = target{5};
503 let Inst{7-3} = target{4-0};
507 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
508 "cbnz\t$cmp, $target", []>,
509 T1Misc<{1,0,?,1,?,?,?}> {
513 let Inst{9} = target{5};
514 let Inst{7-3} = target{4-0};
520 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
522 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
524 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
525 // on Darwin), so it's in ARMInstrThumb2.td.
526 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
528 (tBX GPR:$dst, (ops 14, zero_reg))>,
529 Requires<[IsThumb, IsDarwin]>;
531 // Non-Darwin versions (the difference is R9).
532 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
534 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
536 (tB t_brtarget:$dst)>,
537 Requires<[IsThumb, IsNotDarwin]>;
538 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
540 (tBX GPR:$dst, (ops 14, zero_reg))>,
541 Requires<[IsThumb, IsNotDarwin]>;
546 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
547 // A8.6.16 B: Encoding T1
548 // If Inst{11-8} == 0b1111 then SEE SVC
549 let isCall = 1, Uses = [SP] in
550 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
551 "svc", "\t$imm", []>, Encoding16 {
553 let Inst{15-12} = 0b1101;
554 let Inst{11-8} = 0b1111;
558 // The assembler uses 0xDEFE for a trap instruction.
559 let isBarrier = 1, isTerminator = 1 in
560 def tTRAP : TI<(outs), (ins), IIC_Br,
561 "trap", [(trap)]>, Encoding16 {
565 //===----------------------------------------------------------------------===//
566 // Load Store Instructions.
569 // Loads: reg/reg and reg/imm5
570 let canFoldAsLoad = 1, isReMaterializable = 1 in
571 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
572 Operand AddrMode_r, Operand AddrMode_i,
573 AddrMode am, InstrItinClass itin_r,
574 InstrItinClass itin_i, string asm,
577 T1pILdStEncode<reg_opc,
578 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
579 am, itin_r, asm, "\t$Rt, $addr",
580 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
582 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
583 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
584 am, itin_i, asm, "\t$Rt, $addr",
585 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
587 // Stores: reg/reg and reg/imm5
588 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
589 Operand AddrMode_r, Operand AddrMode_i,
590 AddrMode am, InstrItinClass itin_r,
591 InstrItinClass itin_i, string asm,
594 T1pILdStEncode<reg_opc,
595 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
596 am, itin_r, asm, "\t$Rt, $addr",
597 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
599 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
600 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
601 am, itin_i, asm, "\t$Rt, $addr",
602 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
606 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
607 t_addrmode_is4, AddrModeT1_4,
608 IIC_iLoad_r, IIC_iLoad_i, "ldr",
609 UnOpFrag<(load node:$Src)>>;
612 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
613 t_addrmode_is1, AddrModeT1_1,
614 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
615 UnOpFrag<(zextloadi8 node:$Src)>>;
618 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
619 t_addrmode_is2, AddrModeT1_2,
620 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
621 UnOpFrag<(zextloadi16 node:$Src)>>;
623 let AddedComplexity = 10 in
624 def tLDRSB : // A8.6.80
625 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
626 AddrModeT1_1, IIC_iLoad_bh_r,
627 "ldrsb", "\t$dst, $addr",
628 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
630 let AddedComplexity = 10 in
631 def tLDRSH : // A8.6.84
632 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
633 AddrModeT1_2, IIC_iLoad_bh_r,
634 "ldrsh", "\t$dst, $addr",
635 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
637 let canFoldAsLoad = 1 in
638 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
639 "ldr", "\t$Rt, $addr",
640 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
645 let Inst{7-0} = addr;
649 // FIXME: Use ldr.n to work around a Darwin assembler bug.
650 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
651 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
652 "ldr", ".n\t$Rt, $addr",
653 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
654 T1Encoding<{0,1,0,0,1,?}> {
659 let Inst{7-0} = addr;
662 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
663 // For disassembly use only.
664 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
665 "ldr", "\t$Rt, $addr",
666 [/* disassembly only */]>,
667 T1Encoding<{0,1,0,0,1,?}> {
672 let Inst{7-0} = addr;
675 // A8.6.194 & A8.6.192
676 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
677 t_addrmode_is4, AddrModeT1_4,
678 IIC_iStore_r, IIC_iStore_i, "str",
679 BinOpFrag<(store node:$LHS, node:$RHS)>>;
681 // A8.6.197 & A8.6.195
682 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
683 t_addrmode_is1, AddrModeT1_1,
684 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
685 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
687 // A8.6.207 & A8.6.205
688 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
689 t_addrmode_is2, AddrModeT1_2,
690 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
691 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
694 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
695 "str", "\t$Rt, $addr",
696 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
701 let Inst{7-0} = addr;
704 //===----------------------------------------------------------------------===//
705 // Load / store multiple Instructions.
708 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
709 InstrItinClass itin_upd, bits<6> T1Enc,
710 bit L_bit, string baseOpc> {
712 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
713 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
718 let Inst{7-0} = regs;
722 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
723 "$Rn = $wb", itin_upd>,
724 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
725 GPR:$Rn, pred:$p, reglist:$regs)> {
727 let OutOperandList = (outs GPR:$wb);
728 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
730 let isCodeGenOnly = 1;
732 list<Predicate> Predicates = [IsThumb];
736 // These require base address to be written back or one of the loaded regs.
737 let neverHasSideEffects = 1 in {
739 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
740 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
741 {1,1,0,0,1,?}, 1, "tLDM">;
743 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
744 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
745 {1,1,0,0,0,?}, 0, "tSTM">;
747 } // neverHasSideEffects
749 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
750 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
752 "pop${p}\t$regs", []>,
753 T1Misc<{1,1,0,?,?,?,?}> {
755 let Inst{8} = regs{15};
756 let Inst{7-0} = regs{7-0};
759 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
760 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
762 "push${p}\t$regs", []>,
763 T1Misc<{0,1,0,?,?,?,?}> {
765 let Inst{8} = regs{14};
766 let Inst{7-0} = regs{7-0};
769 //===----------------------------------------------------------------------===//
770 // Arithmetic Instructions.
773 // Helper classes for encoding T1pI patterns:
774 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
775 string opc, string asm, list<dag> pattern>
776 : T1pI<oops, iops, itin, opc, asm, pattern>,
777 T1DataProcessing<opA> {
783 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
784 string opc, string asm, list<dag> pattern>
785 : T1pI<oops, iops, itin, opc, asm, pattern>,
793 // Helper classes for encoding T1sI patterns:
794 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
795 string opc, string asm, list<dag> pattern>
796 : T1sI<oops, iops, itin, opc, asm, pattern>,
797 T1DataProcessing<opA> {
803 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
804 string opc, string asm, list<dag> pattern>
805 : T1sI<oops, iops, itin, opc, asm, pattern>,
814 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
815 string opc, string asm, list<dag> pattern>
816 : T1sI<oops, iops, itin, opc, asm, pattern>,
824 // Helper classes for encoding T1sIt patterns:
825 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
826 string opc, string asm, list<dag> pattern>
827 : T1sIt<oops, iops, itin, opc, asm, pattern>,
828 T1DataProcessing<opA> {
834 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
835 string opc, string asm, list<dag> pattern>
836 : T1sIt<oops, iops, itin, opc, asm, pattern>,
840 let Inst{10-8} = Rdn;
841 let Inst{7-0} = imm8;
844 // Add with carry register
845 let isCommutable = 1, Uses = [CPSR] in
847 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
848 "adc", "\t$Rdn, $Rm",
849 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
852 def tADDi3 : // A8.6.4 T1
853 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
855 "add", "\t$Rd, $Rm, $imm3",
856 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
858 let Inst{8-6} = imm3;
861 def tADDi8 : // A8.6.4 T2
862 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
864 "add", "\t$Rdn, $imm8",
865 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
868 let isCommutable = 1 in
869 def tADDrr : // A8.6.6 T1
870 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
872 "add", "\t$Rd, $Rn, $Rm",
873 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
875 let neverHasSideEffects = 1 in
876 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
877 "add", "\t$Rdn, $Rm", []>,
878 T1Special<{0,0,?,?}> {
882 let Inst{7} = Rdn{3};
884 let Inst{2-0} = Rdn{2-0};
888 let isCommutable = 1 in
889 def tAND : // A8.6.12
890 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
892 "and", "\t$Rdn, $Rm",
893 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
896 def tASRri : // A8.6.14
897 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
899 "asr", "\t$Rd, $Rm, $imm5",
900 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
902 let Inst{10-6} = imm5;
906 def tASRrr : // A8.6.15
907 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
909 "asr", "\t$Rdn, $Rm",
910 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
913 def tBIC : // A8.6.20
914 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
916 "bic", "\t$Rdn, $Rm",
917 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
920 let isCompare = 1, Defs = [CPSR] in {
921 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
922 // Compare-to-zero still works out, just not the relationals
923 //def tCMN : // A8.6.33
924 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
926 // "cmn", "\t$lhs, $rhs",
927 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
929 def tCMNz : // A8.6.33
930 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
933 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
935 } // isCompare = 1, Defs = [CPSR]
938 let isCompare = 1, Defs = [CPSR] in {
939 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
940 "cmp", "\t$Rn, $imm8",
941 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
942 T1General<{1,0,1,?,?}> {
947 let Inst{7-0} = imm8;
951 def tCMPr : // A8.6.36 T1
952 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
955 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
957 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
958 "cmp", "\t$Rn, $Rm", []>,
959 T1Special<{0,1,?,?}> {
965 let Inst{2-0} = Rn{2-0};
967 } // isCompare = 1, Defs = [CPSR]
971 let isCommutable = 1 in
972 def tEOR : // A8.6.45
973 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
975 "eor", "\t$Rdn, $Rm",
976 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
979 def tLSLri : // A8.6.88
980 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
982 "lsl", "\t$Rd, $Rm, $imm5",
983 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
985 let Inst{10-6} = imm5;
989 def tLSLrr : // A8.6.89
990 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
992 "lsl", "\t$Rdn, $Rm",
993 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
996 def tLSRri : // A8.6.90
997 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
999 "lsr", "\t$Rd, $Rm, $imm5",
1000 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1002 let Inst{10-6} = imm5;
1006 def tLSRrr : // A8.6.91
1007 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1009 "lsr", "\t$Rdn, $Rm",
1010 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1013 let isMoveImm = 1 in
1014 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1015 "mov", "\t$Rd, $imm8",
1016 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1017 T1General<{1,0,0,?,?}> {
1021 let Inst{10-8} = Rd;
1022 let Inst{7-0} = imm8;
1025 // A7-73: MOV(2) - mov setting flag.
1027 let neverHasSideEffects = 1 in {
1028 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1030 "mov", "\t$Rd, $Rm", "", []>,
1031 T1Special<{1,0,?,?}> {
1035 let Inst{7} = Rd{3};
1037 let Inst{2-0} = Rd{2-0};
1039 let Defs = [CPSR] in
1040 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1041 "movs\t$Rd, $Rm", []>, Encoding16 {
1045 let Inst{15-6} = 0b0000000000;
1049 } // neverHasSideEffects
1051 // Multiply register
1052 let isCommutable = 1 in
1053 def tMUL : // A8.6.105 T1
1054 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1056 "mul", "\t$Rdn, $Rm, $Rdn",
1057 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1059 // Move inverse register
1060 def tMVN : // A8.6.107
1061 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1062 "mvn", "\t$Rd, $Rn",
1063 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1065 // Bitwise or register
1066 let isCommutable = 1 in
1067 def tORR : // A8.6.114
1068 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1070 "orr", "\t$Rdn, $Rm",
1071 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1074 def tREV : // A8.6.134
1075 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1077 "rev", "\t$Rd, $Rm",
1078 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1079 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1081 def tREV16 : // A8.6.135
1082 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1084 "rev16", "\t$Rd, $Rm",
1085 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1086 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1088 def tREVSH : // A8.6.136
1089 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1091 "revsh", "\t$Rd, $Rm",
1092 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1093 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1095 // Rotate right register
1096 def tROR : // A8.6.139
1097 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1099 "ror", "\t$Rdn, $Rm",
1100 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1103 def tRSB : // A8.6.141
1104 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1106 "rsb", "\t$Rd, $Rn, #0",
1107 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1109 // Subtract with carry register
1110 let Uses = [CPSR] in
1111 def tSBC : // A8.6.151
1112 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1114 "sbc", "\t$Rdn, $Rm",
1115 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1117 // Subtract immediate
1118 def tSUBi3 : // A8.6.210 T1
1119 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1121 "sub", "\t$Rd, $Rm, $imm3",
1122 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1124 let Inst{8-6} = imm3;
1127 def tSUBi8 : // A8.6.210 T2
1128 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1130 "sub", "\t$Rdn, $imm8",
1131 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1133 // Subtract register
1134 def tSUBrr : // A8.6.212
1135 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1137 "sub", "\t$Rd, $Rn, $Rm",
1138 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1140 // TODO: A7-96: STMIA - store multiple.
1143 def tSXTB : // A8.6.222
1144 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1146 "sxtb", "\t$Rd, $Rm",
1147 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1148 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1150 // Sign-extend short
1151 def tSXTH : // A8.6.224
1152 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1154 "sxth", "\t$Rd, $Rm",
1155 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1156 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1159 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1160 def tTST : // A8.6.230
1161 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1162 "tst", "\t$Rn, $Rm",
1163 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1166 def tUXTB : // A8.6.262
1167 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1169 "uxtb", "\t$Rd, $Rm",
1170 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1171 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1173 // Zero-extend short
1174 def tUXTH : // A8.6.264
1175 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1177 "uxth", "\t$Rd, $Rm",
1178 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1179 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1181 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1182 // Expanded after instruction selection into a branch sequence.
1183 let usesCustomInserter = 1 in // Expanded after instruction selection.
1184 def tMOVCCr_pseudo :
1185 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1187 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1189 // tLEApcrel - Load a pc-relative address into a register without offending the
1192 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1193 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1194 T1Encoding<{1,0,1,0,0,?}> {
1197 let Inst{10-8} = Rd;
1198 let Inst{7-0} = addr;
1201 let neverHasSideEffects = 1, isReMaterializable = 1 in
1202 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1205 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1206 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1209 //===----------------------------------------------------------------------===//
1213 // __aeabi_read_tp preserves the registers r1-r3.
1214 // This is a pseudo inst so that we can get the encoding right,
1215 // complete with fixup for the aeabi_read_tp function.
1216 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1217 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1218 [(set R0, ARMthread_pointer)]>;
1220 //===----------------------------------------------------------------------===//
1221 // SJLJ Exception handling intrinsics
1224 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1225 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1226 // from some other function to get here, and we're using the stack frame for the
1227 // containing function to save/restore registers, we can't keep anything live in
1228 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1229 // tromped upon when we get here from a longjmp(). We force everything out of
1230 // registers except for our own input by listing the relevant registers in
1231 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1232 // preserve all of the callee-saved resgisters, which is exactly what we want.
1233 // $val is a scratch register for our use.
1234 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1235 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1236 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1237 AddrModeNone, 0, NoItinerary, "","",
1238 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1240 // FIXME: Non-Darwin version(s)
1241 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1242 Defs = [ R7, LR, SP ] in
1243 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1244 AddrModeNone, 0, IndexModeNone,
1245 Pseudo, NoItinerary, "", "",
1246 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1247 Requires<[IsThumb, IsDarwin]>;
1249 //===----------------------------------------------------------------------===//
1250 // Non-Instruction Patterns
1254 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1255 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1256 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1257 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1260 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1261 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1262 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1263 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1264 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1265 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1267 // Subtract with carry
1268 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1269 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1270 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1271 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1272 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1273 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1275 // ConstantPool, GlobalAddress
1276 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1277 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1280 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1281 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1284 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1285 Requires<[IsThumb, IsNotDarwin]>;
1286 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1287 Requires<[IsThumb, IsDarwin]>;
1289 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1290 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1291 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1292 Requires<[IsThumb, HasV5T, IsDarwin]>;
1294 // Indirect calls to ARM routines
1295 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1296 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1297 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1298 Requires<[IsThumb, HasV5T, IsDarwin]>;
1300 // zextload i1 -> zextload i8
1301 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1302 (tLDRBr t_addrmode_rrs1:$addr)>;
1303 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1304 (tLDRBi t_addrmode_is1:$addr)>;
1306 // extload -> zextload
1307 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1308 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1309 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1310 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1311 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1312 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1314 // If it's impossible to use [r,r] address mode for sextload, select to
1315 // ldr{b|h} + sxt{b|h} instead.
1316 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1317 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1318 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1319 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1320 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1321 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1322 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1323 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1324 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1325 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1326 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1327 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1329 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1330 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1331 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1332 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1333 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1334 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1335 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1336 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1338 // Large immediate handling.
1341 def : T1Pat<(i32 thumb_immshifted:$src),
1342 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1343 (thumb_immshifted_shamt imm:$src))>;
1345 def : T1Pat<(i32 imm0_255_comp:$src),
1346 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1348 // Pseudo instruction that combines ldr from constpool and add pc. This should
1349 // be expanded into two instructions late to allow if-conversion and
1351 let isReMaterializable = 1 in
1352 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1354 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1356 Requires<[IsThumb, IsThumb1Only]>;
1358 // Pseudo-instruction for merged POP and return.
1359 // FIXME: remove when we have a way to marking a MI with these properties.
1360 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1361 hasExtraDefRegAllocReq = 1 in
1362 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1364 (tPOP pred:$p, reglist:$regs)>;
1366 // Indirect branch using "mov pc, $Rm"
1367 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1368 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1369 2, IIC_Br, [(brind GPR:$Rm)],
1370 (tMOVr PC, GPR:$Rm, pred:$p)>;