1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 // For both thumb1 and thumb2.
131 let isNotDuplicable = 1 in
132 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp),
133 "$cp:\n\tadd $dst, pc",
134 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
137 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
138 "add $dst, pc, $rhs * 4", []>;
141 // FIXME: hard code sp?
142 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
143 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
146 // FIXME: hard code sp?
147 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
148 "add $dst, $rhs * 4", []>;
150 // FIXME: Make use of the following?
154 //===----------------------------------------------------------------------===//
155 // Control Flow Instructions.
158 let isReturn = 1, isTerminator = 1 in {
159 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
160 // Alternative return instruction used by vararg functions.
161 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
164 // FIXME: remove when we have a way to marking a MI with these properties.
165 let isReturn = 1, isTerminator = 1 in
166 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
170 Defs = [R0, R1, R2, R3, R12, LR,
171 D0, D1, D2, D3, D4, D5, D6, D7,
172 D16, D17, D18, D19, D20, D21, D22, D23,
173 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
174 // Also used for Thumb2
175 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
177 [(ARMtcall tglobaladdr:$func)]>,
178 Requires<[IsThumb, IsNotDarwin]>;
180 // ARMv5T and above, also used for Thumb2
181 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops),
183 [(ARMcall tglobaladdr:$func)]>,
184 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
186 // Also used for Thumb2
187 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops),
189 [(ARMtcall GPR:$func)]>,
190 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
193 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops),
194 "mov lr, pc\n\tbx $func",
195 [(ARMcall_nolink tGPR:$func)]>,
196 Requires<[IsThumb1Only, IsNotDarwin]>;
199 // On Darwin R9 is call-clobbered.
201 Defs = [R0, R1, R2, R3, R9, R12, LR,
202 D0, D1, D2, D3, D4, D5, D6, D7,
203 D16, D17, D18, D19, D20, D21, D22, D23,
204 D24, D25, D26, D27, D28, D29, D30, D31, CPSR] in {
205 // Also used for Thumb2
206 def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops),
208 [(ARMtcall tglobaladdr:$func)]>,
209 Requires<[IsThumb, IsDarwin]>;
211 // ARMv5T and above, also used for Thumb2
212 def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops),
214 [(ARMcall tglobaladdr:$func)]>,
215 Requires<[IsThumb, HasV5T, IsDarwin]>;
217 // Also used for Thumb2
218 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops),
220 [(ARMtcall GPR:$func)]>,
221 Requires<[IsThumb, HasV5T, IsDarwin]>;
224 def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops),
225 "mov lr, pc\n\tbx $func",
226 [(ARMcall_nolink tGPR:$func)]>,
227 Requires<[IsThumb1Only, IsDarwin]>;
230 let isBranch = 1, isTerminator = 1 in {
231 let isBarrier = 1 in {
232 let isPredicable = 1 in
233 def tB : T1I<(outs), (ins brtarget:$target), "b $target",
237 def tBfar : TIx2<(outs), (ins brtarget:$target),
238 "bl $target\t@ far jump",[]>;
240 def tBR_JTr : T1JTI<(outs),
241 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
242 "mov pc, $target\n\t.align\t2\n$jt",
243 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
247 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
248 // a two-value operand where a dag node expects two operands. :(
249 let isBranch = 1, isTerminator = 1 in
250 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
251 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
253 //===----------------------------------------------------------------------===//
254 // Load Store Instructions.
257 let canFoldAsLoad = 1 in
258 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
259 "ldr", " $dst, $addr",
260 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
262 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
263 "ldrb", " $dst, $addr",
264 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
266 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
267 "ldrh", " $dst, $addr",
268 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
270 let AddedComplexity = 10 in
271 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
272 "ldrsb", " $dst, $addr",
273 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
275 let AddedComplexity = 10 in
276 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
277 "ldrsh", " $dst, $addr",
278 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
280 let canFoldAsLoad = 1 in
281 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
282 "ldr", " $dst, $addr",
283 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
285 // Special instruction for restore. It cannot clobber condition register
286 // when it's expanded by eliminateCallFramePseudoInstr().
287 let canFoldAsLoad = 1, mayLoad = 1 in
288 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
289 "ldr", " $dst, $addr", []>;
292 let canFoldAsLoad = 1 in
293 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
294 "ldr", " $dst, $addr",
295 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
297 // Special LDR for loads from non-pc-relative constpools.
298 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
299 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
300 "ldr", " $dst, $addr", []>;
302 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
303 "str", " $src, $addr",
304 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
306 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
307 "strb", " $src, $addr",
308 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
310 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
311 "strh", " $src, $addr",
312 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
314 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
315 "str", " $src, $addr",
316 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
318 let mayStore = 1 in {
319 // Special instruction for spill. It cannot clobber condition register
320 // when it's expanded by eliminateCallFramePseudoInstr().
321 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
322 "str", " $src, $addr", []>;
325 //===----------------------------------------------------------------------===//
326 // Load / store multiple Instructions.
329 // TODO: A7-44: LDMIA - load multiple
330 // TODO: Allow these to be predicated
333 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
337 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
340 //===----------------------------------------------------------------------===//
341 // Arithmetic Instructions.
344 // Add with carry register
345 let isCommutable = 1, Uses = [CPSR] in
346 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
347 "adc", " $dst, $rhs",
348 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
351 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
352 "add", " $dst, $lhs, $rhs",
353 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
355 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
356 "add", " $dst, $rhs",
357 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
360 let isCommutable = 1 in
361 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
362 "add", " $dst, $lhs, $rhs",
363 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
365 let neverHasSideEffects = 1 in
366 def tADDhirr : T1pIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
367 "add", " $dst, $rhs @ addhirr", []>;
370 let isCommutable = 1 in
371 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
372 "and", " $dst, $rhs",
373 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
376 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
377 "asr", " $dst, $lhs, $rhs",
378 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
381 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
382 "asr", " $dst, $rhs",
383 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
386 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
387 "bic", " $dst, $rhs",
388 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
391 let Defs = [CPSR] in {
392 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
393 "cmn", " $lhs, $rhs",
394 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
395 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
396 "cmn", " $lhs, $rhs",
397 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
401 let Defs = [CPSR] in {
402 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
403 "cmp", " $lhs, $rhs",
404 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
405 def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
406 "cmp", " $lhs, $rhs",
407 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
412 let Defs = [CPSR] in {
413 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
414 "cmp", " $lhs, $rhs",
415 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
416 def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
417 "cmp", " $lhs, $rhs",
418 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
420 // TODO: Make use of the followings cmp hi regs
421 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
422 "cmp", " $lhs, $rhs", []>;
423 def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
424 "cmp", " $lhs, $rhs", []>;
429 let isCommutable = 1 in
430 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
431 "eor", " $dst, $rhs",
432 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
435 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
436 "lsl", " $dst, $lhs, $rhs",
437 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
440 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
441 "lsl", " $dst, $rhs",
442 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
445 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
446 "lsr", " $dst, $lhs, $rhs",
447 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
450 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
451 "lsr", " $dst, $rhs",
452 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
455 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src),
456 "mov", " $dst, $src",
457 [(set tGPR:$dst, imm0_255:$src)]>;
459 // TODO: A7-73: MOV(2) - mov setting flag.
462 let neverHasSideEffects = 1 in {
463 // FIXME: Make this predicable.
464 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
465 "mov $dst, $src", []>;
467 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
468 "movs $dst, $src", []>;
470 // FIXME: Make these predicable.
471 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src),
472 "mov $dst, $src\t@ hir2lor", []>;
473 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src),
474 "mov $dst, $src\t@ lor2hir", []>;
475 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src),
476 "mov $dst, $src\t@ hir2hir", []>;
477 } // neverHasSideEffects
480 let isCommutable = 1 in
481 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
482 "mul", " $dst, $rhs",
483 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
485 // move inverse register
486 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
487 "mvn", " $dst, $src",
488 [(set tGPR:$dst, (not tGPR:$src))]>;
490 // bitwise or register
491 let isCommutable = 1 in
492 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
493 "orr", " $dst, $rhs",
494 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
497 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
498 "rev", " $dst, $src",
499 [(set tGPR:$dst, (bswap tGPR:$src))]>,
500 Requires<[IsThumb1Only, HasV6]>;
502 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
503 "rev16", " $dst, $src",
505 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
506 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
507 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
508 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
509 Requires<[IsThumb1Only, HasV6]>;
511 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
512 "revsh", " $dst, $src",
515 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
516 (shl tGPR:$src, (i32 8))), i16))]>,
517 Requires<[IsThumb1Only, HasV6]>;
519 // rotate right register
520 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
521 "ror", " $dst, $rhs",
522 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
525 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
526 "rsb", " $dst, $src, #0",
527 [(set tGPR:$dst, (ineg tGPR:$src))]>;
529 // Subtract with carry register
531 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
532 "sbc", " $dst, $rhs",
533 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
535 // Subtract immediate
536 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
537 "sub", " $dst, $lhs, $rhs",
538 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
540 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
541 "sub", " $dst, $rhs",
542 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
545 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
546 "sub", " $dst, $lhs, $rhs",
547 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
549 // TODO: A7-96: STMIA - store multiple.
551 def tSUBspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
552 "sub $dst, $rhs * 4", []>;
555 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
556 "sxtb", " $dst, $src",
557 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
558 Requires<[IsThumb1Only, HasV6]>;
561 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
562 "sxth", " $dst, $src",
563 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
564 Requires<[IsThumb1Only, HasV6]>;
567 let isCommutable = 1, Defs = [CPSR] in
568 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
569 "tst", " $lhs, $rhs",
570 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
573 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
574 "uxtb", " $dst, $src",
575 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
576 Requires<[IsThumb1Only, HasV6]>;
579 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
580 "uxth", " $dst, $src",
581 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
582 Requires<[IsThumb1Only, HasV6]>;
585 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
586 // Expanded by the scheduler into a branch sequence.
587 // FIXME: Add actual movcc in IT blocks for Thumb2.
588 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
590 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
592 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
594 // tLEApcrel - Load a pc-relative address into a register without offending the
596 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label),
597 "adr $dst, #$label", []>;
599 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
600 "adr $dst, #${label}_${id:no_hash}", []>;
602 //===----------------------------------------------------------------------===//
606 // __aeabi_read_tp preserves the registers r1-r3.
609 def tTPsoft : TIx2<(outs), (ins),
610 "bl __aeabi_read_tp",
611 [(set R0, ARMthread_pointer)]>;
614 //===----------------------------------------------------------------------===//
615 // Non-Instruction Patterns
619 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
620 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
621 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
622 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
623 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
624 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
626 // Subtract with carry
627 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
628 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
629 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
630 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
631 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
632 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
634 // ConstantPool, GlobalAddress
635 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
636 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
639 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
640 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
643 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
644 Requires<[IsThumb, IsNotDarwin]>;
645 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
646 Requires<[IsThumb, IsDarwin]>;
648 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
649 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
650 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
651 Requires<[IsThumb, HasV5T, IsDarwin]>;
653 // Indirect calls to ARM routines
654 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
655 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
656 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
657 Requires<[IsThumb, HasV5T, IsDarwin]>;
659 // zextload i1 -> zextload i8
660 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
661 (tLDRB t_addrmode_s1:$addr)>;
663 // extload -> zextload
664 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
665 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
666 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
668 // If it's possible to use [r,r] address mode for sextload, select to
669 // ldr{b|h} + sxt{b|h} instead.
670 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
671 (tSXTB (tLDRB t_addrmode_s1:$addr))>;
672 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
673 (tSXTH (tLDRH t_addrmode_s2:$addr))>;
676 // Large immediate handling.
679 def : T1Pat<(i32 thumb_immshifted:$src),
680 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
681 (thumb_immshifted_shamt imm:$src))>;
683 def : T1Pat<(i32 imm0_255_comp:$src),
684 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;