1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_comp_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 def imm0_7_neg : PatLeaf<(i32 imm), [{
40 return (uint32_t)-N->getZExtValue() < 8;
43 def imm0_255_comp : PatLeaf<(i32 imm), [{
44 return ~((uint32_t)N->getZExtValue()) < 256;
47 def imm8_255 : ImmLeaf<i32, [{
48 return Imm >= 8 && Imm < 256;
50 def imm8_255_neg : PatLeaf<(i32 imm), [{
51 unsigned Val = -N->getZExtValue();
52 return Val >= 8 && Val < 256;
55 // Break imm's up into two pieces: an immediate + a left shift. This uses
56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
57 // to get the val/shift pieces.
58 def thumb_immshifted : PatLeaf<(imm), [{
59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
62 def thumb_immshifted_val : SDNodeXForm<imm, [{
63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
64 return CurDAG->getTargetConstant(V, MVT::i32);
67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
69 return CurDAG->getTargetConstant(V, MVT::i32);
72 // Scaled 4 immediate.
73 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
74 def t_imm0_1020s4 : Operand<i32> {
75 let PrintMethod = "printThumbS4ImmOperand";
76 let ParserMatchClass = t_imm0_1020s4_asmoperand;
77 let OperandType = "OPERAND_IMMEDIATE";
80 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
81 def t_imm0_508s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let ParserMatchClass = t_imm0_508s4_asmoperand;
84 let OperandType = "OPERAND_IMMEDIATE";
86 // Alias use only, so no printer is necessary.
87 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
88 def t_imm0_508s4_neg : Operand<i32> {
89 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
90 let OperandType = "OPERAND_IMMEDIATE";
93 // Define Thumb specific addressing modes.
95 // unsigned 8-bit, 2-scaled memory offset
96 class OperandUnsignedOffset_b8s2 : AsmOperandClass {
97 let Name = "UnsignedOffset_b8s2";
98 let PredicateMethod = "isUnsignedOffset<8, 2>";
101 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
103 // thumb style PC relative operand. signed, 8 bits magnitude,
104 // two bits shift. can be represented as either [pc, #imm], #imm,
105 // or relocatable expression...
106 def ThumbMemPC : AsmOperandClass {
107 let Name = "ThumbMemPC";
110 let OperandType = "OPERAND_PCREL" in {
111 def t_brtarget : Operand<OtherVT> {
112 let EncoderMethod = "getThumbBRTargetOpValue";
113 let DecoderMethod = "DecodeThumbBROperand";
116 // ADR instruction labels.
117 def t_adrlabel : Operand<i32> {
118 let EncoderMethod = "getThumbAdrLabelOpValue";
119 let PrintMethod = "printAdrLabelOperand<2>";
120 let ParserMatchClass = UnsignedOffset_b8s2;
123 def t_bcctarget : Operand<i32> {
124 let EncoderMethod = "getThumbBCCTargetOpValue";
125 let DecoderMethod = "DecodeThumbBCCTargetOperand";
128 def t_cbtarget : Operand<i32> {
129 let EncoderMethod = "getThumbCBTargetOpValue";
130 let DecoderMethod = "DecodeThumbCmpBROperand";
133 def t_bltarget : Operand<i32> {
134 let EncoderMethod = "getThumbBLTargetOpValue";
135 let DecoderMethod = "DecodeThumbBLTargetOperand";
138 def t_blxtarget : Operand<i32> {
139 let EncoderMethod = "getThumbBLXTargetOpValue";
140 let DecoderMethod = "DecodeThumbBLXOffset";
143 // t_addrmode_pc := <label> => pc + imm8 * 4
145 def t_addrmode_pc : Operand<i32> {
146 let EncoderMethod = "getAddrModePCOpValue";
147 let DecoderMethod = "DecodeThumbAddrModePC";
148 let PrintMethod = "printThumbLdrLabelOperand";
149 let ParserMatchClass = ThumbMemPC;
153 // t_addrmode_rr := reg + reg
155 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
156 def t_addrmode_rr : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
158 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
159 let PrintMethod = "printThumbAddrModeRROperand";
160 let DecoderMethod = "DecodeThumbAddrModeRR";
161 let ParserMatchClass = t_addrmode_rr_asm_operand;
162 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
165 // t_addrmode_rrs := reg + reg
167 // We use separate scaled versions because the Select* functions need
168 // to explicitly check for a matching constant and return false here so that
169 // the reg+imm forms will match instead. This is a horrible way to do that,
170 // as it forces tight coupling between the methods, but it's how selectiondag
172 def t_addrmode_rrs1 : Operand<i32>,
173 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
174 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
175 let PrintMethod = "printThumbAddrModeRROperand";
176 let DecoderMethod = "DecodeThumbAddrModeRR";
177 let ParserMatchClass = t_addrmode_rr_asm_operand;
178 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
180 def t_addrmode_rrs2 : Operand<i32>,
181 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
182 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
183 let DecoderMethod = "DecodeThumbAddrModeRR";
184 let PrintMethod = "printThumbAddrModeRROperand";
185 let ParserMatchClass = t_addrmode_rr_asm_operand;
186 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
188 def t_addrmode_rrs4 : Operand<i32>,
189 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
190 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
191 let DecoderMethod = "DecodeThumbAddrModeRR";
192 let PrintMethod = "printThumbAddrModeRROperand";
193 let ParserMatchClass = t_addrmode_rr_asm_operand;
194 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
197 // t_addrmode_is4 := reg + imm5 * 4
199 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
200 def t_addrmode_is4 : Operand<i32>,
201 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
202 let EncoderMethod = "getAddrModeISOpValue";
203 let DecoderMethod = "DecodeThumbAddrModeIS";
204 let PrintMethod = "printThumbAddrModeImm5S4Operand";
205 let ParserMatchClass = t_addrmode_is4_asm_operand;
206 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
209 // t_addrmode_is2 := reg + imm5 * 2
211 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
212 def t_addrmode_is2 : Operand<i32>,
213 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
214 let EncoderMethod = "getAddrModeISOpValue";
215 let DecoderMethod = "DecodeThumbAddrModeIS";
216 let PrintMethod = "printThumbAddrModeImm5S2Operand";
217 let ParserMatchClass = t_addrmode_is2_asm_operand;
218 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
221 // t_addrmode_is1 := reg + imm5
223 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
224 def t_addrmode_is1 : Operand<i32>,
225 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
226 let EncoderMethod = "getAddrModeISOpValue";
227 let DecoderMethod = "DecodeThumbAddrModeIS";
228 let PrintMethod = "printThumbAddrModeImm5S1Operand";
229 let ParserMatchClass = t_addrmode_is1_asm_operand;
230 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
233 // t_addrmode_sp := sp + imm8 * 4
235 // FIXME: This really shouldn't have an explicit SP operand at all. It should
236 // be implicit, just like in the instruction encoding itself.
237 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
238 def t_addrmode_sp : Operand<i32>,
239 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
240 let EncoderMethod = "getAddrModeThumbSPOpValue";
241 let DecoderMethod = "DecodeThumbAddrModeSP";
242 let PrintMethod = "printThumbAddrModeSPOperand";
243 let ParserMatchClass = t_addrmode_sp_asm_operand;
244 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
247 //===----------------------------------------------------------------------===//
248 // Miscellaneous Instructions.
251 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
252 // from removing one half of the matched pairs. That breaks PEI, which assumes
253 // these will always be in pairs, and asserts if it finds otherwise. Better way?
254 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
255 def tADJCALLSTACKUP :
256 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
257 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
258 Requires<[IsThumb, IsThumb1Only]>;
260 def tADJCALLSTACKDOWN :
261 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
262 [(ARMcallseq_start imm:$amt)]>,
263 Requires<[IsThumb, IsThumb1Only]>;
266 class T1SystemEncoding<bits<8> opc>
267 : T1Encoding<0b101111> {
268 let Inst{9-8} = 0b11;
272 def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm",
273 [(int_arm_hint imm0_15:$imm)]>,
274 T1SystemEncoding<0x00>,
275 Requires<[IsThumb, HasV6M]> {
280 class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> {
281 let Predicates = [IsThumb, HasV6M];
284 def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110
285 def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410
286 def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408
287 def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409
288 def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157
289 def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> {
290 let Predicates = [IsThumb2, HasV8];
293 // The imm operand $val can be used by a debugger to store more information
294 // about the breakpoint.
295 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
297 T1Encoding<0b101111> {
298 let Inst{9-8} = 0b10;
303 // default immediate for breakpoint mnemonic
304 def : InstAlias<"bkpt", (tBKPT 0)>, Requires<[IsThumb]>;
306 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
307 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
308 let Inst{9-6} = 0b1010;
313 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
314 []>, T1Encoding<0b101101>, Requires<[IsNotMClass]>, Deprecated<HasV8Ops> {
317 let Inst{9-5} = 0b10010;
320 let Inst{2-0} = 0b000;
323 // Change Processor State is a system instruction -- for disassembly only.
324 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
325 NoItinerary, "cps$imod $iflags", []>,
333 let Inst{2-0} = iflags;
334 let DecoderMethod = "DecodeThumbCPS";
337 // For both thumb1 and thumb2.
338 let isNotDuplicable = 1, isCodeGenOnly = 1 in
339 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
340 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
341 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
344 let Inst{6-3} = 0b1111; // Rm = pc
348 // ADD <Rd>, sp, #<imm8>
349 // FIXME: This should not be marked as having side effects, and it should be
350 // rematerializable. Clearing the side effect bit causes miscompilations,
351 // probably because the instruction can be moved around.
352 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
353 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
354 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
358 let Inst{10-8} = dst;
360 let DecoderMethod = "DecodeThumbAddSpecialReg";
363 // Thumb1 frame lowering is rather fragile, we hope to be able to use
364 // tADDrSPi, but we may need to insert a sequence that clobbers CPSR.
365 def tADDframe : PseudoInst<(outs tGPR:$dst), (ins i32imm:$base, i32imm:$offset),
367 Requires<[IsThumb, IsThumb1Only]> {
371 // ADD sp, sp, #<imm7>
372 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
373 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
374 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
378 let DecoderMethod = "DecodeThumbAddSPImm";
381 // SUB sp, sp, #<imm7>
382 // FIXME: The encoding and the ASM string don't match up.
383 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
384 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
385 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
389 let DecoderMethod = "DecodeThumbAddSPImm";
392 def : tInstAlias<"add${p} sp, $imm",
393 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
394 def : tInstAlias<"add${p} sp, sp, $imm",
395 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
397 // Can optionally specify SP as a three operand instruction.
398 def : tInstAlias<"add${p} sp, sp, $imm",
399 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
400 def : tInstAlias<"sub${p} sp, sp, $imm",
401 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
404 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
405 "add", "\t$Rdn, $sp, $Rn", []>,
406 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
407 // A8.6.9 Encoding T1
409 let Inst{7} = Rdn{3};
410 let Inst{6-3} = 0b1101;
411 let Inst{2-0} = Rdn{2-0};
412 let DecoderMethod = "DecodeThumbAddSPReg";
416 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
417 "add", "\t$Rdn, $Rm", []>,
418 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
419 // A8.6.9 Encoding T2
423 let Inst{2-0} = 0b101;
424 let DecoderMethod = "DecodeThumbAddSPReg";
427 //===----------------------------------------------------------------------===//
428 // Control Flow Instructions.
432 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
433 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
434 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
438 let Inst{2-0} = 0b000;
439 let Unpredictable{2-0} = 0b111;
443 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
444 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
445 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
447 // Alternative return instruction used by vararg functions.
448 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
450 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
453 // All calls clobber the non-callee saved registers. SP is marked as a use to
454 // prevent stack-pointer assignments that appear immediately before calls from
455 // potentially appearing dead.
457 Defs = [LR], Uses = [SP] in {
458 // Also used for Thumb2
459 def tBL : TIx2<0b11110, 0b11, 1,
460 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
462 [(ARMtcall tglobaladdr:$func)]>,
463 Requires<[IsThumb]>, Sched<[WriteBrL]> {
465 let Inst{26} = func{23};
466 let Inst{25-16} = func{20-11};
467 let Inst{13} = func{22};
468 let Inst{11} = func{21};
469 let Inst{10-0} = func{10-0};
472 // ARMv5T and above, also used for Thumb2
473 def tBLXi : TIx2<0b11110, 0b11, 0,
474 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
476 [(ARMcall tglobaladdr:$func)]>,
477 Requires<[IsThumb, HasV5T, IsNotMClass]>, Sched<[WriteBrL]> {
479 let Inst{26} = func{23};
480 let Inst{25-16} = func{20-11};
481 let Inst{13} = func{22};
482 let Inst{11} = func{21};
483 let Inst{10-1} = func{10-1};
484 let Inst{0} = 0; // func{0} is assumed zero
487 // Also used for Thumb2
488 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
490 [(ARMtcall GPR:$func)]>,
491 Requires<[IsThumb, HasV5T]>,
492 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
494 let Inst{6-3} = func;
495 let Inst{2-0} = 0b000;
499 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
501 [(ARMcall_nolink tGPR:$func)]>,
502 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
505 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
506 let isPredicable = 1 in
507 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
508 "b", "\t$target", [(br bb:$target)]>,
509 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
511 let Inst{10-0} = target;
512 let AsmMatchConverter = "cvtThumbBranches";
516 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
517 // the clobber of LR.
519 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
520 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
523 def tBR_JTr : tPseudoInst<(outs),
524 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
526 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
527 Sched<[WriteBrTbl]> {
528 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
532 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
533 // a two-value operand where a dag node expects two operands. :(
534 let isBranch = 1, isTerminator = 1 in
535 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
537 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
538 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
542 let Inst{7-0} = target;
543 let AsmMatchConverter = "cvtThumbBranches";
548 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
551 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
553 (tBX GPR:$dst, (ops 14, zero_reg))>,
554 Requires<[IsThumb]>, Sched<[WriteBr]>;
556 // tTAILJMPd: MachO version uses a Thumb2 branch (no Thumb1 tail calls
557 // on MachO), so it's in ARMInstrThumb2.td.
558 // Non-MachO version:
560 def tTAILJMPdND : tPseudoExpand<(outs),
561 (ins t_brtarget:$dst, pred:$p),
563 (tB t_brtarget:$dst, pred:$p)>,
564 Requires<[IsThumb, IsNotMachO]>, Sched<[WriteBr]>;
569 // A8.6.218 Supervisor Call (Software Interrupt)
570 // A8.6.16 B: Encoding T1
571 // If Inst{11-8} == 0b1111 then SEE SVC
572 let isCall = 1, Uses = [SP] in
573 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
574 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
576 let Inst{15-12} = 0b1101;
577 let Inst{11-8} = 0b1111;
581 // The assembler uses 0xDEFE for a trap instruction.
582 let isBarrier = 1, isTerminator = 1 in
583 def tTRAP : TI<(outs), (ins), IIC_Br,
584 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
588 //===----------------------------------------------------------------------===//
589 // Load Store Instructions.
592 // Loads: reg/reg and reg/imm5
593 let canFoldAsLoad = 1, isReMaterializable = 1 in
594 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
595 Operand AddrMode_r, Operand AddrMode_i,
596 AddrMode am, InstrItinClass itin_r,
597 InstrItinClass itin_i, string asm,
600 T1pILdStEncode<reg_opc,
601 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
602 am, itin_r, asm, "\t$Rt, $addr",
603 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
605 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
606 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
607 am, itin_i, asm, "\t$Rt, $addr",
608 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
610 // Stores: reg/reg and reg/imm5
611 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
612 Operand AddrMode_r, Operand AddrMode_i,
613 AddrMode am, InstrItinClass itin_r,
614 InstrItinClass itin_i, string asm,
617 T1pILdStEncode<reg_opc,
618 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
619 am, itin_r, asm, "\t$Rt, $addr",
620 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
622 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
623 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
624 am, itin_i, asm, "\t$Rt, $addr",
625 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
629 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
630 t_addrmode_is4, AddrModeT1_4,
631 IIC_iLoad_r, IIC_iLoad_i, "ldr",
632 UnOpFrag<(load node:$Src)>>;
635 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
636 t_addrmode_is1, AddrModeT1_1,
637 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
638 UnOpFrag<(zextloadi8 node:$Src)>>;
641 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
642 t_addrmode_is2, AddrModeT1_2,
643 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
644 UnOpFrag<(zextloadi16 node:$Src)>>;
646 let AddedComplexity = 10 in
647 def tLDRSB : // A8.6.80
648 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
649 AddrModeT1_1, IIC_iLoad_bh_r,
650 "ldrsb", "\t$Rt, $addr",
651 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
653 let AddedComplexity = 10 in
654 def tLDRSH : // A8.6.84
655 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
656 AddrModeT1_2, IIC_iLoad_bh_r,
657 "ldrsh", "\t$Rt, $addr",
658 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
660 let canFoldAsLoad = 1 in
661 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
662 "ldr", "\t$Rt, $addr",
663 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
668 let Inst{7-0} = addr;
671 let canFoldAsLoad = 1, isReMaterializable = 1 in
672 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
673 "ldr", "\t$Rt, $addr",
674 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
675 T1Encoding<{0,1,0,0,1,?}> {
680 let Inst{7-0} = addr;
683 // A8.6.194 & A8.6.192
684 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
685 t_addrmode_is4, AddrModeT1_4,
686 IIC_iStore_r, IIC_iStore_i, "str",
687 BinOpFrag<(store node:$LHS, node:$RHS)>>;
689 // A8.6.197 & A8.6.195
690 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
691 t_addrmode_is1, AddrModeT1_1,
692 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
693 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
695 // A8.6.207 & A8.6.205
696 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
697 t_addrmode_is2, AddrModeT1_2,
698 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
699 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
702 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
703 "str", "\t$Rt, $addr",
704 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
709 let Inst{7-0} = addr;
712 //===----------------------------------------------------------------------===//
713 // Load / store multiple Instructions.
716 // These require base address to be written back or one of the loaded regs.
717 let hasSideEffects = 0 in {
719 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
720 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
721 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
725 let Inst{7-0} = regs;
728 // Writeback version is just a pseudo, as there's no encoding difference.
729 // Writeback happens iff the base register is not in the destination register
732 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
733 "$Rn = $wb", IIC_iLoad_mu>,
734 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
736 let OutOperandList = (outs GPR:$wb);
737 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
739 let isCodeGenOnly = 1;
741 list<Predicate> Predicates = [IsThumb];
744 // There is no non-writeback version of STM for Thumb.
745 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
746 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
747 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
748 AddrModeNone, 2, IIC_iStore_mu,
749 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
750 T1Encoding<{1,1,0,0,0,?}> {
754 let Inst{7-0} = regs;
759 def : InstAlias<"ldm${p} $Rn!, $regs",
760 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
761 Requires<[IsThumb, IsThumb1Only]>;
763 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
764 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
766 "pop${p}\t$regs", []>,
767 T1Misc<{1,1,0,?,?,?,?}> {
769 let Inst{8} = regs{15};
770 let Inst{7-0} = regs{7-0};
773 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
774 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
776 "push${p}\t$regs", []>,
777 T1Misc<{0,1,0,?,?,?,?}> {
779 let Inst{8} = regs{14};
780 let Inst{7-0} = regs{7-0};
783 //===----------------------------------------------------------------------===//
784 // Arithmetic Instructions.
787 // Helper classes for encoding T1pI patterns:
788 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
789 string opc, string asm, list<dag> pattern>
790 : T1pI<oops, iops, itin, opc, asm, pattern>,
791 T1DataProcessing<opA> {
797 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
798 string opc, string asm, list<dag> pattern>
799 : T1pI<oops, iops, itin, opc, asm, pattern>,
807 // Helper classes for encoding T1sI patterns:
808 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : T1sI<oops, iops, itin, opc, asm, pattern>,
811 T1DataProcessing<opA> {
817 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
818 string opc, string asm, list<dag> pattern>
819 : T1sI<oops, iops, itin, opc, asm, pattern>,
828 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
829 string opc, string asm, list<dag> pattern>
830 : T1sI<oops, iops, itin, opc, asm, pattern>,
838 // Helper classes for encoding T1sIt patterns:
839 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
840 string opc, string asm, list<dag> pattern>
841 : T1sIt<oops, iops, itin, opc, asm, pattern>,
842 T1DataProcessing<opA> {
848 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
849 string opc, string asm, list<dag> pattern>
850 : T1sIt<oops, iops, itin, opc, asm, pattern>,
854 let Inst{10-8} = Rdn;
855 let Inst{7-0} = imm8;
858 // Add with carry register
859 let isCommutable = 1, Uses = [CPSR] in
861 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
862 "adc", "\t$Rdn, $Rm",
863 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
866 def tADDi3 : // A8.6.4 T1
867 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
869 "add", "\t$Rd, $Rm, $imm3",
870 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
873 let Inst{8-6} = imm3;
876 def tADDi8 : // A8.6.4 T2
877 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
878 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
879 "add", "\t$Rdn, $imm8",
880 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
884 let isCommutable = 1 in
885 def tADDrr : // A8.6.6 T1
886 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
888 "add", "\t$Rd, $Rn, $Rm",
889 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
891 let hasSideEffects = 0 in
892 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
893 "add", "\t$Rdn, $Rm", []>,
894 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
898 let Inst{7} = Rdn{3};
900 let Inst{2-0} = Rdn{2-0};
904 let isCommutable = 1 in
905 def tAND : // A8.6.12
906 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
908 "and", "\t$Rdn, $Rm",
909 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
912 def tASRri : // A8.6.14
913 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
915 "asr", "\t$Rd, $Rm, $imm5",
916 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
919 let Inst{10-6} = imm5;
923 def tASRrr : // A8.6.15
924 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
926 "asr", "\t$Rdn, $Rm",
927 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
930 def tBIC : // A8.6.20
931 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
933 "bic", "\t$Rdn, $Rm",
934 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
938 let isCompare = 1, Defs = [CPSR] in {
939 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
940 // Compare-to-zero still works out, just not the relationals
941 //def tCMN : // A8.6.33
942 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
944 // "cmn", "\t$lhs, $rhs",
945 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
947 def tCMNz : // A8.6.33
948 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
951 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
953 } // isCompare = 1, Defs = [CPSR]
956 let isCompare = 1, Defs = [CPSR] in {
957 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
958 "cmp", "\t$Rn, $imm8",
959 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
960 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
965 let Inst{7-0} = imm8;
969 def tCMPr : // A8.6.36 T1
970 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
973 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
975 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
976 "cmp", "\t$Rn, $Rm", []>,
977 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
983 let Inst{2-0} = Rn{2-0};
985 } // isCompare = 1, Defs = [CPSR]
989 let isCommutable = 1 in
990 def tEOR : // A8.6.45
991 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
993 "eor", "\t$Rdn, $Rm",
994 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
997 def tLSLri : // A8.6.88
998 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1000 "lsl", "\t$Rd, $Rm, $imm5",
1001 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
1004 let Inst{10-6} = imm5;
1008 def tLSLrr : // A8.6.89
1009 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1011 "lsl", "\t$Rdn, $Rm",
1012 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1015 def tLSRri : // A8.6.90
1016 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1018 "lsr", "\t$Rd, $Rm, $imm5",
1019 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1022 let Inst{10-6} = imm5;
1026 def tLSRrr : // A8.6.91
1027 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1029 "lsr", "\t$Rdn, $Rm",
1030 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1033 let isMoveImm = 1 in
1034 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1035 "mov", "\t$Rd, $imm8",
1036 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1037 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1041 let Inst{10-8} = Rd;
1042 let Inst{7-0} = imm8;
1044 // Because we have an explicit tMOVSr below, we need an alias to handle
1045 // the immediate "movs" form here. Blech.
1046 def : tInstAlias <"movs $Rdn, $imm",
1047 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1049 // A7-73: MOV(2) - mov setting flag.
1051 let hasSideEffects = 0 in {
1052 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1054 "mov", "\t$Rd, $Rm", "", []>,
1055 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1059 let Inst{7} = Rd{3};
1061 let Inst{2-0} = Rd{2-0};
1063 let Defs = [CPSR] in
1064 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1065 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1069 let Inst{15-6} = 0b0000000000;
1075 // Multiply register
1076 let isCommutable = 1 in
1077 def tMUL : // A8.6.105 T1
1078 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1079 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1080 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1081 T1DataProcessing<0b1101> {
1086 let AsmMatchConverter = "cvtThumbMultiply";
1089 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1092 // Move inverse register
1093 def tMVN : // A8.6.107
1094 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1095 "mvn", "\t$Rd, $Rn",
1096 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1098 // Bitwise or register
1099 let isCommutable = 1 in
1100 def tORR : // A8.6.114
1101 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1103 "orr", "\t$Rdn, $Rm",
1104 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1107 def tREV : // A8.6.134
1108 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1110 "rev", "\t$Rd, $Rm",
1111 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1112 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1114 def tREV16 : // A8.6.135
1115 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1117 "rev16", "\t$Rd, $Rm",
1118 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1119 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1121 def tREVSH : // A8.6.136
1122 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1124 "revsh", "\t$Rd, $Rm",
1125 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1126 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1128 // Rotate right register
1129 def tROR : // A8.6.139
1130 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1132 "ror", "\t$Rdn, $Rm",
1133 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1137 def tRSB : // A8.6.141
1138 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1140 "rsb", "\t$Rd, $Rn, #0",
1141 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1143 // Subtract with carry register
1144 let Uses = [CPSR] in
1145 def tSBC : // A8.6.151
1146 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1148 "sbc", "\t$Rdn, $Rm",
1149 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
1152 // Subtract immediate
1153 def tSUBi3 : // A8.6.210 T1
1154 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1156 "sub", "\t$Rd, $Rm, $imm3",
1157 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1160 let Inst{8-6} = imm3;
1163 def tSUBi8 : // A8.6.210 T2
1164 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1165 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1166 "sub", "\t$Rdn, $imm8",
1167 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1170 // Subtract register
1171 def tSUBrr : // A8.6.212
1172 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1174 "sub", "\t$Rd, $Rn, $Rm",
1175 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1179 def tSXTB : // A8.6.222
1180 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1182 "sxtb", "\t$Rd, $Rm",
1183 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1184 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1187 // Sign-extend short
1188 def tSXTH : // A8.6.224
1189 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1191 "sxth", "\t$Rd, $Rm",
1192 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1193 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1197 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1198 def tTST : // A8.6.230
1199 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1200 "tst", "\t$Rn, $Rm",
1201 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1204 // A8.8.247 UDF - Undefined (Encoding T1)
1205 def tUDF : TI<(outs), (ins imm0_255:$imm8), IIC_Br, "udf\t$imm8",
1206 [(int_arm_undefined imm0_255:$imm8)]>, Encoding16 {
1208 let Inst{15-12} = 0b1101;
1209 let Inst{11-8} = 0b1110;
1210 let Inst{7-0} = imm8;
1214 def tUXTB : // A8.6.262
1215 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1217 "uxtb", "\t$Rd, $Rm",
1218 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1219 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1222 // Zero-extend short
1223 def tUXTH : // A8.6.264
1224 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1226 "uxth", "\t$Rd, $Rm",
1227 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1228 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1230 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1231 // Expanded after instruction selection into a branch sequence.
1232 let usesCustomInserter = 1 in // Expanded after instruction selection.
1233 def tMOVCCr_pseudo :
1234 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p),
1236 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>;
1238 // tLEApcrel - Load a pc-relative address into a register without offending the
1241 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1242 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1243 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1246 let Inst{10-8} = Rd;
1247 let Inst{7-0} = addr;
1248 let DecoderMethod = "DecodeThumbAddSpecialReg";
1251 let hasSideEffects = 0, isReMaterializable = 1 in
1252 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1253 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1255 let hasSideEffects = 1 in
1256 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1257 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1258 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1260 //===----------------------------------------------------------------------===//
1264 // __aeabi_read_tp preserves the registers r1-r3.
1265 // This is a pseudo inst so that we can get the encoding right,
1266 // complete with fixup for the aeabi_read_tp function.
1267 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1268 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1269 [(set R0, ARMthread_pointer)]>,
1272 //===----------------------------------------------------------------------===//
1273 // SJLJ Exception handling intrinsics
1276 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1277 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1278 // from some other function to get here, and we're using the stack frame for the
1279 // containing function to save/restore registers, we can't keep anything live in
1280 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1281 // tromped upon when we get here from a longjmp(). We force everything out of
1282 // registers except for our own input by listing the relevant registers in
1283 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1284 // preserve all of the callee-saved resgisters, which is exactly what we want.
1285 // $val is a scratch register for our use.
1286 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1287 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1288 usesCustomInserter = 1 in
1289 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1290 AddrModeNone, 0, NoItinerary, "","",
1291 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1293 // FIXME: Non-IOS version(s)
1294 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1295 Defs = [ R7, LR, SP ] in
1296 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1297 AddrModeNone, 0, IndexModeNone,
1298 Pseudo, NoItinerary, "", "",
1299 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1300 Requires<[IsThumb]>;
1302 //===----------------------------------------------------------------------===//
1303 // Non-Instruction Patterns
1307 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1308 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1309 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1310 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1313 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1314 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1315 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1316 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1317 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1318 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1320 // Subtract with carry
1321 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1322 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1323 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1324 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1325 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1326 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1328 // Bswap 16 with load/store
1329 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_rrs2:$addr)), (i32 16)),
1330 (tREV16 (tLDRHr t_addrmode_rrs2:$addr))>;
1331 def : T1Pat<(srl (bswap (extloadi16 t_addrmode_is2:$addr)), (i32 16)),
1332 (tREV16 (tLDRHi t_addrmode_is2:$addr))>;
1333 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1334 t_addrmode_rrs2:$addr),
1335 (tSTRHr (tREV16 tGPR:$Rn), t_addrmode_rrs2:$addr)>;
1336 def : T1Pat<(truncstorei16 (srl (bswap tGPR:$Rn), (i32 16)),
1337 t_addrmode_is2:$addr),
1338 (tSTRHi(tREV16 tGPR:$Rn), t_addrmode_is2:$addr)>;
1341 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1344 def tLDRLIT_ga_pcrel : PseudoInst<(outs tGPR:$dst), (ins i32imm:$addr),
1347 (ARMWrapperPIC tglobaladdr:$addr))]>,
1348 Requires<[IsThumb, DontUseMovt]>;
1350 def tLDRLIT_ga_abs : PseudoInst<(outs tGPR:$dst), (ins i32imm:$src),
1353 (ARMWrapper tglobaladdr:$src))]>,
1354 Requires<[IsThumb, DontUseMovt]>;
1358 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1359 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1362 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1363 Requires<[IsThumb]>;
1365 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1366 Requires<[IsThumb, HasV5T, IsNotMClass]>;
1368 // Indirect calls to ARM routines
1369 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1370 Requires<[IsThumb, HasV5T]>;
1372 // zextload i1 -> zextload i8
1373 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1374 (tLDRBr t_addrmode_rrs1:$addr)>;
1375 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1376 (tLDRBi t_addrmode_is1:$addr)>;
1378 // extload -> zextload
1379 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1380 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1381 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1382 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1383 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1384 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1386 // If it's impossible to use [r,r] address mode for sextload, select to
1387 // ldr{b|h} + sxt{b|h} instead.
1388 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1389 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1390 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1391 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1392 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1393 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1394 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1395 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1396 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1397 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1398 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1399 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1401 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1402 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1403 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1404 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1405 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1406 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1407 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1408 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1410 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1411 (tLDRBi t_addrmode_is1:$src)>;
1412 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1413 (tLDRBr t_addrmode_rrs1:$src)>;
1414 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1415 (tLDRHi t_addrmode_is2:$src)>;
1416 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1417 (tLDRHr t_addrmode_rrs2:$src)>;
1418 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1419 (tLDRi t_addrmode_is4:$src)>;
1420 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1421 (tLDRr t_addrmode_rrs4:$src)>;
1422 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1423 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1424 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1425 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1426 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1427 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1428 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1429 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1430 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1431 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1432 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1433 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1435 // Large immediate handling.
1438 def : T1Pat<(i32 thumb_immshifted:$src),
1439 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1440 (thumb_immshifted_shamt imm:$src))>;
1442 def : T1Pat<(i32 imm0_255_comp:$src),
1443 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1445 // Pseudo instruction that combines ldr from constpool and add pc. This should
1446 // be expanded into two instructions late to allow if-conversion and
1448 let isReMaterializable = 1 in
1449 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1451 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1453 Requires<[IsThumb, IsThumb1Only]>;
1455 // Pseudo-instruction for merged POP and return.
1456 // FIXME: remove when we have a way to marking a MI with these properties.
1457 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1458 hasExtraDefRegAllocReq = 1 in
1459 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1461 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1463 // Indirect branch using "mov pc, $Rm"
1464 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1465 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1466 2, IIC_Br, [(brind GPR:$Rm)],
1467 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1471 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1472 // encoding is available on ARMv6K, but we don't differentiate that finely.
1473 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1476 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1477 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1478 // a useful extension and assembles to defined behaviour (the insn does
1480 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1481 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1483 // "neg" is and alias for "rsb rd, rn, #0"
1484 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1485 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1488 // Implied destination operand forms for shifts.
1489 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1490 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1491 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1492 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1493 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1494 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;