1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_comp_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 def imm0_7_neg : PatLeaf<(i32 imm), [{
40 return (uint32_t)-N->getZExtValue() < 8;
43 def imm0_255_comp : PatLeaf<(i32 imm), [{
44 return ~((uint32_t)N->getZExtValue()) < 256;
47 def imm8_255 : ImmLeaf<i32, [{
48 return Imm >= 8 && Imm < 256;
50 def imm8_255_neg : PatLeaf<(i32 imm), [{
51 unsigned Val = -N->getZExtValue();
52 return Val >= 8 && Val < 256;
55 // Break imm's up into two pieces: an immediate + a left shift. This uses
56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
57 // to get the val/shift pieces.
58 def thumb_immshifted : PatLeaf<(imm), [{
59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
62 def thumb_immshifted_val : SDNodeXForm<imm, [{
63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
64 return CurDAG->getTargetConstant(V, MVT::i32);
67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
69 return CurDAG->getTargetConstant(V, MVT::i32);
72 // Scaled 4 immediate.
73 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
74 def t_imm0_1020s4 : Operand<i32> {
75 let PrintMethod = "printThumbS4ImmOperand";
76 let ParserMatchClass = t_imm0_1020s4_asmoperand;
77 let OperandType = "OPERAND_IMMEDIATE";
80 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
81 def t_imm0_508s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let ParserMatchClass = t_imm0_508s4_asmoperand;
84 let OperandType = "OPERAND_IMMEDIATE";
86 // Alias use only, so no printer is necessary.
87 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
88 def t_imm0_508s4_neg : Operand<i32> {
89 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
90 let OperandType = "OPERAND_IMMEDIATE";
93 // Define Thumb specific addressing modes.
95 // unsigned 8-bit, 2-scaled memory offset
96 class OperandUnsignedOffset_b8s2 : AsmOperandClass {
97 let Name = "UnsignedOffset_b8s2";
98 let PredicateMethod = "isUnsignedOffset<8, 2>";
101 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
103 // thumb style PC relative operand. signed, 8 bits magnitude,
104 // two bits shift. can be represented as either [pc, #imm], #imm,
105 // or relocatable expression...
106 def ThumbMemPC : AsmOperandClass {
107 let Name = "ThumbMemPC";
110 let OperandType = "OPERAND_PCREL" in {
111 def t_brtarget : Operand<OtherVT> {
112 let EncoderMethod = "getThumbBRTargetOpValue";
113 let DecoderMethod = "DecodeThumbBROperand";
116 // ADR instruction labels.
117 def t_adrlabel : Operand<i32> {
118 let EncoderMethod = "getThumbAdrLabelOpValue";
119 let PrintMethod = "printAdrLabelOperand<2>";
120 let ParserMatchClass = UnsignedOffset_b8s2;
123 def t_bcctarget : Operand<i32> {
124 let EncoderMethod = "getThumbBCCTargetOpValue";
125 let DecoderMethod = "DecodeThumbBCCTargetOperand";
128 def t_cbtarget : Operand<i32> {
129 let EncoderMethod = "getThumbCBTargetOpValue";
130 let DecoderMethod = "DecodeThumbCmpBROperand";
133 def t_bltarget : Operand<i32> {
134 let EncoderMethod = "getThumbBLTargetOpValue";
135 let DecoderMethod = "DecodeThumbBLTargetOperand";
138 def t_blxtarget : Operand<i32> {
139 let EncoderMethod = "getThumbBLXTargetOpValue";
140 let DecoderMethod = "DecodeThumbBLXOffset";
143 // t_addrmode_pc := <label> => pc + imm8 * 4
145 def t_addrmode_pc : Operand<i32> {
146 let EncoderMethod = "getAddrModePCOpValue";
147 let DecoderMethod = "DecodeThumbAddrModePC";
148 let PrintMethod = "printThumbLdrLabelOperand";
149 let ParserMatchClass = ThumbMemPC;
153 // t_addrmode_rr := reg + reg
155 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
156 def t_addrmode_rr : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
158 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
159 let PrintMethod = "printThumbAddrModeRROperand";
160 let DecoderMethod = "DecodeThumbAddrModeRR";
161 let ParserMatchClass = t_addrmode_rr_asm_operand;
162 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
165 // t_addrmode_rrs := reg + reg
167 // We use separate scaled versions because the Select* functions need
168 // to explicitly check for a matching constant and return false here so that
169 // the reg+imm forms will match instead. This is a horrible way to do that,
170 // as it forces tight coupling between the methods, but it's how selectiondag
172 def t_addrmode_rrs1 : Operand<i32>,
173 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
174 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
175 let PrintMethod = "printThumbAddrModeRROperand";
176 let DecoderMethod = "DecodeThumbAddrModeRR";
177 let ParserMatchClass = t_addrmode_rr_asm_operand;
178 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
180 def t_addrmode_rrs2 : Operand<i32>,
181 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
182 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
183 let DecoderMethod = "DecodeThumbAddrModeRR";
184 let PrintMethod = "printThumbAddrModeRROperand";
185 let ParserMatchClass = t_addrmode_rr_asm_operand;
186 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
188 def t_addrmode_rrs4 : Operand<i32>,
189 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
190 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
191 let DecoderMethod = "DecodeThumbAddrModeRR";
192 let PrintMethod = "printThumbAddrModeRROperand";
193 let ParserMatchClass = t_addrmode_rr_asm_operand;
194 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
197 // t_addrmode_is4 := reg + imm5 * 4
199 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
200 def t_addrmode_is4 : Operand<i32>,
201 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
202 let EncoderMethod = "getAddrModeISOpValue";
203 let DecoderMethod = "DecodeThumbAddrModeIS";
204 let PrintMethod = "printThumbAddrModeImm5S4Operand";
205 let ParserMatchClass = t_addrmode_is4_asm_operand;
206 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
209 // t_addrmode_is2 := reg + imm5 * 2
211 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
212 def t_addrmode_is2 : Operand<i32>,
213 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
214 let EncoderMethod = "getAddrModeISOpValue";
215 let DecoderMethod = "DecodeThumbAddrModeIS";
216 let PrintMethod = "printThumbAddrModeImm5S2Operand";
217 let ParserMatchClass = t_addrmode_is2_asm_operand;
218 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
221 // t_addrmode_is1 := reg + imm5
223 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
224 def t_addrmode_is1 : Operand<i32>,
225 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
226 let EncoderMethod = "getAddrModeISOpValue";
227 let DecoderMethod = "DecodeThumbAddrModeIS";
228 let PrintMethod = "printThumbAddrModeImm5S1Operand";
229 let ParserMatchClass = t_addrmode_is1_asm_operand;
230 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
233 // t_addrmode_sp := sp + imm8 * 4
235 // FIXME: This really shouldn't have an explicit SP operand at all. It should
236 // be implicit, just like in the instruction encoding itself.
237 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
238 def t_addrmode_sp : Operand<i32>,
239 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
240 let EncoderMethod = "getAddrModeThumbSPOpValue";
241 let DecoderMethod = "DecodeThumbAddrModeSP";
242 let PrintMethod = "printThumbAddrModeSPOperand";
243 let ParserMatchClass = t_addrmode_sp_asm_operand;
244 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
247 //===----------------------------------------------------------------------===//
248 // Miscellaneous Instructions.
251 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
252 // from removing one half of the matched pairs. That breaks PEI, which assumes
253 // these will always be in pairs, and asserts if it finds otherwise. Better way?
254 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
255 def tADJCALLSTACKUP :
256 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
257 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
258 Requires<[IsThumb, IsThumb1Only]>;
260 def tADJCALLSTACKDOWN :
261 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
262 [(ARMcallseq_start imm:$amt)]>,
263 Requires<[IsThumb, IsThumb1Only]>;
266 class T1SystemEncoding<bits<8> opc>
267 : T1Encoding<0b101111> {
268 let Inst{9-8} = 0b11;
272 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
273 T1SystemEncoding<0x00>, // A8.6.110
274 Requires<[IsThumb2]>;
276 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
277 T1SystemEncoding<0x10>, // A8.6.410
278 Requires<[IsThumb2]>;
280 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
281 T1SystemEncoding<0x20>, // A8.6.408
282 Requires<[IsThumb2]>;
284 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
285 T1SystemEncoding<0x30>, // A8.6.409
286 Requires<[IsThumb2]>;
288 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
289 T1SystemEncoding<0x40>, // A8.6.157
290 Requires<[IsThumb2]>;
292 // The imm operand $val can be used by a debugger to store more information
293 // about the breakpoint.
294 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
296 T1Encoding<0b101111> {
297 let Inst{9-8} = 0b10;
303 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
304 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
305 let Inst{9-6} = 0b1010;
310 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
311 []>, T1Encoding<0b101101> {
314 let Inst{9-5} = 0b10010;
317 let Inst{2-0} = 0b000;
320 // Change Processor State is a system instruction -- for disassembly only.
321 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
322 NoItinerary, "cps$imod $iflags", []>,
330 let Inst{2-0} = iflags;
331 let DecoderMethod = "DecodeThumbCPS";
334 // For both thumb1 and thumb2.
335 let isNotDuplicable = 1, isCodeGenOnly = 1 in
336 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
337 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
338 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
341 let Inst{6-3} = 0b1111; // Rm = pc
345 // ADD <Rd>, sp, #<imm8>
346 // FIXME: This should not be marked as having side effects, and it should be
347 // rematerializable. Clearing the side effect bit causes miscompilations,
348 // probably because the instruction can be moved around.
349 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
350 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
351 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
355 let Inst{10-8} = dst;
357 let DecoderMethod = "DecodeThumbAddSpecialReg";
360 // ADD sp, sp, #<imm7>
361 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
362 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
363 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
367 let DecoderMethod = "DecodeThumbAddSPImm";
370 // SUB sp, sp, #<imm7>
371 // FIXME: The encoding and the ASM string don't match up.
372 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
373 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
374 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
378 let DecoderMethod = "DecodeThumbAddSPImm";
381 def : tInstAlias<"add${p} sp, $imm",
382 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
383 def : tInstAlias<"add${p} sp, sp, $imm",
384 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
386 // Can optionally specify SP as a three operand instruction.
387 def : tInstAlias<"add${p} sp, sp, $imm",
388 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
389 def : tInstAlias<"sub${p} sp, sp, $imm",
390 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
393 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
394 "add", "\t$Rdn, $sp, $Rn", []>,
395 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
396 // A8.6.9 Encoding T1
398 let Inst{7} = Rdn{3};
399 let Inst{6-3} = 0b1101;
400 let Inst{2-0} = Rdn{2-0};
401 let DecoderMethod = "DecodeThumbAddSPReg";
405 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
406 "add", "\t$Rdn, $Rm", []>,
407 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
408 // A8.6.9 Encoding T2
412 let Inst{2-0} = 0b101;
413 let DecoderMethod = "DecodeThumbAddSPReg";
416 //===----------------------------------------------------------------------===//
417 // Control Flow Instructions.
421 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
422 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
423 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
427 let Inst{2-0} = 0b000;
428 let Unpredictable{2-0} = 0b111;
432 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
433 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
434 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
436 // Alternative return instruction used by vararg functions.
437 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
439 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
442 // All calls clobber the non-callee saved registers. SP is marked as a use to
443 // prevent stack-pointer assignments that appear immediately before calls from
444 // potentially appearing dead.
446 Defs = [LR], Uses = [SP] in {
447 // Also used for Thumb2
448 def tBL : TIx2<0b11110, 0b11, 1,
449 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
451 [(ARMtcall tglobaladdr:$func)]>,
452 Requires<[IsThumb]>, Sched<[WriteBrL]> {
454 let Inst{26} = func{23};
455 let Inst{25-16} = func{20-11};
456 let Inst{13} = func{22};
457 let Inst{11} = func{21};
458 let Inst{10-0} = func{10-0};
461 // ARMv5T and above, also used for Thumb2
462 def tBLXi : TIx2<0b11110, 0b11, 0,
463 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
465 [(ARMcall tglobaladdr:$func)]>,
466 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> {
468 let Inst{26} = func{23};
469 let Inst{25-16} = func{20-11};
470 let Inst{13} = func{22};
471 let Inst{11} = func{21};
472 let Inst{10-1} = func{10-1};
473 let Inst{0} = 0; // func{0} is assumed zero
476 // Also used for Thumb2
477 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
479 [(ARMtcall GPR:$func)]>,
480 Requires<[IsThumb, HasV5T]>,
481 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
483 let Inst{6-3} = func;
484 let Inst{2-0} = 0b000;
488 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
490 [(ARMcall_nolink tGPR:$func)]>,
491 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
494 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
495 let isPredicable = 1 in
496 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
497 "b", "\t$target", [(br bb:$target)]>,
498 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
500 let Inst{10-0} = target;
501 let AsmMatchConverter = "cvtThumbBranches";
505 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
506 // the clobber of LR.
508 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
509 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
512 def tBR_JTr : tPseudoInst<(outs),
513 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
515 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
516 Sched<[WriteBrTbl]> {
517 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
521 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
522 // a two-value operand where a dag node expects two operands. :(
523 let isBranch = 1, isTerminator = 1 in
524 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
526 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
527 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
531 let Inst{7-0} = target;
532 let AsmMatchConverter = "cvtThumbBranches";
537 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
540 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
542 (tBX GPR:$dst, (ops 14, zero_reg))>,
543 Requires<[IsThumb]>, Sched<[WriteBr]>;
545 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
546 // on IOS), so it's in ARMInstrThumb2.td.
549 def tTAILJMPdND : tPseudoExpand<(outs),
550 (ins t_brtarget:$dst, pred:$p),
552 (tB t_brtarget:$dst, pred:$p)>,
553 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>;
558 // A8.6.218 Supervisor Call (Software Interrupt)
559 // A8.6.16 B: Encoding T1
560 // If Inst{11-8} == 0b1111 then SEE SVC
561 let isCall = 1, Uses = [SP] in
562 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
563 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
565 let Inst{15-12} = 0b1101;
566 let Inst{11-8} = 0b1111;
570 // The assembler uses 0xDEFE for a trap instruction.
571 let isBarrier = 1, isTerminator = 1 in
572 def tTRAP : TI<(outs), (ins), IIC_Br,
573 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
577 //===----------------------------------------------------------------------===//
578 // Load Store Instructions.
581 // Loads: reg/reg and reg/imm5
582 let canFoldAsLoad = 1, isReMaterializable = 1 in
583 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
584 Operand AddrMode_r, Operand AddrMode_i,
585 AddrMode am, InstrItinClass itin_r,
586 InstrItinClass itin_i, string asm,
589 T1pILdStEncode<reg_opc,
590 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
591 am, itin_r, asm, "\t$Rt, $addr",
592 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
594 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
595 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
596 am, itin_i, asm, "\t$Rt, $addr",
597 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
599 // Stores: reg/reg and reg/imm5
600 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
601 Operand AddrMode_r, Operand AddrMode_i,
602 AddrMode am, InstrItinClass itin_r,
603 InstrItinClass itin_i, string asm,
606 T1pILdStEncode<reg_opc,
607 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
608 am, itin_r, asm, "\t$Rt, $addr",
609 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
611 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
612 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
613 am, itin_i, asm, "\t$Rt, $addr",
614 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
618 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
619 t_addrmode_is4, AddrModeT1_4,
620 IIC_iLoad_r, IIC_iLoad_i, "ldr",
621 UnOpFrag<(load node:$Src)>>;
624 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
625 t_addrmode_is1, AddrModeT1_1,
626 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
627 UnOpFrag<(zextloadi8 node:$Src)>>;
630 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
631 t_addrmode_is2, AddrModeT1_2,
632 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
633 UnOpFrag<(zextloadi16 node:$Src)>>;
635 let AddedComplexity = 10 in
636 def tLDRSB : // A8.6.80
637 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
638 AddrModeT1_1, IIC_iLoad_bh_r,
639 "ldrsb", "\t$Rt, $addr",
640 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
642 let AddedComplexity = 10 in
643 def tLDRSH : // A8.6.84
644 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
645 AddrModeT1_2, IIC_iLoad_bh_r,
646 "ldrsh", "\t$Rt, $addr",
647 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
649 let canFoldAsLoad = 1 in
650 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
651 "ldr", "\t$Rt, $addr",
652 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
657 let Inst{7-0} = addr;
660 let canFoldAsLoad = 1, isReMaterializable = 1 in
661 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
662 "ldr", "\t$Rt, $addr",
663 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
664 T1Encoding<{0,1,0,0,1,?}> {
669 let Inst{7-0} = addr;
672 // A8.6.194 & A8.6.192
673 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
674 t_addrmode_is4, AddrModeT1_4,
675 IIC_iStore_r, IIC_iStore_i, "str",
676 BinOpFrag<(store node:$LHS, node:$RHS)>>;
678 // A8.6.197 & A8.6.195
679 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
680 t_addrmode_is1, AddrModeT1_1,
681 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
682 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
684 // A8.6.207 & A8.6.205
685 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
686 t_addrmode_is2, AddrModeT1_2,
687 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
688 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
691 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
692 "str", "\t$Rt, $addr",
693 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
698 let Inst{7-0} = addr;
701 //===----------------------------------------------------------------------===//
702 // Load / store multiple Instructions.
705 // These require base address to be written back or one of the loaded regs.
706 let neverHasSideEffects = 1 in {
708 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
709 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
710 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
714 let Inst{7-0} = regs;
717 // Writeback version is just a pseudo, as there's no encoding difference.
718 // Writeback happens iff the base register is not in the destination register
721 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
722 "$Rn = $wb", IIC_iLoad_mu>,
723 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
725 let OutOperandList = (outs GPR:$wb);
726 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
728 let isCodeGenOnly = 1;
730 list<Predicate> Predicates = [IsThumb];
733 // There is no non-writeback version of STM for Thumb.
734 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
735 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
736 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
737 AddrModeNone, 2, IIC_iStore_mu,
738 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
739 T1Encoding<{1,1,0,0,0,?}> {
743 let Inst{7-0} = regs;
746 } // neverHasSideEffects
748 def : InstAlias<"ldm${p} $Rn!, $regs",
749 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
750 Requires<[IsThumb, IsThumb1Only]>;
752 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
753 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
755 "pop${p}\t$regs", []>,
756 T1Misc<{1,1,0,?,?,?,?}> {
758 let Inst{8} = regs{15};
759 let Inst{7-0} = regs{7-0};
762 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
763 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
765 "push${p}\t$regs", []>,
766 T1Misc<{0,1,0,?,?,?,?}> {
768 let Inst{8} = regs{14};
769 let Inst{7-0} = regs{7-0};
772 //===----------------------------------------------------------------------===//
773 // Arithmetic Instructions.
776 // Helper classes for encoding T1pI patterns:
777 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
778 string opc, string asm, list<dag> pattern>
779 : T1pI<oops, iops, itin, opc, asm, pattern>,
780 T1DataProcessing<opA> {
786 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
787 string opc, string asm, list<dag> pattern>
788 : T1pI<oops, iops, itin, opc, asm, pattern>,
796 // Helper classes for encoding T1sI patterns:
797 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
798 string opc, string asm, list<dag> pattern>
799 : T1sI<oops, iops, itin, opc, asm, pattern>,
800 T1DataProcessing<opA> {
806 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
807 string opc, string asm, list<dag> pattern>
808 : T1sI<oops, iops, itin, opc, asm, pattern>,
817 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
818 string opc, string asm, list<dag> pattern>
819 : T1sI<oops, iops, itin, opc, asm, pattern>,
827 // Helper classes for encoding T1sIt patterns:
828 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
829 string opc, string asm, list<dag> pattern>
830 : T1sIt<oops, iops, itin, opc, asm, pattern>,
831 T1DataProcessing<opA> {
837 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
838 string opc, string asm, list<dag> pattern>
839 : T1sIt<oops, iops, itin, opc, asm, pattern>,
843 let Inst{10-8} = Rdn;
844 let Inst{7-0} = imm8;
847 // Add with carry register
848 let isCommutable = 1, Uses = [CPSR] in
850 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
851 "adc", "\t$Rdn, $Rm",
852 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
855 def tADDi3 : // A8.6.4 T1
856 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
858 "add", "\t$Rd, $Rm, $imm3",
859 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
862 let Inst{8-6} = imm3;
865 def tADDi8 : // A8.6.4 T2
866 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
867 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
868 "add", "\t$Rdn, $imm8",
869 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
873 let isCommutable = 1 in
874 def tADDrr : // A8.6.6 T1
875 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
877 "add", "\t$Rd, $Rn, $Rm",
878 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
880 let neverHasSideEffects = 1 in
881 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
882 "add", "\t$Rdn, $Rm", []>,
883 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
887 let Inst{7} = Rdn{3};
889 let Inst{2-0} = Rdn{2-0};
893 let isCommutable = 1 in
894 def tAND : // A8.6.12
895 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
897 "and", "\t$Rdn, $Rm",
898 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
901 def tASRri : // A8.6.14
902 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
904 "asr", "\t$Rd, $Rm, $imm5",
905 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
908 let Inst{10-6} = imm5;
912 def tASRrr : // A8.6.15
913 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
915 "asr", "\t$Rdn, $Rm",
916 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
919 def tBIC : // A8.6.20
920 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
922 "bic", "\t$Rdn, $Rm",
923 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
927 let isCompare = 1, Defs = [CPSR] in {
928 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
929 // Compare-to-zero still works out, just not the relationals
930 //def tCMN : // A8.6.33
931 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
933 // "cmn", "\t$lhs, $rhs",
934 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
936 def tCMNz : // A8.6.33
937 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
940 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
942 } // isCompare = 1, Defs = [CPSR]
945 let isCompare = 1, Defs = [CPSR] in {
946 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
947 "cmp", "\t$Rn, $imm8",
948 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
949 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
954 let Inst{7-0} = imm8;
958 def tCMPr : // A8.6.36 T1
959 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
962 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
964 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
965 "cmp", "\t$Rn, $Rm", []>,
966 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
972 let Inst{2-0} = Rn{2-0};
974 } // isCompare = 1, Defs = [CPSR]
978 let isCommutable = 1 in
979 def tEOR : // A8.6.45
980 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
982 "eor", "\t$Rdn, $Rm",
983 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
986 def tLSLri : // A8.6.88
987 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
989 "lsl", "\t$Rd, $Rm, $imm5",
990 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
993 let Inst{10-6} = imm5;
997 def tLSLrr : // A8.6.89
998 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1000 "lsl", "\t$Rdn, $Rm",
1001 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1004 def tLSRri : // A8.6.90
1005 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1007 "lsr", "\t$Rd, $Rm, $imm5",
1008 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1011 let Inst{10-6} = imm5;
1015 def tLSRrr : // A8.6.91
1016 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1018 "lsr", "\t$Rdn, $Rm",
1019 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1022 let isMoveImm = 1 in
1023 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1024 "mov", "\t$Rd, $imm8",
1025 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1026 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1030 let Inst{10-8} = Rd;
1031 let Inst{7-0} = imm8;
1033 // Because we have an explicit tMOVSr below, we need an alias to handle
1034 // the immediate "movs" form here. Blech.
1035 def : tInstAlias <"movs $Rdn, $imm",
1036 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1038 // A7-73: MOV(2) - mov setting flag.
1040 let neverHasSideEffects = 1 in {
1041 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1043 "mov", "\t$Rd, $Rm", "", []>,
1044 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1048 let Inst{7} = Rd{3};
1050 let Inst{2-0} = Rd{2-0};
1052 let Defs = [CPSR] in
1053 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1054 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1058 let Inst{15-6} = 0b0000000000;
1062 } // neverHasSideEffects
1064 // Multiply register
1065 let isCommutable = 1 in
1066 def tMUL : // A8.6.105 T1
1067 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1068 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1069 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1070 T1DataProcessing<0b1101> {
1075 let AsmMatchConverter = "cvtThumbMultiply";
1078 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1081 // Move inverse register
1082 def tMVN : // A8.6.107
1083 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1084 "mvn", "\t$Rd, $Rn",
1085 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1087 // Bitwise or register
1088 let isCommutable = 1 in
1089 def tORR : // A8.6.114
1090 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1092 "orr", "\t$Rdn, $Rm",
1093 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1096 def tREV : // A8.6.134
1097 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1099 "rev", "\t$Rd, $Rm",
1100 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1101 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1103 def tREV16 : // A8.6.135
1104 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1106 "rev16", "\t$Rd, $Rm",
1107 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1108 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1110 def tREVSH : // A8.6.136
1111 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1113 "revsh", "\t$Rd, $Rm",
1114 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1115 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1117 // Rotate right register
1118 def tROR : // A8.6.139
1119 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1121 "ror", "\t$Rdn, $Rm",
1122 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1126 def tRSB : // A8.6.141
1127 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1129 "rsb", "\t$Rd, $Rn, #0",
1130 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1132 // Subtract with carry register
1133 let Uses = [CPSR] in
1134 def tSBC : // A8.6.151
1135 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1137 "sbc", "\t$Rdn, $Rm",
1138 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
1141 // Subtract immediate
1142 def tSUBi3 : // A8.6.210 T1
1143 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1145 "sub", "\t$Rd, $Rm, $imm3",
1146 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1149 let Inst{8-6} = imm3;
1152 def tSUBi8 : // A8.6.210 T2
1153 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1154 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1155 "sub", "\t$Rdn, $imm8",
1156 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1159 // Subtract register
1160 def tSUBrr : // A8.6.212
1161 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1163 "sub", "\t$Rd, $Rn, $Rm",
1164 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1168 def tSXTB : // A8.6.222
1169 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1171 "sxtb", "\t$Rd, $Rm",
1172 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1173 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1176 // Sign-extend short
1177 def tSXTH : // A8.6.224
1178 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1180 "sxth", "\t$Rd, $Rm",
1181 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1182 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1186 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1187 def tTST : // A8.6.230
1188 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1189 "tst", "\t$Rn, $Rm",
1190 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1194 def tUXTB : // A8.6.262
1195 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1197 "uxtb", "\t$Rd, $Rm",
1198 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1199 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1202 // Zero-extend short
1203 def tUXTH : // A8.6.264
1204 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1206 "uxth", "\t$Rd, $Rm",
1207 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1208 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1210 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1211 // Expanded after instruction selection into a branch sequence.
1212 let usesCustomInserter = 1 in // Expanded after instruction selection.
1213 def tMOVCCr_pseudo :
1214 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p),
1216 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>;
1218 // tLEApcrel - Load a pc-relative address into a register without offending the
1221 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1222 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1223 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1226 let Inst{10-8} = Rd;
1227 let Inst{7-0} = addr;
1228 let DecoderMethod = "DecodeThumbAddSpecialReg";
1231 let neverHasSideEffects = 1, isReMaterializable = 1 in
1232 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1233 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1235 let hasSideEffects = 1 in
1236 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1237 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1238 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1240 //===----------------------------------------------------------------------===//
1244 // __aeabi_read_tp preserves the registers r1-r3.
1245 // This is a pseudo inst so that we can get the encoding right,
1246 // complete with fixup for the aeabi_read_tp function.
1247 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1248 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1249 [(set R0, ARMthread_pointer)]>,
1252 //===----------------------------------------------------------------------===//
1253 // SJLJ Exception handling intrinsics
1256 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1257 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1258 // from some other function to get here, and we're using the stack frame for the
1259 // containing function to save/restore registers, we can't keep anything live in
1260 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1261 // tromped upon when we get here from a longjmp(). We force everything out of
1262 // registers except for our own input by listing the relevant registers in
1263 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1264 // preserve all of the callee-saved resgisters, which is exactly what we want.
1265 // $val is a scratch register for our use.
1266 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1267 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1268 usesCustomInserter = 1 in
1269 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1270 AddrModeNone, 0, NoItinerary, "","",
1271 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1273 // FIXME: Non-IOS version(s)
1274 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1275 Defs = [ R7, LR, SP ] in
1276 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1277 AddrModeNone, 0, IndexModeNone,
1278 Pseudo, NoItinerary, "", "",
1279 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1280 Requires<[IsThumb, IsIOS]>;
1282 //===----------------------------------------------------------------------===//
1283 // Non-Instruction Patterns
1287 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1288 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1289 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1290 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1293 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1294 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1295 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1296 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1297 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1298 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1300 // Subtract with carry
1301 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1302 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1303 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1304 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1305 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1306 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1308 // ConstantPool, GlobalAddress
1309 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1310 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1313 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1314 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1317 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1318 Requires<[IsThumb]>;
1320 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1321 Requires<[IsThumb, HasV5T]>;
1323 // Indirect calls to ARM routines
1324 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1325 Requires<[IsThumb, HasV5T]>;
1327 // zextload i1 -> zextload i8
1328 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1329 (tLDRBr t_addrmode_rrs1:$addr)>;
1330 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1331 (tLDRBi t_addrmode_is1:$addr)>;
1333 // extload -> zextload
1334 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1335 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1336 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1337 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1338 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1339 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1341 // If it's impossible to use [r,r] address mode for sextload, select to
1342 // ldr{b|h} + sxt{b|h} instead.
1343 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1344 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1345 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1346 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1347 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1348 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1349 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1350 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1351 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1352 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1353 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1354 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1356 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1357 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1358 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1359 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1360 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1361 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1362 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1363 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1365 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1366 (tLDRBi t_addrmode_is1:$src)>;
1367 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1368 (tLDRBr t_addrmode_rrs1:$src)>;
1369 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1370 (tLDRHi t_addrmode_is2:$src)>;
1371 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1372 (tLDRHr t_addrmode_rrs2:$src)>;
1373 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1374 (tLDRi t_addrmode_is4:$src)>;
1375 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1376 (tLDRr t_addrmode_rrs4:$src)>;
1377 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1378 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1379 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1380 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1381 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1382 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1383 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1384 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1385 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1386 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1387 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1388 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1390 // Large immediate handling.
1393 def : T1Pat<(i32 thumb_immshifted:$src),
1394 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1395 (thumb_immshifted_shamt imm:$src))>;
1397 def : T1Pat<(i32 imm0_255_comp:$src),
1398 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1400 // Pseudo instruction that combines ldr from constpool and add pc. This should
1401 // be expanded into two instructions late to allow if-conversion and
1403 let isReMaterializable = 1 in
1404 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1406 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1408 Requires<[IsThumb, IsThumb1Only]>;
1410 // Pseudo-instruction for merged POP and return.
1411 // FIXME: remove when we have a way to marking a MI with these properties.
1412 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1413 hasExtraDefRegAllocReq = 1 in
1414 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1416 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1418 // Indirect branch using "mov pc, $Rm"
1419 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1420 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1421 2, IIC_Br, [(brind GPR:$Rm)],
1422 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1426 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1427 // encoding is available on ARMv6K, but we don't differentiate that finely.
1428 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1431 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1432 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1433 // a useful extension and assembles to defined behaviour (the insn does
1435 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1436 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1438 // "neg" is and alias for "rsb rd, rn, #0"
1439 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1440 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1443 // Implied destination operand forms for shifts.
1444 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1445 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1446 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1447 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1448 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1449 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;