1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
130 "@ tADJCALLSTACKUP $amt1",
131 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
133 def tADJCALLSTACKDOWN :
134 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
135 "@ tADJCALLSTACKDOWN $amt",
136 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
139 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
140 [/* For disassembly only; pattern left blank */]>,
141 T1Encoding<0b101111> {
142 let Inst{9-8} = 0b11;
143 let Inst{7-0} = 0b00000000;
146 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
147 [/* For disassembly only; pattern left blank */]>,
148 T1Encoding<0b101111> {
149 let Inst{9-8} = 0b11;
150 let Inst{7-0} = 0b00010000;
153 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
154 [/* For disassembly only; pattern left blank */]>,
155 T1Encoding<0b101111> {
156 let Inst{9-8} = 0b11;
157 let Inst{7-0} = 0b00100000;
160 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
161 [/* For disassembly only; pattern left blank */]>,
162 T1Encoding<0b101111> {
163 let Inst{9-8} = 0b11;
164 let Inst{7-0} = 0b00110000;
167 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
168 [/* For disassembly only; pattern left blank */]>,
169 T1Encoding<0b101111> {
170 let Inst{9-8} = 0b11;
171 let Inst{7-0} = 0b01000000;
174 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
175 [/* For disassembly only; pattern left blank */]>,
176 T1Encoding<0b101101> {
177 let Inst{9-5} = 0b10010;
181 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
182 [/* For disassembly only; pattern left blank */]>,
183 T1Encoding<0b101101> {
184 let Inst{9-5} = 0b10010;
188 // The i32imm operand $val can be used by a debugger to store more information
189 // about the breakpoint.
190 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
191 [/* For disassembly only; pattern left blank */]>,
192 T1Encoding<0b101111> {
193 let Inst{9-8} = 0b10;
196 // Change Processor State is a system instruction -- for disassembly only.
197 // The singleton $opt operand contains the following information:
198 // opt{4-0} = mode ==> don't care
199 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
200 // opt{8-6} = AIF from Inst{2-0}
201 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
203 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
204 // CPS which has more options.
205 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
206 [/* For disassembly only; pattern left blank */]>,
209 // For both thumb1 and thumb2.
210 let isNotDuplicable = 1 in
211 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
212 "\n$cp:\n\tadd\t$dst, pc",
213 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
214 T1Special<{0,0,?,?}> {
215 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
219 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
220 "add\t$dst, pc, $rhs", []>,
221 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
224 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
225 "add\t$dst, $sp, $rhs", []>,
226 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
229 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
230 "add\t$dst, $rhs", []>,
231 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
234 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
235 "sub\t$dst, $rhs", []>,
236 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
239 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
240 "add\t$dst, $rhs", []>,
241 T1Special<{0,0,?,?}> {
242 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
246 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
247 "add\t$dst, $rhs", []>,
248 T1Special<{0,0,?,?}> {
249 // A8.6.9 Encoding T2
251 let Inst{2-0} = 0b101;
254 // Pseudo instruction that will expand into a tSUBspi + a copy.
255 let usesCustomInserter = 1 in { // Expanded after instruction selection.
256 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs),
257 NoItinerary, "@ sub\t$dst, $rhs", []>;
259 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
260 NoItinerary, "@ add\t$dst, $rhs", []>;
263 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
264 NoItinerary, "@ and\t$dst, $rhs", []>;
265 } // usesCustomInserter
267 //===----------------------------------------------------------------------===//
268 // Control Flow Instructions.
271 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
272 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
273 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
274 let Inst{6-3} = 0b1110; // Rm = lr
276 // Alternative return instruction used by vararg functions.
277 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
278 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
282 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
283 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
285 T1Special<{1,0,1,?}> {
286 // <Rd> = Inst{7:2-0} = pc
287 let Inst{2-0} = 0b111;
291 // FIXME: remove when we have a way to marking a MI with these properties.
292 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
293 hasExtraDefRegAllocReq = 1 in
294 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br,
295 "pop${p}\t$dsts", []>,
296 T1Misc<{1,1,0,?,?,?,?}>;
299 Defs = [R0, R1, R2, R3, R12, LR,
300 D0, D1, D2, D3, D4, D5, D6, D7,
301 D16, D17, D18, D19, D20, D21, D22, D23,
302 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
303 // Also used for Thumb2
304 def tBL : TIx2<0b11110, 0b11, 1,
305 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
307 [(ARMtcall tglobaladdr:$func)]>,
308 Requires<[IsThumb, IsNotDarwin]>;
310 // ARMv5T and above, also used for Thumb2
311 def tBLXi : TIx2<0b11110, 0b11, 0,
312 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
314 [(ARMcall tglobaladdr:$func)]>,
315 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
317 // Also used for Thumb2
318 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
320 [(ARMtcall GPR:$func)]>,
321 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
322 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
325 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
326 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
327 "mov\tlr, pc\n\tbx\t$func",
328 [(ARMcall_nolink tGPR:$func)]>,
329 Requires<[IsThumb1Only, IsNotDarwin]>;
332 // On Darwin R9 is call-clobbered.
334 Defs = [R0, R1, R2, R3, R9, R12, LR,
335 D0, D1, D2, D3, D4, D5, D6, D7,
336 D16, D17, D18, D19, D20, D21, D22, D23,
337 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
338 // Also used for Thumb2
339 def tBLr9 : TIx2<0b11110, 0b11, 1,
340 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
342 [(ARMtcall tglobaladdr:$func)]>,
343 Requires<[IsThumb, IsDarwin]>;
345 // ARMv5T and above, also used for Thumb2
346 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
347 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
349 [(ARMcall tglobaladdr:$func)]>,
350 Requires<[IsThumb, HasV5T, IsDarwin]>;
352 // Also used for Thumb2
353 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
355 [(ARMtcall GPR:$func)]>,
356 Requires<[IsThumb, HasV5T, IsDarwin]>,
357 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
360 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
361 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
362 "mov\tlr, pc\n\tbx\t$func",
363 [(ARMcall_nolink tGPR:$func)]>,
364 Requires<[IsThumb1Only, IsDarwin]>;
367 let isBranch = 1, isTerminator = 1 in {
368 let isBarrier = 1 in {
369 let isPredicable = 1 in
370 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
371 "b\t$target", [(br bb:$target)]>,
372 T1Encoding<{1,1,1,0,0,?}>;
376 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
377 "bl\t$target\t@ far jump",[]>;
379 def tBR_JTr : T1JTI<(outs),
380 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
381 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
382 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
384 let Inst{15-7} = 0b010001101;
385 let Inst{2-0} = 0b111;
390 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
391 // a two-value operand where a dag node expects two operands. :(
392 let isBranch = 1, isTerminator = 1 in
393 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
395 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
396 T1Encoding<{1,1,0,1,?,?}>;
398 // Compare and branch on zero / non-zero
399 let isBranch = 1, isTerminator = 1 in {
400 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
401 "cbz\t$cmp, $target", []>,
402 T1Misc<{0,0,?,1,?,?,?}>;
404 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
405 "cbnz\t$cmp, $target", []>,
406 T1Misc<{1,0,?,1,?,?,?}>;
409 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
410 // A8.6.16 B: Encoding T1
411 // If Inst{11-8} == 0b1111 then SEE SVC
413 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
415 let Inst{15-12} = 0b1101;
416 let Inst{11-8} = 0b1111;
420 // A8.6.16 B: Encoding T1 -- for disassembly only
421 // If Inst{11-8} == 0b1110 then UNDEFINED
422 def tTRAP : T1I<(outs), (ins), IIC_Br, "trap", []>, Encoding16 {
423 let Inst{15-12} = 0b1101;
424 let Inst{11-8} = 0b1110;
427 //===----------------------------------------------------------------------===//
428 // Load Store Instructions.
431 let canFoldAsLoad = 1, isReMaterializable = 1 in
432 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
433 "ldr", "\t$dst, $addr",
434 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
436 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
437 "ldr", "\t$dst, $addr",
441 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
442 "ldrb", "\t$dst, $addr",
443 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
445 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
446 "ldrb", "\t$dst, $addr",
450 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
451 "ldrh", "\t$dst, $addr",
452 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
454 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
455 "ldrh", "\t$dst, $addr",
459 let AddedComplexity = 10 in
460 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
461 "ldrsb", "\t$dst, $addr",
462 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
465 let AddedComplexity = 10 in
466 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
467 "ldrsh", "\t$dst, $addr",
468 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
471 let canFoldAsLoad = 1 in
472 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
473 "ldr", "\t$dst, $addr",
474 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
477 // Special instruction for restore. It cannot clobber condition register
478 // when it's expanded by eliminateCallFramePseudoInstr().
479 let canFoldAsLoad = 1, mayLoad = 1 in
480 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
481 "ldr", "\t$dst, $addr", []>,
485 // FIXME: Use ldr.n to work around a Darwin assembler bug.
486 let canFoldAsLoad = 1, isReMaterializable = 1 in
487 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
488 "ldr", ".n\t$dst, $addr",
489 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
490 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
492 // Special LDR for loads from non-pc-relative constpools.
493 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
494 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
495 "ldr", "\t$dst, $addr", []>,
498 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
499 "str", "\t$src, $addr",
500 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
502 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
503 "str", "\t$src, $addr",
507 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
508 "strb", "\t$src, $addr",
509 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
511 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
512 "strb", "\t$src, $addr",
516 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
517 "strh", "\t$src, $addr",
518 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
520 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
521 "strh", "\t$src, $addr",
525 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
526 "str", "\t$src, $addr",
527 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
530 let mayStore = 1 in {
531 // Special instruction for spill. It cannot clobber condition register
532 // when it's expanded by eliminateCallFramePseudoInstr().
533 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
534 "str", "\t$src, $addr", []>,
538 //===----------------------------------------------------------------------===//
539 // Load / store multiple Instructions.
542 // These requires base address to be written back or one of the loaded regs.
543 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in {
544 def tLDM : T1I<(outs),
545 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
547 "ldm${addr:submode}${p}\t$addr, $dsts", []>,
548 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
550 def tLDM_UPD : T1It<(outs tGPR:$wb),
551 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops),
553 "ldm${addr:submode}${p}\t$addr!, $dsts",
554 "$addr.addr = $wb", []>,
555 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53
556 } // mayLoad, hasExtraDefRegAllocReq
558 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
559 def tSTM_UPD : T1It<(outs tGPR:$wb),
560 (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops),
562 "stm${addr:submode}${p}\t$addr!, $srcs",
563 "$addr.addr = $wb", []>,
564 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189
566 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
567 def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br,
568 "pop${p}\t$dsts", []>,
569 T1Misc<{1,1,0,?,?,?,?}>;
571 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
572 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops), IIC_Br,
573 "push${p}\t$srcs", []>,
574 T1Misc<{0,1,0,?,?,?,?}>;
576 //===----------------------------------------------------------------------===//
577 // Arithmetic Instructions.
580 // Add with carry register
581 let isCommutable = 1, Uses = [CPSR] in
582 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
583 "adc", "\t$dst, $rhs",
584 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
585 T1DataProcessing<0b0101>;
588 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
589 "add", "\t$dst, $lhs, $rhs",
590 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
593 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
594 "add", "\t$dst, $rhs",
595 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
596 T1General<{1,1,0,?,?}>;
599 let isCommutable = 1 in
600 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
601 "add", "\t$dst, $lhs, $rhs",
602 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
605 let neverHasSideEffects = 1 in
606 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
607 "add", "\t$dst, $rhs", []>,
608 T1Special<{0,0,?,?}>;
611 let isCommutable = 1 in
612 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
613 "and", "\t$dst, $rhs",
614 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
615 T1DataProcessing<0b0000>;
618 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
619 "asr", "\t$dst, $lhs, $rhs",
620 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
621 T1General<{0,1,0,?,?}>;
624 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
625 "asr", "\t$dst, $rhs",
626 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
627 T1DataProcessing<0b0100>;
630 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
631 "bic", "\t$dst, $rhs",
632 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
633 T1DataProcessing<0b1110>;
636 let Defs = [CPSR] in {
637 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
638 // Compare-to-zero still works out, just not the relationals
639 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
640 // "cmn", "\t$lhs, $rhs",
641 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
642 // T1DataProcessing<0b1011>;
643 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
644 "cmn", "\t$lhs, $rhs",
645 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
646 T1DataProcessing<0b1011>;
650 let Defs = [CPSR] in {
651 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
652 "cmp", "\t$lhs, $rhs",
653 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
654 T1General<{1,0,1,?,?}>;
655 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
656 "cmp", "\t$lhs, $rhs",
657 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
658 T1General<{1,0,1,?,?}>;
662 let Defs = [CPSR] in {
663 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
664 "cmp", "\t$lhs, $rhs",
665 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
666 T1DataProcessing<0b1010>;
667 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
668 "cmp", "\t$lhs, $rhs",
669 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
670 T1DataProcessing<0b1010>;
672 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
673 "cmp", "\t$lhs, $rhs", []>,
674 T1Special<{0,1,?,?}>;
675 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
676 "cmp", "\t$lhs, $rhs", []>,
677 T1Special<{0,1,?,?}>;
682 let isCommutable = 1 in
683 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
684 "eor", "\t$dst, $rhs",
685 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
686 T1DataProcessing<0b0001>;
689 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
690 "lsl", "\t$dst, $lhs, $rhs",
691 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
692 T1General<{0,0,0,?,?}>;
695 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
696 "lsl", "\t$dst, $rhs",
697 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
698 T1DataProcessing<0b0010>;
701 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
702 "lsr", "\t$dst, $lhs, $rhs",
703 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
704 T1General<{0,0,1,?,?}>;
707 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
708 "lsr", "\t$dst, $rhs",
709 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
710 T1DataProcessing<0b0011>;
713 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
714 "mov", "\t$dst, $src",
715 [(set tGPR:$dst, imm0_255:$src)]>,
716 T1General<{1,0,0,?,?}>;
718 // TODO: A7-73: MOV(2) - mov setting flag.
721 let neverHasSideEffects = 1 in {
722 // FIXME: Make this predicable.
723 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
724 "mov\t$dst, $src", []>,
727 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
728 "movs\t$dst, $src", []>, Encoding16 {
729 let Inst{15-6} = 0b0000000000;
732 // FIXME: Make these predicable.
733 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
734 "mov\t$dst, $src", []>,
735 T1Special<{1,0,0,?}>;
736 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
737 "mov\t$dst, $src", []>,
738 T1Special<{1,0,?,0}>;
739 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
740 "mov\t$dst, $src", []>,
741 T1Special<{1,0,?,?}>;
742 } // neverHasSideEffects
745 let isCommutable = 1 in
746 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
747 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
748 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
749 T1DataProcessing<0b1101>;
751 // move inverse register
752 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
753 "mvn", "\t$dst, $src",
754 [(set tGPR:$dst, (not tGPR:$src))]>,
755 T1DataProcessing<0b1111>;
757 // bitwise or register
758 let isCommutable = 1 in
759 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
760 "orr", "\t$dst, $rhs",
761 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
762 T1DataProcessing<0b1100>;
765 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
766 "rev", "\t$dst, $src",
767 [(set tGPR:$dst, (bswap tGPR:$src))]>,
768 Requires<[IsThumb1Only, HasV6]>,
769 T1Misc<{1,0,1,0,0,0,?}>;
771 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
772 "rev16", "\t$dst, $src",
774 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
775 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
776 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
777 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
778 Requires<[IsThumb1Only, HasV6]>,
779 T1Misc<{1,0,1,0,0,1,?}>;
781 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
782 "revsh", "\t$dst, $src",
785 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
786 (shl tGPR:$src, (i32 8))), i16))]>,
787 Requires<[IsThumb1Only, HasV6]>,
788 T1Misc<{1,0,1,0,1,1,?}>;
790 // rotate right register
791 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
792 "ror", "\t$dst, $rhs",
793 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
794 T1DataProcessing<0b0111>;
797 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
798 "rsb", "\t$dst, $src, #0",
799 [(set tGPR:$dst, (ineg tGPR:$src))]>,
800 T1DataProcessing<0b1001>;
802 // Subtract with carry register
804 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
805 "sbc", "\t$dst, $rhs",
806 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
807 T1DataProcessing<0b0110>;
809 // Subtract immediate
810 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
811 "sub", "\t$dst, $lhs, $rhs",
812 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
815 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
816 "sub", "\t$dst, $rhs",
817 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
818 T1General<{1,1,1,?,?}>;
821 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
822 "sub", "\t$dst, $lhs, $rhs",
823 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
826 // TODO: A7-96: STMIA - store multiple.
829 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
830 "sxtb", "\t$dst, $src",
831 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
832 Requires<[IsThumb1Only, HasV6]>,
833 T1Misc<{0,0,1,0,0,1,?}>;
836 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
837 "sxth", "\t$dst, $src",
838 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
839 Requires<[IsThumb1Only, HasV6]>,
840 T1Misc<{0,0,1,0,0,0,?}>;
843 let isCommutable = 1, Defs = [CPSR] in
844 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
845 "tst", "\t$lhs, $rhs",
846 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
847 T1DataProcessing<0b1000>;
850 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
851 "uxtb", "\t$dst, $src",
852 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
853 Requires<[IsThumb1Only, HasV6]>,
854 T1Misc<{0,0,1,0,1,1,?}>;
857 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
858 "uxth", "\t$dst, $src",
859 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
860 Requires<[IsThumb1Only, HasV6]>,
861 T1Misc<{0,0,1,0,1,0,?}>;
864 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
865 // Expanded after instruction selection into a branch sequence.
866 let usesCustomInserter = 1 in // Expanded after instruction selection.
868 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
869 NoItinerary, "@ tMOVCCr $cc",
870 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
873 // 16-bit movcc in IT blocks for Thumb2.
874 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
875 "mov", "\t$dst, $rhs", []>,
876 T1Special<{1,0,?,?}>;
878 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
879 "mov", "\t$dst, $rhs", []>,
880 T1General<{1,0,0,?,?}>;
882 // tLEApcrel - Load a pc-relative address into a register without offending the
884 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
885 "adr$p\t$dst, #$label", []>,
886 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
888 def tLEApcrelJT : T1I<(outs tGPR:$dst),
889 (ins i32imm:$label, nohash_imm:$id, pred:$p),
890 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
891 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
893 //===----------------------------------------------------------------------===//
897 // __aeabi_read_tp preserves the registers r1-r3.
900 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
901 "bl\t__aeabi_read_tp",
902 [(set R0, ARMthread_pointer)]>;
905 // SJLJ Exception handling intrinsics
906 // eh_sjlj_setjmp() is an instruction sequence to store the return
907 // address and save #0 in R0 for the non-longjmp case.
908 // Since by its nature we may be coming from some other function to get
909 // here, and we're using the stack frame for the containing function to
910 // save/restore registers, we can't keep anything live in regs across
911 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
912 // when we get here from a longjmp(). We force everthing out of registers
913 // except for our own input by listing the relevant registers in Defs. By
914 // doing so, we also cause the prologue/epilogue code to actively preserve
915 // all of the callee-saved resgisters, which is exactly what we want.
916 // The current SP is passed in $val, and we reuse the reg as a scratch.
918 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in {
919 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
920 AddrModeNone, SizeSpecial, NoItinerary,
921 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n"
924 "\tstr\t$val, [$src, #4]\n"
927 "\tmovs\tr0, #1\t@ end eh.setjmp\n"
929 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
931 //===----------------------------------------------------------------------===//
932 // Non-Instruction Patterns
936 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
937 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
938 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
939 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
940 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
941 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
943 // Subtract with carry
944 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
945 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
946 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
947 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
948 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
949 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
951 // ConstantPool, GlobalAddress
952 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
953 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
956 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
957 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
960 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
961 Requires<[IsThumb, IsNotDarwin]>;
962 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
963 Requires<[IsThumb, IsDarwin]>;
965 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
966 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
967 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
968 Requires<[IsThumb, HasV5T, IsDarwin]>;
970 // Indirect calls to ARM routines
971 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
972 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
973 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
974 Requires<[IsThumb, HasV5T, IsDarwin]>;
976 // zextload i1 -> zextload i8
977 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
978 (tLDRB t_addrmode_s1:$addr)>;
980 // extload -> zextload
981 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
982 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
983 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
985 // If it's impossible to use [r,r] address mode for sextload, select to
986 // ldr{b|h} + sxt{b|h} instead.
987 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
988 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
989 Requires<[IsThumb1Only, HasV6]>;
990 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
991 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
992 Requires<[IsThumb1Only, HasV6]>;
994 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
995 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
996 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
997 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
999 // Large immediate handling.
1002 def : T1Pat<(i32 thumb_immshifted:$src),
1003 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1004 (thumb_immshifted_shamt imm:$src))>;
1006 def : T1Pat<(i32 imm0_255_comp:$src),
1007 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1009 // Pseudo instruction that combines ldr from constpool and add pc. This should
1010 // be expanded into two instructions late to allow if-conversion and
1012 let isReMaterializable = 1 in
1013 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1014 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc",
1015 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1017 Requires<[IsThumb1Only]>;