1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr : Operand<i32>, ImmLeaf<i32, [{
23 return Imm > 0 && Imm <= 32;
25 let EncoderMethod = "getThumbSRImmOpValue";
26 let DecoderMethod = "DecodeThumbSRImm";
29 def imm_neg_XFORM : SDNodeXForm<imm, [{
30 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
32 def imm_comp_XFORM : SDNodeXForm<imm, [{
33 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
36 def imm0_7_neg : PatLeaf<(i32 imm), [{
37 return (uint32_t)-N->getZExtValue() < 8;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : ImmLeaf<i32, [{
45 return Imm >= 8 && Imm < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift. This uses
53 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54 // to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // ADR instruction labels.
70 def t_adrlabel : Operand<i32> {
71 let EncoderMethod = "getThumbAdrLabelOpValue";
74 // Scaled 4 immediate.
75 def t_imm_s4 : Operand<i32> {
76 let PrintMethod = "printThumbS4ImmOperand";
77 let OperandType = "OPERAND_IMMEDIATE";
80 // Define Thumb specific addressing modes.
82 let OperandType = "OPERAND_PCREL" in {
83 def t_brtarget : Operand<OtherVT> {
84 let EncoderMethod = "getThumbBRTargetOpValue";
85 let DecoderMethod = "DecodeThumbBROperand";
88 def t_bcctarget : Operand<i32> {
89 let EncoderMethod = "getThumbBCCTargetOpValue";
90 let DecoderMethod = "DecodeThumbBCCTargetOperand";
93 def t_cbtarget : Operand<i32> {
94 let EncoderMethod = "getThumbCBTargetOpValue";
95 let DecoderMethod = "DecodeThumbCmpBROperand";
98 def t_bltarget : Operand<i32> {
99 let EncoderMethod = "getThumbBLTargetOpValue";
100 let DecoderMethod = "DecodeThumbBLTargetOperand";
103 def t_blxtarget : Operand<i32> {
104 let EncoderMethod = "getThumbBLXTargetOpValue";
105 let DecoderMethod = "DecodeThumbBLXOffset";
109 // t_addrmode_rr := reg + reg
111 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
112 def t_addrmode_rr : Operand<i32>,
113 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
114 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
115 let PrintMethod = "printThumbAddrModeRROperand";
116 let DecoderMethod = "DecodeThumbAddrModeRR";
117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
120 // t_addrmode_rrs := reg + reg
122 def t_addrmode_rrs1 : Operand<i32>,
123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125 let PrintMethod = "printThumbAddrModeRROperand";
126 let DecoderMethod = "DecodeThumbAddrModeRR";
127 let ParserMatchClass = t_addrmode_rr_asm_operand;
128 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
130 def t_addrmode_rrs2 : Operand<i32>,
131 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
132 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
133 let DecoderMethod = "DecodeThumbAddrModeRR";
134 let PrintMethod = "printThumbAddrModeRROperand";
135 let ParserMatchClass = t_addrmode_rr_asm_operand;
136 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
138 def t_addrmode_rrs4 : Operand<i32>,
139 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
140 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
141 let DecoderMethod = "DecodeThumbAddrModeRR";
142 let PrintMethod = "printThumbAddrModeRROperand";
143 let ParserMatchClass = t_addrmode_rr_asm_operand;
144 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
147 // t_addrmode_is4 := reg + imm5 * 4
149 def t_addrmode_is4 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
151 let EncoderMethod = "getAddrModeISOpValue";
152 let DecoderMethod = "DecodeThumbAddrModeIS";
153 let PrintMethod = "printThumbAddrModeImm5S4Operand";
154 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
157 // t_addrmode_is2 := reg + imm5 * 2
159 def t_addrmode_is2 : Operand<i32>,
160 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
161 let EncoderMethod = "getAddrModeISOpValue";
162 let DecoderMethod = "DecodeThumbAddrModeIS";
163 let PrintMethod = "printThumbAddrModeImm5S2Operand";
164 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
167 // t_addrmode_is1 := reg + imm5
169 def t_addrmode_is1 : Operand<i32>,
170 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
171 let EncoderMethod = "getAddrModeISOpValue";
172 let DecoderMethod = "DecodeThumbAddrModeIS";
173 let PrintMethod = "printThumbAddrModeImm5S1Operand";
174 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
177 // t_addrmode_sp := sp + imm8 * 4
179 def t_addrmode_sp : Operand<i32>,
180 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
181 let EncoderMethod = "getAddrModeThumbSPOpValue";
182 let DecoderMethod = "DecodeThumbAddrModeSP";
183 let PrintMethod = "printThumbAddrModeSPOperand";
184 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
187 // t_addrmode_pc := <label> => pc + imm8 * 4
189 def t_addrmode_pc : Operand<i32> {
190 let EncoderMethod = "getAddrModePCOpValue";
191 let DecoderMethod = "DecodeThumbAddrModePC";
194 //===----------------------------------------------------------------------===//
195 // Miscellaneous Instructions.
198 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
199 // from removing one half of the matched pairs. That breaks PEI, which assumes
200 // these will always be in pairs, and asserts if it finds otherwise. Better way?
201 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
202 def tADJCALLSTACKUP :
203 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
204 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
205 Requires<[IsThumb, IsThumb1Only]>;
207 def tADJCALLSTACKDOWN :
208 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
209 [(ARMcallseq_start imm:$amt)]>,
210 Requires<[IsThumb, IsThumb1Only]>;
213 // T1Disassembly - A simple class to make encoding some disassembly patterns
214 // easier and less verbose.
215 class T1Disassembly<bits<2> op1, bits<8> op2>
216 : T1Encoding<0b101111> {
221 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
222 [/* For disassembly only; pattern left blank */]>,
223 T1Disassembly<0b11, 0x00>; // A8.6.110
225 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
226 [/* For disassembly only; pattern left blank */]>,
227 T1Disassembly<0b11, 0x10>; // A8.6.410
229 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
230 [/* For disassembly only; pattern left blank */]>,
231 T1Disassembly<0b11, 0x20>; // A8.6.408
233 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
234 [/* For disassembly only; pattern left blank */]>,
235 T1Disassembly<0b11, 0x30>; // A8.6.409
237 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
238 [/* For disassembly only; pattern left blank */]>,
239 T1Disassembly<0b11, 0x40>; // A8.6.157
241 // The i32imm operand $val can be used by a debugger to store more information
242 // about the breakpoint.
243 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
244 [/* For disassembly only; pattern left blank */]>,
245 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
251 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
252 []>, T1Encoding<0b101101> {
255 let Inst{9-5} = 0b10010;
258 let Inst{2-0} = 0b000;
261 // Change Processor State is a system instruction -- for disassembly only.
262 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
263 NoItinerary, "cps$imod $iflags",
264 [/* For disassembly only; pattern left blank */]>,
272 let Inst{2-0} = iflags;
273 let DecoderMethod = "DecodeThumbCPS";
276 // For both thumb1 and thumb2.
277 let isNotDuplicable = 1, isCodeGenOnly = 1 in
278 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
279 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
280 T1Special<{0,0,?,?}> {
283 let Inst{6-3} = 0b1111; // Rm = pc
287 // ADD <Rd>, sp, #<imm8>
288 // This is rematerializable, which is particularly useful for taking the
289 // address of locals.
290 let isReMaterializable = 1 in
291 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
292 "add\t$dst, $sp, $rhs", []>,
293 T1Encoding<{1,0,1,0,1,?}> {
297 let Inst{10-8} = dst;
299 let DecoderMethod = "DecodeThumbAddSpecialReg";
302 // ADD sp, sp, #<imm7>
303 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
304 "add\t$dst, $rhs", []>,
305 T1Misc<{0,0,0,0,0,?,?}> {
309 let DecoderMethod = "DecodeThumbAddSPImm";
312 // SUB sp, sp, #<imm7>
313 // FIXME: The encoding and the ASM string don't match up.
314 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
315 "sub\t$dst, $rhs", []>,
316 T1Misc<{0,0,0,0,1,?,?}> {
320 let DecoderMethod = "DecodeThumbAddSPImm";
324 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
325 "add\t$dst, $rhs", []>,
326 T1Special<{0,0,?,?}> {
327 // A8.6.9 Encoding T1
329 let Inst{7} = dst{3};
330 let Inst{6-3} = 0b1101;
331 let Inst{2-0} = dst{2-0};
332 let DecoderMethod = "DecodeThumbAddSPReg";
336 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
337 "add\t$dst, $rhs", []>,
338 T1Special<{0,0,?,?}> {
339 // A8.6.9 Encoding T2
343 let Inst{2-0} = 0b101;
344 let DecoderMethod = "DecodeThumbAddSPReg";
347 //===----------------------------------------------------------------------===//
348 // Control Flow Instructions.
352 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
353 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
354 T1Special<{1,1,0,?}> {
358 let Inst{2-0} = 0b000;
362 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
363 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
364 [(ARMretflag)], (tBX LR, pred:$p)>;
366 // Alternative return instruction used by vararg functions.
367 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
369 (tBX GPR:$Rm, pred:$p)>;
372 // All calls clobber the non-callee saved registers. SP is marked as a use to
373 // prevent stack-pointer assignments that appear immediately before calls from
374 // potentially appearing dead.
376 // On non-Darwin platforms R9 is callee-saved.
377 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
379 // Also used for Thumb2
380 def tBL : TIx2<0b11110, 0b11, 1,
381 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
383 [(ARMtcall tglobaladdr:$func)]>,
384 Requires<[IsThumb, IsNotDarwin]> {
386 let Inst{26} = func{21};
387 let Inst{25-16} = func{20-11};
390 let Inst{10-0} = func{10-0};
393 // ARMv5T and above, also used for Thumb2
394 def tBLXi : TIx2<0b11110, 0b11, 0,
395 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
397 [(ARMcall tglobaladdr:$func)]>,
398 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
400 let Inst{25-16} = func{20-11};
403 let Inst{10-1} = func{10-1};
404 let Inst{0} = 0; // func{0} is assumed zero
407 // Also used for Thumb2
408 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
410 [(ARMtcall GPR:$func)]>,
411 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
412 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
414 let Inst{6-3} = func;
415 let Inst{2-0} = 0b000;
419 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
421 [(ARMcall_nolink tGPR:$func)]>,
422 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
426 // On Darwin R9 is call-clobbered.
427 // R7 is marked as a use to prevent frame-pointer assignments from being
428 // moved above / below calls.
429 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
431 // Also used for Thumb2
432 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
433 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
434 (tBL pred:$p, t_bltarget:$func)>,
435 Requires<[IsThumb, IsDarwin]>;
437 // ARMv5T and above, also used for Thumb2
438 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
439 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
440 (tBLXi pred:$p, t_blxtarget:$func)>,
441 Requires<[IsThumb, HasV5T, IsDarwin]>;
443 // Also used for Thumb2
444 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
445 2, IIC_Br, [(ARMtcall GPR:$func)],
446 (tBLXr pred:$p, GPR:$func)>,
447 Requires<[IsThumb, HasV5T, IsDarwin]>;
450 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
452 [(ARMcall_nolink tGPR:$func)]>,
453 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
456 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
457 let isPredicable = 1 in
458 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
459 "b\t$target", [(br bb:$target)]>,
460 T1Encoding<{1,1,1,0,0,?}> {
462 let Inst{10-0} = target;
466 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
467 // the clobber of LR.
469 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
470 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
472 def tBR_JTr : tPseudoInst<(outs),
473 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
475 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
476 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
480 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
481 // a two-value operand where a dag node expects two operands. :(
482 let isBranch = 1, isTerminator = 1 in
483 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
485 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
486 T1BranchCond<{1,1,0,1}> {
490 let Inst{7-0} = target;
493 // Compare and branch on zero / non-zero
494 let isBranch = 1, isTerminator = 1 in {
495 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
496 "cbz\t$Rn, $target", []>,
497 T1Misc<{0,0,?,1,?,?,?}> {
501 let Inst{9} = target{5};
502 let Inst{7-3} = target{4-0};
506 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
507 "cbnz\t$Rn, $target", []>,
508 T1Misc<{1,0,?,1,?,?,?}> {
512 let Inst{9} = target{5};
513 let Inst{7-3} = target{4-0};
519 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
521 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
523 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
524 // on Darwin), so it's in ARMInstrThumb2.td.
525 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
527 (tBX GPR:$dst, (ops 14, zero_reg))>,
528 Requires<[IsThumb, IsDarwin]>;
530 // Non-Darwin versions (the difference is R9).
531 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
533 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
535 (tB t_brtarget:$dst)>,
536 Requires<[IsThumb, IsNotDarwin]>;
537 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
539 (tBX GPR:$dst, (ops 14, zero_reg))>,
540 Requires<[IsThumb, IsNotDarwin]>;
545 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
546 // A8.6.16 B: Encoding T1
547 // If Inst{11-8} == 0b1111 then SEE SVC
548 let isCall = 1, Uses = [SP] in
549 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
550 "svc", "\t$imm", []>, Encoding16 {
552 let Inst{15-12} = 0b1101;
553 let Inst{11-8} = 0b1111;
557 // The assembler uses 0xDEFE for a trap instruction.
558 let isBarrier = 1, isTerminator = 1 in
559 def tTRAP : TI<(outs), (ins), IIC_Br,
560 "trap", [(trap)]>, Encoding16 {
564 //===----------------------------------------------------------------------===//
565 // Load Store Instructions.
568 // Loads: reg/reg and reg/imm5
569 let canFoldAsLoad = 1, isReMaterializable = 1 in
570 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
571 Operand AddrMode_r, Operand AddrMode_i,
572 AddrMode am, InstrItinClass itin_r,
573 InstrItinClass itin_i, string asm,
576 T1pILdStEncode<reg_opc,
577 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
578 am, itin_r, asm, "\t$Rt, $addr",
579 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
581 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
582 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
583 am, itin_i, asm, "\t$Rt, $addr",
584 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
586 // Stores: reg/reg and reg/imm5
587 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
588 Operand AddrMode_r, Operand AddrMode_i,
589 AddrMode am, InstrItinClass itin_r,
590 InstrItinClass itin_i, string asm,
593 T1pILdStEncode<reg_opc,
594 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
595 am, itin_r, asm, "\t$Rt, $addr",
596 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
598 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
599 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
600 am, itin_i, asm, "\t$Rt, $addr",
601 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
605 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
606 t_addrmode_is4, AddrModeT1_4,
607 IIC_iLoad_r, IIC_iLoad_i, "ldr",
608 UnOpFrag<(load node:$Src)>>;
611 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
612 t_addrmode_is1, AddrModeT1_1,
613 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
614 UnOpFrag<(zextloadi8 node:$Src)>>;
617 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
618 t_addrmode_is2, AddrModeT1_2,
619 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
620 UnOpFrag<(zextloadi16 node:$Src)>>;
622 let AddedComplexity = 10 in
623 def tLDRSB : // A8.6.80
624 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
625 AddrModeT1_1, IIC_iLoad_bh_r,
626 "ldrsb", "\t$Rt, $addr",
627 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
629 let AddedComplexity = 10 in
630 def tLDRSH : // A8.6.84
631 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
632 AddrModeT1_2, IIC_iLoad_bh_r,
633 "ldrsh", "\t$Rt, $addr",
634 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
636 let canFoldAsLoad = 1 in
637 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
638 "ldr", "\t$Rt, $addr",
639 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
644 let Inst{7-0} = addr;
648 // FIXME: Use ldr.n to work around a Darwin assembler bug.
649 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
650 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
651 "ldr", ".n\t$Rt, $addr",
652 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
653 T1Encoding<{0,1,0,0,1,?}> {
658 let Inst{7-0} = addr;
661 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
662 // For disassembly use only.
663 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
664 "ldr", "\t$Rt, $addr",
665 [/* disassembly only */]>,
666 T1Encoding<{0,1,0,0,1,?}> {
671 let Inst{7-0} = addr;
674 // A8.6.194 & A8.6.192
675 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
676 t_addrmode_is4, AddrModeT1_4,
677 IIC_iStore_r, IIC_iStore_i, "str",
678 BinOpFrag<(store node:$LHS, node:$RHS)>>;
680 // A8.6.197 & A8.6.195
681 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
682 t_addrmode_is1, AddrModeT1_1,
683 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
684 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
686 // A8.6.207 & A8.6.205
687 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
688 t_addrmode_is2, AddrModeT1_2,
689 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
690 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
693 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
694 "str", "\t$Rt, $addr",
695 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
700 let Inst{7-0} = addr;
703 //===----------------------------------------------------------------------===//
704 // Load / store multiple Instructions.
707 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
708 InstrItinClass itin_upd, bits<6> T1Enc,
709 bit L_bit, string baseOpc> {
711 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
712 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
717 let Inst{7-0} = regs;
721 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
722 "$Rn = $wb", itin_upd>,
723 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
724 GPR:$Rn, pred:$p, reglist:$regs)> {
726 let OutOperandList = (outs GPR:$wb);
727 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
729 let isCodeGenOnly = 1;
731 list<Predicate> Predicates = [IsThumb];
735 // These require base address to be written back or one of the loaded regs.
736 let neverHasSideEffects = 1 in {
738 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
739 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
740 {1,1,0,0,1,?}, 1, "tLDM">;
742 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
743 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
744 {1,1,0,0,0,?}, 0, "tSTM">;
746 } // neverHasSideEffects
748 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
749 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
751 "pop${p}\t$regs", []>,
752 T1Misc<{1,1,0,?,?,?,?}> {
754 let Inst{8} = regs{15};
755 let Inst{7-0} = regs{7-0};
758 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
759 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
761 "push${p}\t$regs", []>,
762 T1Misc<{0,1,0,?,?,?,?}> {
764 let Inst{8} = regs{14};
765 let Inst{7-0} = regs{7-0};
768 //===----------------------------------------------------------------------===//
769 // Arithmetic Instructions.
772 // Helper classes for encoding T1pI patterns:
773 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
774 string opc, string asm, list<dag> pattern>
775 : T1pI<oops, iops, itin, opc, asm, pattern>,
776 T1DataProcessing<opA> {
782 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
783 string opc, string asm, list<dag> pattern>
784 : T1pI<oops, iops, itin, opc, asm, pattern>,
792 // Helper classes for encoding T1sI patterns:
793 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
794 string opc, string asm, list<dag> pattern>
795 : T1sI<oops, iops, itin, opc, asm, pattern>,
796 T1DataProcessing<opA> {
802 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
803 string opc, string asm, list<dag> pattern>
804 : T1sI<oops, iops, itin, opc, asm, pattern>,
813 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
814 string opc, string asm, list<dag> pattern>
815 : T1sI<oops, iops, itin, opc, asm, pattern>,
823 // Helper classes for encoding T1sIt patterns:
824 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
825 string opc, string asm, list<dag> pattern>
826 : T1sIt<oops, iops, itin, opc, asm, pattern>,
827 T1DataProcessing<opA> {
833 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
834 string opc, string asm, list<dag> pattern>
835 : T1sIt<oops, iops, itin, opc, asm, pattern>,
839 let Inst{10-8} = Rdn;
840 let Inst{7-0} = imm8;
843 // Add with carry register
844 let isCommutable = 1, Uses = [CPSR] in
846 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
847 "adc", "\t$Rdn, $Rm",
848 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
851 def tADDi3 : // A8.6.4 T1
852 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
854 "add", "\t$Rd, $Rm, $imm3",
855 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
857 let Inst{8-6} = imm3;
860 def tADDi8 : // A8.6.4 T2
861 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
862 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
863 "add", "\t$Rdn, $imm8",
864 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
867 let isCommutable = 1 in
868 def tADDrr : // A8.6.6 T1
869 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
871 "add", "\t$Rd, $Rn, $Rm",
872 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
874 let neverHasSideEffects = 1 in
875 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
876 "add", "\t$Rdn, $Rm", []>,
877 T1Special<{0,0,?,?}> {
881 let Inst{7} = Rdn{3};
883 let Inst{2-0} = Rdn{2-0};
887 let isCommutable = 1 in
888 def tAND : // A8.6.12
889 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
891 "and", "\t$Rdn, $Rm",
892 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
895 def tASRri : // A8.6.14
896 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
898 "asr", "\t$Rd, $Rm, $imm5",
899 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
901 let Inst{10-6} = imm5;
905 def tASRrr : // A8.6.15
906 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
908 "asr", "\t$Rdn, $Rm",
909 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
912 def tBIC : // A8.6.20
913 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
915 "bic", "\t$Rdn, $Rm",
916 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
919 let isCompare = 1, Defs = [CPSR] in {
920 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
921 // Compare-to-zero still works out, just not the relationals
922 //def tCMN : // A8.6.33
923 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
925 // "cmn", "\t$lhs, $rhs",
926 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
928 def tCMNz : // A8.6.33
929 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
932 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
934 } // isCompare = 1, Defs = [CPSR]
937 let isCompare = 1, Defs = [CPSR] in {
938 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
939 "cmp", "\t$Rn, $imm8",
940 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
941 T1General<{1,0,1,?,?}> {
946 let Inst{7-0} = imm8;
950 def tCMPr : // A8.6.36 T1
951 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
954 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
956 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
957 "cmp", "\t$Rn, $Rm", []>,
958 T1Special<{0,1,?,?}> {
964 let Inst{2-0} = Rn{2-0};
966 } // isCompare = 1, Defs = [CPSR]
970 let isCommutable = 1 in
971 def tEOR : // A8.6.45
972 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
974 "eor", "\t$Rdn, $Rm",
975 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
978 def tLSLri : // A8.6.88
979 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
981 "lsl", "\t$Rd, $Rm, $imm5",
982 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
984 let Inst{10-6} = imm5;
988 def tLSLrr : // A8.6.89
989 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
991 "lsl", "\t$Rdn, $Rm",
992 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
995 def tLSRri : // A8.6.90
996 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
998 "lsr", "\t$Rd, $Rm, $imm5",
999 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
1001 let Inst{10-6} = imm5;
1005 def tLSRrr : // A8.6.91
1006 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1008 "lsr", "\t$Rdn, $Rm",
1009 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1012 let isMoveImm = 1 in
1013 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1014 "mov", "\t$Rd, $imm8",
1015 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1016 T1General<{1,0,0,?,?}> {
1020 let Inst{10-8} = Rd;
1021 let Inst{7-0} = imm8;
1024 // A7-73: MOV(2) - mov setting flag.
1026 let neverHasSideEffects = 1 in {
1027 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1029 "mov", "\t$Rd, $Rm", "", []>,
1030 T1Special<{1,0,?,?}> {
1034 let Inst{7} = Rd{3};
1036 let Inst{2-0} = Rd{2-0};
1038 let Defs = [CPSR] in
1039 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1040 "movs\t$Rd, $Rm", []>, Encoding16 {
1044 let Inst{15-6} = 0b0000000000;
1048 } // neverHasSideEffects
1050 // Multiply register
1051 let isCommutable = 1 in
1052 def tMUL : // A8.6.105 T1
1053 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1055 "mul", "\t$Rdn, $Rm, $Rdn",
1056 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1058 // Move inverse register
1059 def tMVN : // A8.6.107
1060 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1061 "mvn", "\t$Rd, $Rn",
1062 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1064 // Bitwise or register
1065 let isCommutable = 1 in
1066 def tORR : // A8.6.114
1067 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1069 "orr", "\t$Rdn, $Rm",
1070 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1073 def tREV : // A8.6.134
1074 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1076 "rev", "\t$Rd, $Rm",
1077 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1078 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1080 def tREV16 : // A8.6.135
1081 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1083 "rev16", "\t$Rd, $Rm",
1084 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1085 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1087 def tREVSH : // A8.6.136
1088 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1090 "revsh", "\t$Rd, $Rm",
1091 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1092 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1094 // Rotate right register
1095 def tROR : // A8.6.139
1096 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1098 "ror", "\t$Rdn, $Rm",
1099 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1102 def tRSB : // A8.6.141
1103 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1105 "rsb", "\t$Rd, $Rn, #0",
1106 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1108 // Subtract with carry register
1109 let Uses = [CPSR] in
1110 def tSBC : // A8.6.151
1111 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1113 "sbc", "\t$Rdn, $Rm",
1114 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1116 // Subtract immediate
1117 def tSUBi3 : // A8.6.210 T1
1118 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1120 "sub", "\t$Rd, $Rm, $imm3",
1121 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1123 let Inst{8-6} = imm3;
1126 def tSUBi8 : // A8.6.210 T2
1127 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1129 "sub", "\t$Rdn, $imm8",
1130 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1132 // Subtract register
1133 def tSUBrr : // A8.6.212
1134 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1136 "sub", "\t$Rd, $Rn, $Rm",
1137 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1139 // TODO: A7-96: STMIA - store multiple.
1142 def tSXTB : // A8.6.222
1143 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1145 "sxtb", "\t$Rd, $Rm",
1146 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1147 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1149 // Sign-extend short
1150 def tSXTH : // A8.6.224
1151 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1153 "sxth", "\t$Rd, $Rm",
1154 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1155 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1158 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1159 def tTST : // A8.6.230
1160 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1161 "tst", "\t$Rn, $Rm",
1162 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1165 def tUXTB : // A8.6.262
1166 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1168 "uxtb", "\t$Rd, $Rm",
1169 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1170 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1172 // Zero-extend short
1173 def tUXTH : // A8.6.264
1174 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1176 "uxth", "\t$Rd, $Rm",
1177 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1178 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1180 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1181 // Expanded after instruction selection into a branch sequence.
1182 let usesCustomInserter = 1 in // Expanded after instruction selection.
1183 def tMOVCCr_pseudo :
1184 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1186 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1188 // tLEApcrel - Load a pc-relative address into a register without offending the
1191 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1192 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1193 T1Encoding<{1,0,1,0,0,?}> {
1196 let Inst{10-8} = Rd;
1197 let Inst{7-0} = addr;
1198 let DecoderMethod = "DecodeThumbAddSpecialReg";
1201 let neverHasSideEffects = 1, isReMaterializable = 1 in
1202 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1205 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1206 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1209 //===----------------------------------------------------------------------===//
1213 // __aeabi_read_tp preserves the registers r1-r3.
1214 // This is a pseudo inst so that we can get the encoding right,
1215 // complete with fixup for the aeabi_read_tp function.
1216 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1217 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1218 [(set R0, ARMthread_pointer)]>;
1220 //===----------------------------------------------------------------------===//
1221 // SJLJ Exception handling intrinsics
1224 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1225 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1226 // from some other function to get here, and we're using the stack frame for the
1227 // containing function to save/restore registers, we can't keep anything live in
1228 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1229 // tromped upon when we get here from a longjmp(). We force everything out of
1230 // registers except for our own input by listing the relevant registers in
1231 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1232 // preserve all of the callee-saved resgisters, which is exactly what we want.
1233 // $val is a scratch register for our use.
1234 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1235 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1236 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1237 AddrModeNone, 0, NoItinerary, "","",
1238 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1240 // FIXME: Non-Darwin version(s)
1241 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1242 Defs = [ R7, LR, SP ] in
1243 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1244 AddrModeNone, 0, IndexModeNone,
1245 Pseudo, NoItinerary, "", "",
1246 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1247 Requires<[IsThumb, IsDarwin]>;
1249 //===----------------------------------------------------------------------===//
1250 // Non-Instruction Patterns
1254 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1255 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1256 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1257 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1260 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1261 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1262 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1263 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1264 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1265 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1267 // Subtract with carry
1268 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1269 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1270 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1271 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1272 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1273 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1275 // ConstantPool, GlobalAddress
1276 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1277 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1280 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1281 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1284 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1285 Requires<[IsThumb, IsNotDarwin]>;
1286 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1287 Requires<[IsThumb, IsDarwin]>;
1289 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1290 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1291 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1292 Requires<[IsThumb, HasV5T, IsDarwin]>;
1294 // Indirect calls to ARM routines
1295 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1296 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1297 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1298 Requires<[IsThumb, HasV5T, IsDarwin]>;
1300 // zextload i1 -> zextload i8
1301 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1302 (tLDRBr t_addrmode_rrs1:$addr)>;
1303 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1304 (tLDRBi t_addrmode_is1:$addr)>;
1306 // extload -> zextload
1307 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1308 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1309 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1310 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1311 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1312 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1314 // If it's impossible to use [r,r] address mode for sextload, select to
1315 // ldr{b|h} + sxt{b|h} instead.
1316 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1317 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1318 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1319 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1320 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1321 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1322 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1323 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1324 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1325 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1326 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1327 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1329 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1330 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1331 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1332 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1333 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1334 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1335 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1336 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1338 // Large immediate handling.
1341 def : T1Pat<(i32 thumb_immshifted:$src),
1342 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1343 (thumb_immshifted_shamt imm:$src))>;
1345 def : T1Pat<(i32 imm0_255_comp:$src),
1346 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1348 // Pseudo instruction that combines ldr from constpool and add pc. This should
1349 // be expanded into two instructions late to allow if-conversion and
1351 let isReMaterializable = 1 in
1352 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1354 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1356 Requires<[IsThumb, IsThumb1Only]>;
1358 // Pseudo-instruction for merged POP and return.
1359 // FIXME: remove when we have a way to marking a MI with these properties.
1360 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1361 hasExtraDefRegAllocReq = 1 in
1362 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1364 (tPOP pred:$p, reglist:$regs)>;
1366 // Indirect branch using "mov pc, $Rm"
1367 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1368 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1369 2, IIC_Br, [(brind GPR:$Rm)],
1370 (tMOVr PC, GPR:$Rm, pred:$p)>;