1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_comp_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 def imm0_7_neg : PatLeaf<(i32 imm), [{
40 return (uint32_t)-N->getZExtValue() < 8;
43 def imm0_255_comp : PatLeaf<(i32 imm), [{
44 return ~((uint32_t)N->getZExtValue()) < 256;
47 def imm8_255 : ImmLeaf<i32, [{
48 return Imm >= 8 && Imm < 256;
50 def imm8_255_neg : PatLeaf<(i32 imm), [{
51 unsigned Val = -N->getZExtValue();
52 return Val >= 8 && Val < 256;
55 // Break imm's up into two pieces: an immediate + a left shift. This uses
56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
57 // to get the val/shift pieces.
58 def thumb_immshifted : PatLeaf<(imm), [{
59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
62 def thumb_immshifted_val : SDNodeXForm<imm, [{
63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
64 return CurDAG->getTargetConstant(V, MVT::i32);
67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
69 return CurDAG->getTargetConstant(V, MVT::i32);
72 // ADR instruction labels.
73 def t_adrlabel : Operand<i32> {
74 let EncoderMethod = "getThumbAdrLabelOpValue";
77 // Scaled 4 immediate.
78 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
79 def t_imm0_1020s4 : Operand<i32> {
80 let PrintMethod = "printThumbS4ImmOperand";
81 let ParserMatchClass = t_imm0_1020s4_asmoperand;
82 let OperandType = "OPERAND_IMMEDIATE";
85 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
86 def t_imm0_508s4 : Operand<i32> {
87 let PrintMethod = "printThumbS4ImmOperand";
88 let ParserMatchClass = t_imm0_508s4_asmoperand;
89 let OperandType = "OPERAND_IMMEDIATE";
91 // Alias use only, so no printer is necessary.
92 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
93 def t_imm0_508s4_neg : Operand<i32> {
94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
95 let OperandType = "OPERAND_IMMEDIATE";
98 // Define Thumb specific addressing modes.
100 let OperandType = "OPERAND_PCREL" in {
101 def t_brtarget : Operand<OtherVT> {
102 let EncoderMethod = "getThumbBRTargetOpValue";
103 let DecoderMethod = "DecodeThumbBROperand";
106 def t_bcctarget : Operand<i32> {
107 let EncoderMethod = "getThumbBCCTargetOpValue";
108 let DecoderMethod = "DecodeThumbBCCTargetOperand";
111 def t_cbtarget : Operand<i32> {
112 let EncoderMethod = "getThumbCBTargetOpValue";
113 let DecoderMethod = "DecodeThumbCmpBROperand";
116 def t_bltarget : Operand<i32> {
117 let EncoderMethod = "getThumbBLTargetOpValue";
118 let DecoderMethod = "DecodeThumbBLTargetOperand";
121 def t_blxtarget : Operand<i32> {
122 let EncoderMethod = "getThumbBLXTargetOpValue";
123 let DecoderMethod = "DecodeThumbBLXOffset";
127 // t_addrmode_rr := reg + reg
129 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
130 def t_addrmode_rr : Operand<i32>,
131 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
132 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
133 let PrintMethod = "printThumbAddrModeRROperand";
134 let DecoderMethod = "DecodeThumbAddrModeRR";
135 let ParserMatchClass = t_addrmode_rr_asm_operand;
136 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
139 // t_addrmode_rrs := reg + reg
141 // We use separate scaled versions because the Select* functions need
142 // to explicitly check for a matching constant and return false here so that
143 // the reg+imm forms will match instead. This is a horrible way to do that,
144 // as it forces tight coupling between the methods, but it's how selectiondag
146 def t_addrmode_rrs1 : Operand<i32>,
147 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
148 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
149 let PrintMethod = "printThumbAddrModeRROperand";
150 let DecoderMethod = "DecodeThumbAddrModeRR";
151 let ParserMatchClass = t_addrmode_rr_asm_operand;
152 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
154 def t_addrmode_rrs2 : Operand<i32>,
155 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
156 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
157 let DecoderMethod = "DecodeThumbAddrModeRR";
158 let PrintMethod = "printThumbAddrModeRROperand";
159 let ParserMatchClass = t_addrmode_rr_asm_operand;
160 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
162 def t_addrmode_rrs4 : Operand<i32>,
163 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
164 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
165 let DecoderMethod = "DecodeThumbAddrModeRR";
166 let PrintMethod = "printThumbAddrModeRROperand";
167 let ParserMatchClass = t_addrmode_rr_asm_operand;
168 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
171 // t_addrmode_is4 := reg + imm5 * 4
173 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
174 def t_addrmode_is4 : Operand<i32>,
175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
176 let EncoderMethod = "getAddrModeISOpValue";
177 let DecoderMethod = "DecodeThumbAddrModeIS";
178 let PrintMethod = "printThumbAddrModeImm5S4Operand";
179 let ParserMatchClass = t_addrmode_is4_asm_operand;
180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
183 // t_addrmode_is2 := reg + imm5 * 2
185 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
186 def t_addrmode_is2 : Operand<i32>,
187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
188 let EncoderMethod = "getAddrModeISOpValue";
189 let DecoderMethod = "DecodeThumbAddrModeIS";
190 let PrintMethod = "printThumbAddrModeImm5S2Operand";
191 let ParserMatchClass = t_addrmode_is2_asm_operand;
192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
195 // t_addrmode_is1 := reg + imm5
197 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
198 def t_addrmode_is1 : Operand<i32>,
199 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
200 let EncoderMethod = "getAddrModeISOpValue";
201 let DecoderMethod = "DecodeThumbAddrModeIS";
202 let PrintMethod = "printThumbAddrModeImm5S1Operand";
203 let ParserMatchClass = t_addrmode_is1_asm_operand;
204 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
207 // t_addrmode_sp := sp + imm8 * 4
209 // FIXME: This really shouldn't have an explicit SP operand at all. It should
210 // be implicit, just like in the instruction encoding itself.
211 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
212 def t_addrmode_sp : Operand<i32>,
213 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
214 let EncoderMethod = "getAddrModeThumbSPOpValue";
215 let DecoderMethod = "DecodeThumbAddrModeSP";
216 let PrintMethod = "printThumbAddrModeSPOperand";
217 let ParserMatchClass = t_addrmode_sp_asm_operand;
218 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
221 // t_addrmode_pc := <label> => pc + imm8 * 4
223 def t_addrmode_pc : Operand<i32> {
224 let EncoderMethod = "getAddrModePCOpValue";
225 let DecoderMethod = "DecodeThumbAddrModePC";
226 let PrintMethod = "printThumbLdrLabelOperand";
229 //===----------------------------------------------------------------------===//
230 // Miscellaneous Instructions.
233 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
234 // from removing one half of the matched pairs. That breaks PEI, which assumes
235 // these will always be in pairs, and asserts if it finds otherwise. Better way?
236 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
237 def tADJCALLSTACKUP :
238 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
239 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
240 Requires<[IsThumb, IsThumb1Only]>;
242 def tADJCALLSTACKDOWN :
243 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
244 [(ARMcallseq_start imm:$amt)]>,
245 Requires<[IsThumb, IsThumb1Only]>;
248 class T1SystemEncoding<bits<8> opc>
249 : T1Encoding<0b101111> {
250 let Inst{9-8} = 0b11;
254 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
255 T1SystemEncoding<0x00>, // A8.6.110
256 Requires<[IsThumb2]>;
258 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
259 T1SystemEncoding<0x10>, // A8.6.410
260 Requires<[IsThumb2]>;
262 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
263 T1SystemEncoding<0x20>, // A8.6.408
264 Requires<[IsThumb2]>;
266 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
267 T1SystemEncoding<0x30>, // A8.6.409
268 Requires<[IsThumb2]>;
270 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
271 T1SystemEncoding<0x40>, // A8.6.157
272 Requires<[IsThumb2]>;
274 // The imm operand $val can be used by a debugger to store more information
275 // about the breakpoint.
276 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
278 T1Encoding<0b101111> {
279 let Inst{9-8} = 0b10;
285 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
286 []>, T1Encoding<0b101101> {
289 let Inst{9-5} = 0b10010;
292 let Inst{2-0} = 0b000;
295 // Change Processor State is a system instruction -- for disassembly only.
296 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
297 NoItinerary, "cps$imod $iflags", []>,
305 let Inst{2-0} = iflags;
306 let DecoderMethod = "DecodeThumbCPS";
309 // For both thumb1 and thumb2.
310 let isNotDuplicable = 1, isCodeGenOnly = 1 in
311 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
312 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
313 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
316 let Inst{6-3} = 0b1111; // Rm = pc
320 // ADD <Rd>, sp, #<imm8>
321 // FIXME: This should not be marked as having side effects, and it should be
322 // rematerializable. Clearing the side effect bit causes miscompilations,
323 // probably because the instruction can be moved around.
324 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
325 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
326 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
330 let Inst{10-8} = dst;
332 let DecoderMethod = "DecodeThumbAddSpecialReg";
335 // ADD sp, sp, #<imm7>
336 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
337 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
338 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
342 let DecoderMethod = "DecodeThumbAddSPImm";
345 // SUB sp, sp, #<imm7>
346 // FIXME: The encoding and the ASM string don't match up.
347 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
348 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
349 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
353 let DecoderMethod = "DecodeThumbAddSPImm";
356 def : tInstAlias<"add${p} sp, $imm",
357 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
358 def : tInstAlias<"add${p} sp, sp, $imm",
359 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
361 // Can optionally specify SP as a three operand instruction.
362 def : tInstAlias<"add${p} sp, sp, $imm",
363 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
364 def : tInstAlias<"sub${p} sp, sp, $imm",
365 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
368 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
369 "add", "\t$Rdn, $sp, $Rn", []>,
370 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
371 // A8.6.9 Encoding T1
373 let Inst{7} = Rdn{3};
374 let Inst{6-3} = 0b1101;
375 let Inst{2-0} = Rdn{2-0};
376 let DecoderMethod = "DecodeThumbAddSPReg";
380 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
381 "add", "\t$Rdn, $Rm", []>,
382 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
383 // A8.6.9 Encoding T2
387 let Inst{2-0} = 0b101;
388 let DecoderMethod = "DecodeThumbAddSPReg";
391 //===----------------------------------------------------------------------===//
392 // Control Flow Instructions.
396 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
397 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
398 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
402 let Inst{2-0} = 0b000;
403 let Unpredictable{2-0} = 0b111;
407 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
408 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
409 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
411 // Alternative return instruction used by vararg functions.
412 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
414 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
417 // All calls clobber the non-callee saved registers. SP is marked as a use to
418 // prevent stack-pointer assignments that appear immediately before calls from
419 // potentially appearing dead.
421 Defs = [LR], Uses = [SP] in {
422 // Also used for Thumb2
423 def tBL : TIx2<0b11110, 0b11, 1,
424 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
426 [(ARMtcall tglobaladdr:$func)]>,
427 Requires<[IsThumb]>, Sched<[WriteBrL]> {
429 let Inst{26} = func{23};
430 let Inst{25-16} = func{20-11};
431 let Inst{13} = func{22};
432 let Inst{11} = func{21};
433 let Inst{10-0} = func{10-0};
436 // ARMv5T and above, also used for Thumb2
437 def tBLXi : TIx2<0b11110, 0b11, 0,
438 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
440 [(ARMcall tglobaladdr:$func)]>,
441 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> {
443 let Inst{26} = func{23};
444 let Inst{25-16} = func{20-11};
445 let Inst{13} = func{22};
446 let Inst{11} = func{21};
447 let Inst{10-1} = func{10-1};
448 let Inst{0} = 0; // func{0} is assumed zero
451 // Also used for Thumb2
452 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
454 [(ARMtcall GPR:$func)]>,
455 Requires<[IsThumb, HasV5T]>,
456 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
458 let Inst{6-3} = func;
459 let Inst{2-0} = 0b000;
463 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
465 [(ARMcall_nolink tGPR:$func)]>,
466 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
469 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
470 let isPredicable = 1 in
471 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
472 "b", "\t$target", [(br bb:$target)]>,
473 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
475 let Inst{10-0} = target;
479 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
480 // the clobber of LR.
482 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
483 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
486 def tBR_JTr : tPseudoInst<(outs),
487 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
489 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
490 Sched<[WriteBrTbl]> {
491 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
495 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
496 // a two-value operand where a dag node expects two operands. :(
497 let isBranch = 1, isTerminator = 1 in
498 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
500 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
501 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
505 let Inst{7-0} = target;
509 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
512 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
514 (tBX GPR:$dst, (ops 14, zero_reg))>,
515 Requires<[IsThumb]>, Sched<[WriteBr]>;
517 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
518 // on IOS), so it's in ARMInstrThumb2.td.
521 def tTAILJMPdND : tPseudoExpand<(outs),
522 (ins t_brtarget:$dst, pred:$p),
524 (tB t_brtarget:$dst, pred:$p)>,
525 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>;
530 // A8.6.218 Supervisor Call (Software Interrupt)
531 // A8.6.16 B: Encoding T1
532 // If Inst{11-8} == 0b1111 then SEE SVC
533 let isCall = 1, Uses = [SP] in
534 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
535 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
537 let Inst{15-12} = 0b1101;
538 let Inst{11-8} = 0b1111;
542 // The assembler uses 0xDEFE for a trap instruction.
543 let isBarrier = 1, isTerminator = 1 in
544 def tTRAP : TI<(outs), (ins), IIC_Br,
545 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
549 //===----------------------------------------------------------------------===//
550 // Load Store Instructions.
553 // Loads: reg/reg and reg/imm5
554 let canFoldAsLoad = 1, isReMaterializable = 1 in
555 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
556 Operand AddrMode_r, Operand AddrMode_i,
557 AddrMode am, InstrItinClass itin_r,
558 InstrItinClass itin_i, string asm,
561 T1pILdStEncode<reg_opc,
562 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
563 am, itin_r, asm, "\t$Rt, $addr",
564 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
566 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
567 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
568 am, itin_i, asm, "\t$Rt, $addr",
569 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
571 // Stores: reg/reg and reg/imm5
572 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
573 Operand AddrMode_r, Operand AddrMode_i,
574 AddrMode am, InstrItinClass itin_r,
575 InstrItinClass itin_i, string asm,
578 T1pILdStEncode<reg_opc,
579 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
580 am, itin_r, asm, "\t$Rt, $addr",
581 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
583 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
584 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
585 am, itin_i, asm, "\t$Rt, $addr",
586 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
590 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
591 t_addrmode_is4, AddrModeT1_4,
592 IIC_iLoad_r, IIC_iLoad_i, "ldr",
593 UnOpFrag<(load node:$Src)>>;
596 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
597 t_addrmode_is1, AddrModeT1_1,
598 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
599 UnOpFrag<(zextloadi8 node:$Src)>>;
602 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
603 t_addrmode_is2, AddrModeT1_2,
604 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
605 UnOpFrag<(zextloadi16 node:$Src)>>;
607 let AddedComplexity = 10 in
608 def tLDRSB : // A8.6.80
609 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
610 AddrModeT1_1, IIC_iLoad_bh_r,
611 "ldrsb", "\t$Rt, $addr",
612 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
614 let AddedComplexity = 10 in
615 def tLDRSH : // A8.6.84
616 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
617 AddrModeT1_2, IIC_iLoad_bh_r,
618 "ldrsh", "\t$Rt, $addr",
619 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
621 let canFoldAsLoad = 1 in
622 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
623 "ldr", "\t$Rt, $addr",
624 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
629 let Inst{7-0} = addr;
633 // FIXME: Use ldr.n to work around a darwin assembler bug.
634 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
635 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
636 "ldr", ".n\t$Rt, $addr",
637 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
638 T1Encoding<{0,1,0,0,1,?}> {
643 let Inst{7-0} = addr;
646 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
647 // For assembly/disassembly use only.
648 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
649 "ldr", "\t$Rt, $addr", []>,
650 T1Encoding<{0,1,0,0,1,?}> {
655 let Inst{7-0} = addr;
658 // A8.6.194 & A8.6.192
659 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
660 t_addrmode_is4, AddrModeT1_4,
661 IIC_iStore_r, IIC_iStore_i, "str",
662 BinOpFrag<(store node:$LHS, node:$RHS)>>;
664 // A8.6.197 & A8.6.195
665 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
666 t_addrmode_is1, AddrModeT1_1,
667 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
668 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
670 // A8.6.207 & A8.6.205
671 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
672 t_addrmode_is2, AddrModeT1_2,
673 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
674 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
677 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
678 "str", "\t$Rt, $addr",
679 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
684 let Inst{7-0} = addr;
687 //===----------------------------------------------------------------------===//
688 // Load / store multiple Instructions.
691 // These require base address to be written back or one of the loaded regs.
692 let neverHasSideEffects = 1 in {
694 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
695 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
696 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
700 let Inst{7-0} = regs;
703 // Writeback version is just a pseudo, as there's no encoding difference.
704 // Writeback happens iff the base register is not in the destination register
707 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
708 "$Rn = $wb", IIC_iLoad_mu>,
709 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
711 let OutOperandList = (outs GPR:$wb);
712 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
714 let isCodeGenOnly = 1;
716 list<Predicate> Predicates = [IsThumb];
719 // There is no non-writeback version of STM for Thumb.
720 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
721 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
722 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
723 AddrModeNone, 2, IIC_iStore_mu,
724 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
725 T1Encoding<{1,1,0,0,0,?}> {
729 let Inst{7-0} = regs;
732 } // neverHasSideEffects
734 def : InstAlias<"ldm${p} $Rn!, $regs",
735 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
736 Requires<[IsThumb, IsThumb1Only]>;
738 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
739 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
741 "pop${p}\t$regs", []>,
742 T1Misc<{1,1,0,?,?,?,?}> {
744 let Inst{8} = regs{15};
745 let Inst{7-0} = regs{7-0};
748 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
749 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
751 "push${p}\t$regs", []>,
752 T1Misc<{0,1,0,?,?,?,?}> {
754 let Inst{8} = regs{14};
755 let Inst{7-0} = regs{7-0};
758 //===----------------------------------------------------------------------===//
759 // Arithmetic Instructions.
762 // Helper classes for encoding T1pI patterns:
763 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
764 string opc, string asm, list<dag> pattern>
765 : T1pI<oops, iops, itin, opc, asm, pattern>,
766 T1DataProcessing<opA> {
772 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
773 string opc, string asm, list<dag> pattern>
774 : T1pI<oops, iops, itin, opc, asm, pattern>,
782 // Helper classes for encoding T1sI patterns:
783 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
784 string opc, string asm, list<dag> pattern>
785 : T1sI<oops, iops, itin, opc, asm, pattern>,
786 T1DataProcessing<opA> {
792 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
793 string opc, string asm, list<dag> pattern>
794 : T1sI<oops, iops, itin, opc, asm, pattern>,
803 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
804 string opc, string asm, list<dag> pattern>
805 : T1sI<oops, iops, itin, opc, asm, pattern>,
813 // Helper classes for encoding T1sIt patterns:
814 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
815 string opc, string asm, list<dag> pattern>
816 : T1sIt<oops, iops, itin, opc, asm, pattern>,
817 T1DataProcessing<opA> {
823 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
824 string opc, string asm, list<dag> pattern>
825 : T1sIt<oops, iops, itin, opc, asm, pattern>,
829 let Inst{10-8} = Rdn;
830 let Inst{7-0} = imm8;
833 // Add with carry register
834 let isCommutable = 1, Uses = [CPSR] in
836 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
837 "adc", "\t$Rdn, $Rm",
838 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
841 def tADDi3 : // A8.6.4 T1
842 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
844 "add", "\t$Rd, $Rm, $imm3",
845 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
848 let Inst{8-6} = imm3;
851 def tADDi8 : // A8.6.4 T2
852 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
853 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
854 "add", "\t$Rdn, $imm8",
855 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
859 let isCommutable = 1 in
860 def tADDrr : // A8.6.6 T1
861 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
863 "add", "\t$Rd, $Rn, $Rm",
864 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
866 let neverHasSideEffects = 1 in
867 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
868 "add", "\t$Rdn, $Rm", []>,
869 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
873 let Inst{7} = Rdn{3};
875 let Inst{2-0} = Rdn{2-0};
879 let isCommutable = 1 in
880 def tAND : // A8.6.12
881 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
883 "and", "\t$Rdn, $Rm",
884 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
887 def tASRri : // A8.6.14
888 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
890 "asr", "\t$Rd, $Rm, $imm5",
891 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
894 let Inst{10-6} = imm5;
898 def tASRrr : // A8.6.15
899 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
901 "asr", "\t$Rdn, $Rm",
902 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
905 def tBIC : // A8.6.20
906 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
908 "bic", "\t$Rdn, $Rm",
909 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
913 let isCompare = 1, Defs = [CPSR] in {
914 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
915 // Compare-to-zero still works out, just not the relationals
916 //def tCMN : // A8.6.33
917 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
919 // "cmn", "\t$lhs, $rhs",
920 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
922 def tCMNz : // A8.6.33
923 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
926 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
928 } // isCompare = 1, Defs = [CPSR]
931 let isCompare = 1, Defs = [CPSR] in {
932 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
933 "cmp", "\t$Rn, $imm8",
934 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
935 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
940 let Inst{7-0} = imm8;
944 def tCMPr : // A8.6.36 T1
945 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
948 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
950 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
951 "cmp", "\t$Rn, $Rm", []>,
952 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
958 let Inst{2-0} = Rn{2-0};
960 } // isCompare = 1, Defs = [CPSR]
964 let isCommutable = 1 in
965 def tEOR : // A8.6.45
966 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
968 "eor", "\t$Rdn, $Rm",
969 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
972 def tLSLri : // A8.6.88
973 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
975 "lsl", "\t$Rd, $Rm, $imm5",
976 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
979 let Inst{10-6} = imm5;
983 def tLSLrr : // A8.6.89
984 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
986 "lsl", "\t$Rdn, $Rm",
987 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
990 def tLSRri : // A8.6.90
991 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
993 "lsr", "\t$Rd, $Rm, $imm5",
994 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
997 let Inst{10-6} = imm5;
1001 def tLSRrr : // A8.6.91
1002 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1004 "lsr", "\t$Rdn, $Rm",
1005 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1008 let isMoveImm = 1 in
1009 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1010 "mov", "\t$Rd, $imm8",
1011 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1012 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1016 let Inst{10-8} = Rd;
1017 let Inst{7-0} = imm8;
1019 // Because we have an explicit tMOVSr below, we need an alias to handle
1020 // the immediate "movs" form here. Blech.
1021 def : tInstAlias <"movs $Rdn, $imm",
1022 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1024 // A7-73: MOV(2) - mov setting flag.
1026 let neverHasSideEffects = 1 in {
1027 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1029 "mov", "\t$Rd, $Rm", "", []>,
1030 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1034 let Inst{7} = Rd{3};
1036 let Inst{2-0} = Rd{2-0};
1038 let Defs = [CPSR] in
1039 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1040 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1044 let Inst{15-6} = 0b0000000000;
1048 } // neverHasSideEffects
1050 // Multiply register
1051 let isCommutable = 1 in
1052 def tMUL : // A8.6.105 T1
1053 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1054 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1055 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1056 T1DataProcessing<0b1101> {
1061 let AsmMatchConverter = "cvtThumbMultiply";
1064 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1067 // Move inverse register
1068 def tMVN : // A8.6.107
1069 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1070 "mvn", "\t$Rd, $Rn",
1071 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1073 // Bitwise or register
1074 let isCommutable = 1 in
1075 def tORR : // A8.6.114
1076 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1078 "orr", "\t$Rdn, $Rm",
1079 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1082 def tREV : // A8.6.134
1083 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1085 "rev", "\t$Rd, $Rm",
1086 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1087 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1089 def tREV16 : // A8.6.135
1090 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1092 "rev16", "\t$Rd, $Rm",
1093 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1094 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1096 def tREVSH : // A8.6.136
1097 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1099 "revsh", "\t$Rd, $Rm",
1100 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1101 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1103 // Rotate right register
1104 def tROR : // A8.6.139
1105 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1107 "ror", "\t$Rdn, $Rm",
1108 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1112 def tRSB : // A8.6.141
1113 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1115 "rsb", "\t$Rd, $Rn, #0",
1116 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1118 // Subtract with carry register
1119 let Uses = [CPSR] in
1120 def tSBC : // A8.6.151
1121 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1123 "sbc", "\t$Rdn, $Rm",
1124 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
1127 // Subtract immediate
1128 def tSUBi3 : // A8.6.210 T1
1129 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1131 "sub", "\t$Rd, $Rm, $imm3",
1132 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1135 let Inst{8-6} = imm3;
1138 def tSUBi8 : // A8.6.210 T2
1139 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1140 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1141 "sub", "\t$Rdn, $imm8",
1142 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1145 // Subtract register
1146 def tSUBrr : // A8.6.212
1147 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1149 "sub", "\t$Rd, $Rn, $Rm",
1150 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1154 def tSXTB : // A8.6.222
1155 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1157 "sxtb", "\t$Rd, $Rm",
1158 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1159 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1162 // Sign-extend short
1163 def tSXTH : // A8.6.224
1164 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1166 "sxth", "\t$Rd, $Rm",
1167 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1168 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1172 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1173 def tTST : // A8.6.230
1174 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1175 "tst", "\t$Rn, $Rm",
1176 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1180 def tUXTB : // A8.6.262
1181 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1183 "uxtb", "\t$Rd, $Rm",
1184 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1185 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1188 // Zero-extend short
1189 def tUXTH : // A8.6.264
1190 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1192 "uxth", "\t$Rd, $Rm",
1193 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1194 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1196 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1197 // Expanded after instruction selection into a branch sequence.
1198 let usesCustomInserter = 1 in // Expanded after instruction selection.
1199 def tMOVCCr_pseudo :
1200 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1202 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1204 // tLEApcrel - Load a pc-relative address into a register without offending the
1207 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1208 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1209 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1212 let Inst{10-8} = Rd;
1213 let Inst{7-0} = addr;
1214 let DecoderMethod = "DecodeThumbAddSpecialReg";
1217 let neverHasSideEffects = 1, isReMaterializable = 1 in
1218 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1219 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1221 let hasSideEffects = 1 in
1222 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1223 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1224 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1226 //===----------------------------------------------------------------------===//
1230 // __aeabi_read_tp preserves the registers r1-r3.
1231 // This is a pseudo inst so that we can get the encoding right,
1232 // complete with fixup for the aeabi_read_tp function.
1233 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1234 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1235 [(set R0, ARMthread_pointer)]>,
1238 //===----------------------------------------------------------------------===//
1239 // SJLJ Exception handling intrinsics
1242 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1243 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1244 // from some other function to get here, and we're using the stack frame for the
1245 // containing function to save/restore registers, we can't keep anything live in
1246 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1247 // tromped upon when we get here from a longjmp(). We force everything out of
1248 // registers except for our own input by listing the relevant registers in
1249 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1250 // preserve all of the callee-saved resgisters, which is exactly what we want.
1251 // $val is a scratch register for our use.
1252 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1253 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1254 usesCustomInserter = 1 in
1255 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1256 AddrModeNone, 0, NoItinerary, "","",
1257 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1259 // FIXME: Non-IOS version(s)
1260 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1261 Defs = [ R7, LR, SP ] in
1262 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1263 AddrModeNone, 0, IndexModeNone,
1264 Pseudo, NoItinerary, "", "",
1265 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1266 Requires<[IsThumb, IsIOS]>;
1268 //===----------------------------------------------------------------------===//
1269 // Non-Instruction Patterns
1273 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1274 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1275 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1276 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1279 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1280 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1281 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1282 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1283 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1284 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1286 // Subtract with carry
1287 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1288 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1289 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1290 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1291 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1292 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1294 // ConstantPool, GlobalAddress
1295 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1296 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1299 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1300 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1303 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1304 Requires<[IsThumb]>;
1306 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1307 Requires<[IsThumb, HasV5T]>;
1309 // Indirect calls to ARM routines
1310 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1311 Requires<[IsThumb, HasV5T]>;
1313 // zextload i1 -> zextload i8
1314 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1315 (tLDRBr t_addrmode_rrs1:$addr)>;
1316 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1317 (tLDRBi t_addrmode_is1:$addr)>;
1319 // extload -> zextload
1320 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1321 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1322 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1323 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1324 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1325 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1327 // If it's impossible to use [r,r] address mode for sextload, select to
1328 // ldr{b|h} + sxt{b|h} instead.
1329 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1330 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1331 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1332 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1333 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1334 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1335 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1336 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1337 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1338 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1339 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1340 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1342 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1343 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1344 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1345 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1346 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1347 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1348 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1349 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1351 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1352 (tLDRBi t_addrmode_is1:$src)>;
1353 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1354 (tLDRBr t_addrmode_rrs1:$src)>;
1355 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1356 (tLDRHi t_addrmode_is2:$src)>;
1357 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1358 (tLDRHr t_addrmode_rrs2:$src)>;
1359 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1360 (tLDRi t_addrmode_is4:$src)>;
1361 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1362 (tLDRr t_addrmode_rrs4:$src)>;
1363 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1364 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1365 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1366 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1367 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1368 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1369 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1370 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1371 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1372 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1373 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1374 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1376 // Large immediate handling.
1379 def : T1Pat<(i32 thumb_immshifted:$src),
1380 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1381 (thumb_immshifted_shamt imm:$src))>;
1383 def : T1Pat<(i32 imm0_255_comp:$src),
1384 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1386 // Pseudo instruction that combines ldr from constpool and add pc. This should
1387 // be expanded into two instructions late to allow if-conversion and
1389 let isReMaterializable = 1 in
1390 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1392 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1394 Requires<[IsThumb, IsThumb1Only]>;
1396 // Pseudo-instruction for merged POP and return.
1397 // FIXME: remove when we have a way to marking a MI with these properties.
1398 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1399 hasExtraDefRegAllocReq = 1 in
1400 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1402 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1404 // Indirect branch using "mov pc, $Rm"
1405 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1406 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1407 2, IIC_Br, [(brind GPR:$Rm)],
1408 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1412 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1413 // encoding is available on ARMv6K, but we don't differentiate that finely.
1414 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1417 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1418 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1419 // a useful extension and assembles to defined behaviour (the insn does
1421 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1422 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1424 // "neg" is and alias for "rsb rd, rn, #0"
1425 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1426 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1429 // Implied destination operand forms for shifts.
1430 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1431 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1432 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1433 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1434 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1435 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;