1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift. This uses
53 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54 // to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // ADR instruction labels.
70 def t_adrlabel : Operand<i32> {
71 let EncoderMethod = "getThumbAdrLabelOpValue";
74 // Scaled 4 immediate.
75 def t_imm_s4 : Operand<i32> {
76 let PrintMethod = "printThumbS4ImmOperand";
79 // Define Thumb specific addressing modes.
81 def t_brtarget : Operand<OtherVT> {
82 let EncoderMethod = "getThumbBRTargetOpValue";
85 def t_bcctarget : Operand<i32> {
86 let EncoderMethod = "getThumbBCCTargetOpValue";
89 def t_cbtarget : Operand<i32> {
90 let EncoderMethod = "getThumbCBTargetOpValue";
93 def t_bltarget : Operand<i32> {
94 let EncoderMethod = "getThumbBLTargetOpValue";
97 def t_blxtarget : Operand<i32> {
98 let EncoderMethod = "getThumbBLXTargetOpValue";
101 def MemModeRegThumbAsmOperand : AsmOperandClass {
102 let Name = "MemModeRegThumb";
103 let SuperClasses = [];
106 def MemModeImmThumbAsmOperand : AsmOperandClass {
107 let Name = "MemModeImmThumb";
108 let SuperClasses = [];
111 // t_addrmode_rr := reg + reg
113 def t_addrmode_rr : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
115 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
116 let PrintMethod = "printThumbAddrModeRROperand";
117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
120 // t_addrmode_rrs := reg + reg
122 def t_addrmode_rrs1 : Operand<i32>,
123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125 let PrintMethod = "printThumbAddrModeRROperand";
126 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127 let ParserMatchClass = MemModeRegThumbAsmOperand;
129 def t_addrmode_rrs2 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132 let PrintMethod = "printThumbAddrModeRROperand";
133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
134 let ParserMatchClass = MemModeRegThumbAsmOperand;
136 def t_addrmode_rrs4 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
138 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139 let PrintMethod = "printThumbAddrModeRROperand";
140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141 let ParserMatchClass = MemModeRegThumbAsmOperand;
144 // t_addrmode_is4 := reg + imm5 * 4
146 def t_addrmode_is4 : Operand<i32>,
147 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
148 let EncoderMethod = "getAddrModeISOpValue";
149 let PrintMethod = "printThumbAddrModeImm5S4Operand";
150 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
151 let ParserMatchClass = MemModeImmThumbAsmOperand;
154 // t_addrmode_is2 := reg + imm5 * 2
156 def t_addrmode_is2 : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
158 let EncoderMethod = "getAddrModeISOpValue";
159 let PrintMethod = "printThumbAddrModeImm5S2Operand";
160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
161 let ParserMatchClass = MemModeImmThumbAsmOperand;
164 // t_addrmode_is1 := reg + imm5
166 def t_addrmode_is1 : Operand<i32>,
167 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
168 let EncoderMethod = "getAddrModeISOpValue";
169 let PrintMethod = "printThumbAddrModeImm5S1Operand";
170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171 let ParserMatchClass = MemModeImmThumbAsmOperand;
174 // t_addrmode_sp := sp + imm8 * 4
176 def t_addrmode_sp : Operand<i32>,
177 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
178 let EncoderMethod = "getAddrModeThumbSPOpValue";
179 let PrintMethod = "printThumbAddrModeSPOperand";
180 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
181 let ParserMatchClass = MemModeImmThumbAsmOperand;
184 // t_addrmode_pc := <label> => pc + imm8 * 4
186 def t_addrmode_pc : Operand<i32> {
187 let EncoderMethod = "getAddrModePCOpValue";
188 let ParserMatchClass = MemModeImmThumbAsmOperand;
191 //===----------------------------------------------------------------------===//
192 // Miscellaneous Instructions.
195 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
196 // from removing one half of the matched pairs. That breaks PEI, which assumes
197 // these will always be in pairs, and asserts if it finds otherwise. Better way?
198 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
199 def tADJCALLSTACKUP :
200 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
201 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
202 Requires<[IsThumb, IsThumb1Only]>;
204 def tADJCALLSTACKDOWN :
205 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
206 [(ARMcallseq_start imm:$amt)]>,
207 Requires<[IsThumb, IsThumb1Only]>;
210 // T1Disassembly - A simple class to make encoding some disassembly patterns
211 // easier and less verbose.
212 class T1Disassembly<bits<2> op1, bits<8> op2>
213 : T1Encoding<0b101111> {
218 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
219 [/* For disassembly only; pattern left blank */]>,
220 T1Disassembly<0b11, 0x00>; // A8.6.110
222 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
223 [/* For disassembly only; pattern left blank */]>,
224 T1Disassembly<0b11, 0x10>; // A8.6.410
226 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
227 [/* For disassembly only; pattern left blank */]>,
228 T1Disassembly<0b11, 0x20>; // A8.6.408
230 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
231 [/* For disassembly only; pattern left blank */]>,
232 T1Disassembly<0b11, 0x30>; // A8.6.409
234 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
235 [/* For disassembly only; pattern left blank */]>,
236 T1Disassembly<0b11, 0x40>; // A8.6.157
238 // The i32imm operand $val can be used by a debugger to store more information
239 // about the breakpoint.
240 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
241 [/* For disassembly only; pattern left blank */]>,
242 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
248 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
249 [/* For disassembly only; pattern left blank */]>,
250 T1Encoding<0b101101> {
252 let Inst{9-5} = 0b10010;
254 let Inst{3} = 1; // Big-Endian
255 let Inst{2-0} = 0b000;
258 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
259 [/* For disassembly only; pattern left blank */]>,
260 T1Encoding<0b101101> {
262 let Inst{9-5} = 0b10010;
264 let Inst{3} = 0; // Little-Endian
265 let Inst{2-0} = 0b000;
268 // Change Processor State is a system instruction -- for disassembly only.
269 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
270 NoItinerary, "cps$imod $iflags",
271 [/* For disassembly only; pattern left blank */]>,
279 let Inst{2-0} = iflags;
282 // For both thumb1 and thumb2.
283 let isNotDuplicable = 1, isCodeGenOnly = 1 in
284 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
285 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
286 T1Special<{0,0,?,?}> {
289 let Inst{6-3} = 0b1111; // Rm = pc
293 // PC relative add (ADR).
294 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
295 "add\t$dst, pc, $rhs", []>,
296 T1Encoding<{1,0,1,0,0,?}> {
300 let Inst{10-8} = dst;
304 // ADD <Rd>, sp, #<imm8>
305 // This is rematerializable, which is particularly useful for taking the
306 // address of locals.
307 let isReMaterializable = 1 in
308 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
309 "add\t$dst, $sp, $rhs", []>,
310 T1Encoding<{1,0,1,0,1,?}> {
314 let Inst{10-8} = dst;
318 // ADD sp, sp, #<imm7>
319 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
320 "add\t$dst, $rhs", []>,
321 T1Misc<{0,0,0,0,0,?,?}> {
327 // SUB sp, sp, #<imm7>
328 // FIXME: The encoding and the ASM string don't match up.
329 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
330 "sub\t$dst, $rhs", []>,
331 T1Misc<{0,0,0,0,1,?,?}> {
338 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
339 "add\t$dst, $rhs", []>,
340 T1Special<{0,0,?,?}> {
341 // A8.6.9 Encoding T1
343 let Inst{7} = dst{3};
344 let Inst{6-3} = 0b1101;
345 let Inst{2-0} = dst{2-0};
349 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
350 "add\t$dst, $rhs", []>,
351 T1Special<{0,0,?,?}> {
352 // A8.6.9 Encoding T2
356 let Inst{2-0} = 0b101;
359 //===----------------------------------------------------------------------===//
360 // Control Flow Instructions.
363 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
364 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
366 T1Special<{1,1,0,?}> {
368 let Inst{6-3} = 0b1110; // Rm = lr
369 let Inst{2-0} = 0b000;
372 def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm",
373 [/* for disassembly only */]>,
374 T1Special<{1,1,0,?}> {
378 let Inst{2-0} = 0b000;
381 // Alternative return instruction used by vararg functions.
382 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
385 T1Special<{1,1,0,?}> {
389 let Inst{2-0} = 0b000;
394 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
395 def tBRIND : TI<(outs), (ins GPR:$Rm),
399 T1Special<{1,0,?,?}> {
402 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
404 let Inst{2-0} = 0b111;
408 // FIXME: remove when we have a way to marking a MI with these properties.
409 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
410 hasExtraDefRegAllocReq = 1 in
411 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
413 "pop${p}\t$regs", []>,
414 T1Misc<{1,1,0,?,?,?,?}> {
417 let Inst{8} = regs{15}; // registers = P:'0000000':register_list
418 let Inst{7-0} = regs{7-0};
421 // All calls clobber the non-callee saved registers. SP is marked as a use to
422 // prevent stack-pointer assignments that appear immediately before calls from
423 // potentially appearing dead.
425 // On non-Darwin platforms R9 is callee-saved.
426 Defs = [R0, R1, R2, R3, R12, LR,
427 D0, D1, D2, D3, D4, D5, D6, D7,
428 D16, D17, D18, D19, D20, D21, D22, D23,
429 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
431 // Also used for Thumb2
432 def tBL : TIx2<0b11110, 0b11, 1,
433 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
435 [(ARMtcall tglobaladdr:$func)]>,
436 Requires<[IsThumb, IsNotDarwin]> {
438 let Inst{25-16} = func{20-11};
441 let Inst{10-0} = func{10-0};
444 // ARMv5T and above, also used for Thumb2
445 def tBLXi : TIx2<0b11110, 0b11, 0,
446 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
448 [(ARMcall tglobaladdr:$func)]>,
449 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
451 let Inst{25-16} = func{20-11};
454 let Inst{10-1} = func{10-1};
455 let Inst{0} = 0; // func{0} is assumed zero
458 // Also used for Thumb2
459 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
461 [(ARMtcall GPR:$func)]>,
462 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
463 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
466 // FIXME: Should be a pseudo.
467 let isCodeGenOnly = 1 in
468 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
469 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
470 "mov\tlr, pc\n\tbx\t$func",
471 [(ARMcall_nolink tGPR:$func)]>,
472 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
476 // On Darwin R9 is call-clobbered.
477 // R7 is marked as a use to prevent frame-pointer assignments from being
478 // moved above / below calls.
479 Defs = [R0, R1, R2, R3, R9, R12, LR,
480 D0, D1, D2, D3, D4, D5, D6, D7,
481 D16, D17, D18, D19, D20, D21, D22, D23,
482 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR],
484 // Also used for Thumb2
485 def tBLr9 : TIx2<0b11110, 0b11, 1,
486 (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
487 IIC_Br, "bl${p}\t$func",
488 [(ARMtcall tglobaladdr:$func)]>,
489 Requires<[IsThumb, IsDarwin]> {
491 let Inst{25-16} = func{20-11};
494 let Inst{10-0} = func{10-0};
497 // ARMv5T and above, also used for Thumb2
498 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
499 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
500 IIC_Br, "blx${p}\t$func",
501 [(ARMcall tglobaladdr:$func)]>,
502 Requires<[IsThumb, HasV5T, IsDarwin]> {
504 let Inst{25-16} = func{20-11};
507 let Inst{10-1} = func{10-1};
508 let Inst{0} = 0; // func{0} is assumed zero
511 // Also used for Thumb2
512 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
514 [(ARMtcall GPR:$func)]>,
515 Requires<[IsThumb, HasV5T, IsDarwin]>,
516 T1Special<{1,1,1,?}> {
519 let Inst{6-3} = func;
520 let Inst{2-0} = 0b000;
524 let isCodeGenOnly = 1 in
525 // FIXME: Should be a pseudo.
526 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
527 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
528 "mov\tlr, pc\n\tbx\t$func",
529 [(ARMcall_nolink tGPR:$func)]>,
530 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
533 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
534 let isPredicable = 1 in
535 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
536 "b\t$target", [(br bb:$target)]>,
537 T1Encoding<{1,1,1,0,0,?}> {
539 let Inst{10-0} = target;
543 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
544 // the clobber of LR.
546 def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
547 Size4Bytes, IIC_Br, []>;
549 def tBR_JTr : tPseudoInst<(outs),
550 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
552 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
553 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
557 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
558 // a two-value operand where a dag node expects two operands. :(
559 let isBranch = 1, isTerminator = 1 in
560 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
562 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
563 T1Encoding<{1,1,0,1,?,?}> {
567 let Inst{7-0} = target;
570 // Compare and branch on zero / non-zero
571 let isBranch = 1, isTerminator = 1 in {
572 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
573 "cbz\t$Rn, $target", []>,
574 T1Misc<{0,0,?,1,?,?,?}> {
578 let Inst{9} = target{5};
579 let Inst{7-3} = target{4-0};
583 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
584 "cbnz\t$cmp, $target", []>,
585 T1Misc<{1,0,?,1,?,?,?}> {
589 let Inst{9} = target{5};
590 let Inst{7-3} = target{4-0};
595 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
596 // A8.6.16 B: Encoding T1
597 // If Inst{11-8} == 0b1111 then SEE SVC
598 let isCall = 1, Uses = [SP] in
599 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
600 "svc", "\t$imm", []>, Encoding16 {
602 let Inst{15-12} = 0b1101;
603 let Inst{11-8} = 0b1111;
607 // The assembler uses 0xDEFE for a trap instruction.
608 let isBarrier = 1, isTerminator = 1 in
609 def tTRAP : TI<(outs), (ins), IIC_Br,
610 "trap", [(trap)]>, Encoding16 {
614 //===----------------------------------------------------------------------===//
615 // Load Store Instructions.
618 // Loads: reg/reg and reg/imm5
619 let canFoldAsLoad = 1, isReMaterializable = 1 in
620 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
621 Operand AddrMode_r, Operand AddrMode_i,
622 AddrMode am, InstrItinClass itin_r,
623 InstrItinClass itin_i, string asm,
626 T1pILdStEncode<reg_opc,
627 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
628 am, itin_r, asm, "\t$Rt, $addr",
629 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
631 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
632 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
633 am, itin_i, asm, "\t$Rt, $addr",
634 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
636 // Stores: reg/reg and reg/imm5
637 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
638 Operand AddrMode_r, Operand AddrMode_i,
639 AddrMode am, InstrItinClass itin_r,
640 InstrItinClass itin_i, string asm,
643 T1pILdStEncode<reg_opc,
644 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
645 am, itin_r, asm, "\t$Rt, $addr",
646 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
648 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
649 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
650 am, itin_i, asm, "\t$Rt, $addr",
651 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
655 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
656 t_addrmode_is4, AddrModeT1_4,
657 IIC_iLoad_r, IIC_iLoad_i, "ldr",
658 UnOpFrag<(load node:$Src)>>;
661 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
662 t_addrmode_is1, AddrModeT1_1,
663 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
664 UnOpFrag<(zextloadi8 node:$Src)>>;
667 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
668 t_addrmode_is2, AddrModeT1_2,
669 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
670 UnOpFrag<(zextloadi16 node:$Src)>>;
672 let AddedComplexity = 10 in
673 def tLDRSB : // A8.6.80
674 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
675 AddrModeT1_1, IIC_iLoad_bh_r,
676 "ldrsb", "\t$dst, $addr",
677 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
679 let AddedComplexity = 10 in
680 def tLDRSH : // A8.6.84
681 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
682 AddrModeT1_2, IIC_iLoad_bh_r,
683 "ldrsh", "\t$dst, $addr",
684 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
686 let canFoldAsLoad = 1 in
687 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
688 "ldr", "\t$Rt, $addr",
689 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
694 let Inst{7-0} = addr;
697 // Special instruction for restore. It cannot clobber condition register
698 // when it's expanded by eliminateCallFramePseudoInstr().
699 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
700 // FIXME: Pseudo for tLDRspi
701 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
702 "ldr", "\t$dst, $addr", []>,
707 let Inst{7-0} = addr;
711 // FIXME: Use ldr.n to work around a Darwin assembler bug.
712 let canFoldAsLoad = 1, isReMaterializable = 1 in
713 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
714 "ldr", ".n\t$Rt, $addr",
715 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
716 T1Encoding<{0,1,0,0,1,?}> {
721 let Inst{7-0} = addr;
724 // A8.6.194 & A8.6.192
725 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
726 t_addrmode_is4, AddrModeT1_4,
727 IIC_iStore_r, IIC_iStore_i, "str",
728 BinOpFrag<(store node:$LHS, node:$RHS)>>;
730 // A8.6.197 & A8.6.195
731 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
732 t_addrmode_is1, AddrModeT1_1,
733 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
734 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
736 // A8.6.207 & A8.6.205
737 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
738 t_addrmode_is2, AddrModeT1_2,
739 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
740 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
743 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
744 "str", "\t$Rt, $addr",
745 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
750 let Inst{7-0} = addr;
753 let mayStore = 1, neverHasSideEffects = 1 in
754 // Special instruction for spill. It cannot clobber condition register when it's
755 // expanded by eliminateCallFramePseudoInstr().
756 // FIXME: Pseudo for tSTRspi
757 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
758 "str", "\t$src, $addr", []>,
763 let Inst{7-0} = addr;
766 //===----------------------------------------------------------------------===//
767 // Load / store multiple Instructions.
770 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
771 InstrItinClass itin_upd, bits<6> T1Enc,
774 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
775 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
780 let Inst{7-0} = regs;
783 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
784 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
789 let Inst{7-0} = regs;
793 // These require base address to be written back or one of the loaded regs.
794 let neverHasSideEffects = 1 in {
796 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
797 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
800 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
801 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
804 } // neverHasSideEffects
806 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
807 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
809 "pop${p}\t$regs", []>,
810 T1Misc<{1,1,0,?,?,?,?}> {
812 let Inst{8} = regs{15};
813 let Inst{7-0} = regs{7-0};
816 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
817 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
819 "push${p}\t$regs", []>,
820 T1Misc<{0,1,0,?,?,?,?}> {
822 let Inst{8} = regs{14};
823 let Inst{7-0} = regs{7-0};
826 //===----------------------------------------------------------------------===//
827 // Arithmetic Instructions.
830 // Helper classes for encoding T1pI patterns:
831 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
832 string opc, string asm, list<dag> pattern>
833 : T1pI<oops, iops, itin, opc, asm, pattern>,
834 T1DataProcessing<opA> {
840 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
841 string opc, string asm, list<dag> pattern>
842 : T1pI<oops, iops, itin, opc, asm, pattern>,
850 // Helper classes for encoding T1sI patterns:
851 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
852 string opc, string asm, list<dag> pattern>
853 : T1sI<oops, iops, itin, opc, asm, pattern>,
854 T1DataProcessing<opA> {
860 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
861 string opc, string asm, list<dag> pattern>
862 : T1sI<oops, iops, itin, opc, asm, pattern>,
871 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
872 string opc, string asm, list<dag> pattern>
873 : T1sI<oops, iops, itin, opc, asm, pattern>,
881 // Helper classes for encoding T1sIt patterns:
882 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
883 string opc, string asm, list<dag> pattern>
884 : T1sIt<oops, iops, itin, opc, asm, pattern>,
885 T1DataProcessing<opA> {
891 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
892 string opc, string asm, list<dag> pattern>
893 : T1sIt<oops, iops, itin, opc, asm, pattern>,
897 let Inst{10-8} = Rdn;
898 let Inst{7-0} = imm8;
901 // Add with carry register
902 let isCommutable = 1, Uses = [CPSR] in
904 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
905 "adc", "\t$Rdn, $Rm",
906 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
909 def tADDi3 : // A8.6.4 T1
910 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
911 "add", "\t$Rd, $Rm, $imm3",
912 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
914 let Inst{8-6} = imm3;
917 def tADDi8 : // A8.6.4 T2
918 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
920 "add", "\t$Rdn, $imm8",
921 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
924 let isCommutable = 1 in
925 def tADDrr : // A8.6.6 T1
926 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
928 "add", "\t$Rd, $Rn, $Rm",
929 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
931 let neverHasSideEffects = 1 in
932 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
933 "add", "\t$Rdn, $Rm", []>,
934 T1Special<{0,0,?,?}> {
938 let Inst{7} = Rdn{3};
940 let Inst{2-0} = Rdn{2-0};
944 let isCommutable = 1 in
945 def tAND : // A8.6.12
946 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
948 "and", "\t$Rdn, $Rm",
949 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
952 def tASRri : // A8.6.14
953 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
955 "asr", "\t$Rd, $Rm, $imm5",
956 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
958 let Inst{10-6} = imm5;
962 def tASRrr : // A8.6.15
963 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
965 "asr", "\t$Rdn, $Rm",
966 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
969 def tBIC : // A8.6.20
970 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
972 "bic", "\t$Rdn, $Rm",
973 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
976 let isCompare = 1, Defs = [CPSR] in {
977 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
978 // Compare-to-zero still works out, just not the relationals
979 //def tCMN : // A8.6.33
980 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
982 // "cmn", "\t$lhs, $rhs",
983 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
985 def tCMNz : // A8.6.33
986 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
989 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
991 } // isCompare = 1, Defs = [CPSR]
994 let isCompare = 1, Defs = [CPSR] in {
995 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
996 "cmp", "\t$Rn, $imm8",
997 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
998 T1General<{1,0,1,?,?}> {
1002 let Inst{10-8} = Rn;
1003 let Inst{7-0} = imm8;
1007 def tCMPr : // A8.6.36 T1
1008 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1010 "cmp", "\t$Rn, $Rm",
1011 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
1013 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1014 "cmp", "\t$Rn, $Rm", []>,
1015 T1Special<{0,1,?,?}> {
1019 let Inst{7} = Rn{3};
1021 let Inst{2-0} = Rn{2-0};
1023 } // isCompare = 1, Defs = [CPSR]
1027 let isCommutable = 1 in
1028 def tEOR : // A8.6.45
1029 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1031 "eor", "\t$Rdn, $Rm",
1032 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1035 def tLSLri : // A8.6.88
1036 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1038 "lsl", "\t$Rd, $Rm, $imm5",
1039 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1041 let Inst{10-6} = imm5;
1045 def tLSLrr : // A8.6.89
1046 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1048 "lsl", "\t$Rdn, $Rm",
1049 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1052 def tLSRri : // A8.6.90
1053 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1055 "lsr", "\t$Rd, $Rm, $imm5",
1056 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1058 let Inst{10-6} = imm5;
1062 def tLSRrr : // A8.6.91
1063 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1065 "lsr", "\t$Rdn, $Rm",
1066 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1069 let isMoveImm = 1 in
1070 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
1071 "mov", "\t$Rd, $imm8",
1072 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1073 T1General<{1,0,0,?,?}> {
1077 let Inst{10-8} = Rd;
1078 let Inst{7-0} = imm8;
1081 // TODO: A7-73: MOV(2) - mov setting flag.
1083 let neverHasSideEffects = 1 in {
1084 // FIXME: Make this predicable.
1085 def tMOVr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1086 "mov\t$Rd, $Rm", []>,
1091 // Bits {7-6} are encoded by the T1Special value.
1092 let Inst{5-3} = Rm{2-0};
1093 let Inst{2-0} = Rd{2-0};
1095 let Defs = [CPSR] in
1096 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1097 "movs\t$Rd, $Rm", []>, Encoding16 {
1101 let Inst{15-6} = 0b0000000000;
1106 // FIXME: Make these predicable.
1107 def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1108 "mov\t$Rd, $Rm", []>,
1109 T1Special<{1,0,0,?}> {
1113 // Bit {7} is encoded by the T1Special value.
1115 let Inst{2-0} = Rd{2-0};
1117 def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1118 "mov\t$Rd, $Rm", []>,
1119 T1Special<{1,0,?,0}> {
1123 // Bit {6} is encoded by the T1Special value.
1124 let Inst{7} = Rd{3};
1125 let Inst{5-3} = Rm{2-0};
1126 let Inst{2-0} = Rd{2-0};
1128 def tMOVgpr2gpr : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1129 "mov\t$Rd, $Rm", []>,
1130 T1Special<{1,0,?,?}> {
1134 let Inst{7} = Rd{3};
1136 let Inst{2-0} = Rd{2-0};
1138 } // neverHasSideEffects
1140 // Multiply register
1141 let isCommutable = 1 in
1142 def tMUL : // A8.6.105 T1
1143 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1145 "mul", "\t$Rdn, $Rm, $Rdn",
1146 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1148 // Move inverse register
1149 def tMVN : // A8.6.107
1150 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1151 "mvn", "\t$Rd, $Rn",
1152 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1154 // Bitwise or register
1155 let isCommutable = 1 in
1156 def tORR : // A8.6.114
1157 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1159 "orr", "\t$Rdn, $Rm",
1160 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1163 def tREV : // A8.6.134
1164 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1166 "rev", "\t$Rd, $Rm",
1167 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1168 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1170 def tREV16 : // A8.6.135
1171 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1173 "rev16", "\t$Rd, $Rm",
1175 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1176 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1177 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1178 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1179 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1181 def tREVSH : // A8.6.136
1182 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1184 "revsh", "\t$Rd, $Rm",
1187 (or (srl tGPR:$Rm, (i32 8)),
1188 (shl tGPR:$Rm, (i32 8))), i16))]>,
1189 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1191 def : T1Pat<(sext_inreg (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1192 (shl tGPR:$Rm, (i32 8))), i16),
1194 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1196 def : T1Pat<(sra (bswap tGPR:$Rm), (i32 16)), (tREVSH tGPR:$Rm)>,
1197 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1199 // Rotate right register
1200 def tROR : // A8.6.139
1201 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1203 "ror", "\t$Rdn, $Rm",
1204 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1207 def tRSB : // A8.6.141
1208 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1210 "rsb", "\t$Rd, $Rn, #0",
1211 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1213 // Subtract with carry register
1214 let Uses = [CPSR] in
1215 def tSBC : // A8.6.151
1216 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1218 "sbc", "\t$Rdn, $Rm",
1219 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1221 // Subtract immediate
1222 def tSUBi3 : // A8.6.210 T1
1223 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1225 "sub", "\t$Rd, $Rm, $imm3",
1226 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1228 let Inst{8-6} = imm3;
1231 def tSUBi8 : // A8.6.210 T2
1232 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1234 "sub", "\t$Rdn, $imm8",
1235 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1237 // Subtract register
1238 def tSUBrr : // A8.6.212
1239 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1241 "sub", "\t$Rd, $Rn, $Rm",
1242 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1244 // TODO: A7-96: STMIA - store multiple.
1247 def tSXTB : // A8.6.222
1248 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1250 "sxtb", "\t$Rd, $Rm",
1251 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1252 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1254 // Sign-extend short
1255 def tSXTH : // A8.6.224
1256 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1258 "sxth", "\t$Rd, $Rm",
1259 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1260 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1263 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1264 def tTST : // A8.6.230
1265 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1266 "tst", "\t$Rn, $Rm",
1267 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1270 def tUXTB : // A8.6.262
1271 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1273 "uxtb", "\t$Rd, $Rm",
1274 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1275 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1277 // Zero-extend short
1278 def tUXTH : // A8.6.264
1279 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1281 "uxth", "\t$Rd, $Rm",
1282 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1283 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1285 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1286 // Expanded after instruction selection into a branch sequence.
1287 let usesCustomInserter = 1 in // Expanded after instruction selection.
1288 def tMOVCCr_pseudo :
1289 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1291 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1294 // 16-bit movcc in IT blocks for Thumb2.
1295 let neverHasSideEffects = 1 in {
1296 def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1297 "mov", "\t$Rdn, $Rm", []>,
1298 T1Special<{1,0,?,?}> {
1301 let Inst{7} = Rdn{3};
1303 let Inst{2-0} = Rdn{2-0};
1306 let isMoveImm = 1 in
1307 def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1308 "mov", "\t$Rdn, $Rm", []>,
1309 T1General<{1,0,0,?,?}> {
1312 let Inst{10-8} = Rdn;
1316 } // neverHasSideEffects
1318 // tLEApcrel - Load a pc-relative address into a register without offending the
1321 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1322 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1323 T1Encoding<{1,0,1,0,0,?}> {
1326 let Inst{10-8} = Rd;
1327 let Inst{7-0} = addr;
1330 let neverHasSideEffects = 1, isReMaterializable = 1 in
1331 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1332 Size2Bytes, IIC_iALUi, []>;
1334 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1335 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1336 Size2Bytes, IIC_iALUi, []>;
1338 //===----------------------------------------------------------------------===//
1339 // Move between coprocessor and ARM core register -- for disassembly only
1342 class tMovRCopro<string opc, bit direction, dag oops, dag iops>
1343 : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1344 [/* For disassembly only; pattern left blank */]> {
1345 let Inst{27-24} = 0b1110;
1346 let Inst{20} = direction;
1356 let Inst{15-12} = Rt;
1357 let Inst{11-8} = cop;
1358 let Inst{23-21} = opc1;
1359 let Inst{7-5} = opc2;
1360 let Inst{3-0} = CRm;
1361 let Inst{19-16} = CRn;
1364 def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
1365 (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
1366 c_imm:$CRm, i32imm:$opc2)>;
1367 def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
1368 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn,
1369 c_imm:$CRm, i32imm:$opc2)>;
1371 class tMovRRCopro<string opc, bit direction>
1372 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1373 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
1374 [/* For disassembly only; pattern left blank */]> {
1375 let Inst{27-24} = 0b1100;
1376 let Inst{23-21} = 0b010;
1377 let Inst{20} = direction;
1385 let Inst{15-12} = Rt;
1386 let Inst{19-16} = Rt2;
1387 let Inst{11-8} = cop;
1388 let Inst{7-4} = opc1;
1389 let Inst{3-0} = CRm;
1392 def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
1393 def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1395 //===----------------------------------------------------------------------===//
1396 // Other Coprocessor Instructions. For disassembly only.
1398 def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1399 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1400 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1401 [/* For disassembly only; pattern left blank */]> {
1402 let Inst{27-24} = 0b1110;
1411 let Inst{3-0} = CRm;
1413 let Inst{7-5} = opc2;
1414 let Inst{11-8} = cop;
1415 let Inst{15-12} = CRd;
1416 let Inst{19-16} = CRn;
1417 let Inst{23-20} = opc1;
1420 //===----------------------------------------------------------------------===//
1424 // __aeabi_read_tp preserves the registers r1-r3.
1425 let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1426 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1427 "bl\t__aeabi_read_tp",
1428 [(set R0, ARMthread_pointer)]> {
1429 // Encoding is 0xf7fffffe.
1430 let Inst = 0xf7fffffe;
1433 //===----------------------------------------------------------------------===//
1434 // SJLJ Exception handling intrinsics
1437 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1438 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1439 // from some other function to get here, and we're using the stack frame for the
1440 // containing function to save/restore registers, we can't keep anything live in
1441 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1442 // tromped upon when we get here from a longjmp(). We force everthing out of
1443 // registers except for our own input by listing the relevant registers in
1444 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1445 // preserve all of the callee-saved resgisters, which is exactly what we want.
1446 // $val is a scratch register for our use.
1447 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ],
1448 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1449 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1450 AddrModeNone, SizeSpecial, NoItinerary, "","",
1451 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1453 // FIXME: Non-Darwin version(s)
1454 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1455 Defs = [ R7, LR, SP ] in
1456 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1457 AddrModeNone, SizeSpecial, IndexModeNone,
1458 Pseudo, NoItinerary, "", "",
1459 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1460 Requires<[IsThumb, IsDarwin]>;
1462 //===----------------------------------------------------------------------===//
1463 // Non-Instruction Patterns
1467 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1468 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1469 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1470 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1473 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1474 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1475 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1476 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1477 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1478 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1480 // Subtract with carry
1481 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1482 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1483 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1484 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1485 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1486 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1488 // ConstantPool, GlobalAddress
1489 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1490 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1493 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1494 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1497 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1498 Requires<[IsThumb, IsNotDarwin]>;
1499 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1500 Requires<[IsThumb, IsDarwin]>;
1502 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1503 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1504 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1505 Requires<[IsThumb, HasV5T, IsDarwin]>;
1507 // Indirect calls to ARM routines
1508 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1509 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1510 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1511 Requires<[IsThumb, HasV5T, IsDarwin]>;
1513 // zextload i1 -> zextload i8
1514 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1515 (tLDRBr t_addrmode_rrs1:$addr)>;
1516 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1517 (tLDRBi t_addrmode_is1:$addr)>;
1519 // extload -> zextload
1520 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1521 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1522 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1523 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1524 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1525 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1527 // If it's impossible to use [r,r] address mode for sextload, select to
1528 // ldr{b|h} + sxt{b|h} instead.
1529 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1530 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1531 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1532 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1533 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1534 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1535 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1536 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1537 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1538 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1539 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1540 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1542 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1543 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1544 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1545 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1546 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1547 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1548 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1549 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1551 // Large immediate handling.
1554 def : T1Pat<(i32 thumb_immshifted:$src),
1555 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1556 (thumb_immshifted_shamt imm:$src))>;
1558 def : T1Pat<(i32 imm0_255_comp:$src),
1559 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1561 // Pseudo instruction that combines ldr from constpool and add pc. This should
1562 // be expanded into two instructions late to allow if-conversion and
1564 let isReMaterializable = 1 in
1565 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1567 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1569 Requires<[IsThumb, IsThumb1Only]>;