1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : ImmLeaf<i32, [{
31 return Imm >= 0 && Imm < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : ImmLeaf<i32, [{
38 return Imm >= 0 && Imm < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : ImmLeaf<i32, [{
45 return Imm >= 8 && Imm < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift. This uses
53 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54 // to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // ADR instruction labels.
70 def t_adrlabel : Operand<i32> {
71 let EncoderMethod = "getThumbAdrLabelOpValue";
74 // Scaled 4 immediate.
75 def t_imm_s4 : Operand<i32> {
76 let PrintMethod = "printThumbS4ImmOperand";
79 // Define Thumb specific addressing modes.
81 def t_brtarget : Operand<OtherVT> {
82 let EncoderMethod = "getThumbBRTargetOpValue";
85 def t_bcctarget : Operand<i32> {
86 let EncoderMethod = "getThumbBCCTargetOpValue";
89 def t_cbtarget : Operand<i32> {
90 let EncoderMethod = "getThumbCBTargetOpValue";
93 def t_bltarget : Operand<i32> {
94 let EncoderMethod = "getThumbBLTargetOpValue";
97 def t_blxtarget : Operand<i32> {
98 let EncoderMethod = "getThumbBLXTargetOpValue";
101 def MemModeRegThumbAsmOperand : AsmOperandClass {
102 let Name = "MemModeRegThumb";
103 let SuperClasses = [];
106 def MemModeImmThumbAsmOperand : AsmOperandClass {
107 let Name = "MemModeImmThumb";
108 let SuperClasses = [];
111 // t_addrmode_rr := reg + reg
113 def t_addrmode_rr : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
115 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
116 let PrintMethod = "printThumbAddrModeRROperand";
117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
120 // t_addrmode_rrs := reg + reg
122 def t_addrmode_rrs1 : Operand<i32>,
123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125 let PrintMethod = "printThumbAddrModeRROperand";
126 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127 let ParserMatchClass = MemModeRegThumbAsmOperand;
129 def t_addrmode_rrs2 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132 let PrintMethod = "printThumbAddrModeRROperand";
133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
134 let ParserMatchClass = MemModeRegThumbAsmOperand;
136 def t_addrmode_rrs4 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
138 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139 let PrintMethod = "printThumbAddrModeRROperand";
140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141 let ParserMatchClass = MemModeRegThumbAsmOperand;
144 // t_addrmode_is4 := reg + imm5 * 4
146 def t_addrmode_is4 : Operand<i32>,
147 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
148 let EncoderMethod = "getAddrModeISOpValue";
149 let PrintMethod = "printThumbAddrModeImm5S4Operand";
150 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
151 let ParserMatchClass = MemModeImmThumbAsmOperand;
154 // t_addrmode_is2 := reg + imm5 * 2
156 def t_addrmode_is2 : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
158 let EncoderMethod = "getAddrModeISOpValue";
159 let PrintMethod = "printThumbAddrModeImm5S2Operand";
160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
161 let ParserMatchClass = MemModeImmThumbAsmOperand;
164 // t_addrmode_is1 := reg + imm5
166 def t_addrmode_is1 : Operand<i32>,
167 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
168 let EncoderMethod = "getAddrModeISOpValue";
169 let PrintMethod = "printThumbAddrModeImm5S1Operand";
170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171 let ParserMatchClass = MemModeImmThumbAsmOperand;
174 // t_addrmode_sp := sp + imm8 * 4
176 def t_addrmode_sp : Operand<i32>,
177 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
178 let EncoderMethod = "getAddrModeThumbSPOpValue";
179 let PrintMethod = "printThumbAddrModeSPOperand";
180 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
181 let ParserMatchClass = MemModeImmThumbAsmOperand;
184 // t_addrmode_pc := <label> => pc + imm8 * 4
186 def t_addrmode_pc : Operand<i32> {
187 let EncoderMethod = "getAddrModePCOpValue";
188 let ParserMatchClass = MemModeImmThumbAsmOperand;
191 //===----------------------------------------------------------------------===//
192 // Miscellaneous Instructions.
195 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
196 // from removing one half of the matched pairs. That breaks PEI, which assumes
197 // these will always be in pairs, and asserts if it finds otherwise. Better way?
198 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
199 def tADJCALLSTACKUP :
200 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
201 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
202 Requires<[IsThumb, IsThumb1Only]>;
204 def tADJCALLSTACKDOWN :
205 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
206 [(ARMcallseq_start imm:$amt)]>,
207 Requires<[IsThumb, IsThumb1Only]>;
210 // T1Disassembly - A simple class to make encoding some disassembly patterns
211 // easier and less verbose.
212 class T1Disassembly<bits<2> op1, bits<8> op2>
213 : T1Encoding<0b101111> {
218 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
219 [/* For disassembly only; pattern left blank */]>,
220 T1Disassembly<0b11, 0x00>; // A8.6.110
222 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
223 [/* For disassembly only; pattern left blank */]>,
224 T1Disassembly<0b11, 0x10>; // A8.6.410
226 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
227 [/* For disassembly only; pattern left blank */]>,
228 T1Disassembly<0b11, 0x20>; // A8.6.408
230 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
231 [/* For disassembly only; pattern left blank */]>,
232 T1Disassembly<0b11, 0x30>; // A8.6.409
234 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
235 [/* For disassembly only; pattern left blank */]>,
236 T1Disassembly<0b11, 0x40>; // A8.6.157
238 // The i32imm operand $val can be used by a debugger to store more information
239 // about the breakpoint.
240 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
241 [/* For disassembly only; pattern left blank */]>,
242 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
248 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
249 [/* For disassembly only; pattern left blank */]>,
250 T1Encoding<0b101101> {
252 let Inst{9-5} = 0b10010;
254 let Inst{3} = 1; // Big-Endian
255 let Inst{2-0} = 0b000;
258 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
259 [/* For disassembly only; pattern left blank */]>,
260 T1Encoding<0b101101> {
262 let Inst{9-5} = 0b10010;
264 let Inst{3} = 0; // Little-Endian
265 let Inst{2-0} = 0b000;
268 // Change Processor State is a system instruction -- for disassembly only.
269 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
270 NoItinerary, "cps$imod $iflags",
271 [/* For disassembly only; pattern left blank */]>,
279 let Inst{2-0} = iflags;
282 // For both thumb1 and thumb2.
283 let isNotDuplicable = 1, isCodeGenOnly = 1 in
284 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
285 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
286 T1Special<{0,0,?,?}> {
289 let Inst{6-3} = 0b1111; // Rm = pc
293 // PC relative add (ADR).
294 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
295 "add\t$dst, pc, $rhs", []>,
296 T1Encoding<{1,0,1,0,0,?}> {
300 let Inst{10-8} = dst;
304 // ADD <Rd>, sp, #<imm8>
305 // This is rematerializable, which is particularly useful for taking the
306 // address of locals.
307 let isReMaterializable = 1 in
308 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
309 "add\t$dst, $sp, $rhs", []>,
310 T1Encoding<{1,0,1,0,1,?}> {
314 let Inst{10-8} = dst;
318 // ADD sp, sp, #<imm7>
319 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
320 "add\t$dst, $rhs", []>,
321 T1Misc<{0,0,0,0,0,?,?}> {
327 // SUB sp, sp, #<imm7>
328 // FIXME: The encoding and the ASM string don't match up.
329 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
330 "sub\t$dst, $rhs", []>,
331 T1Misc<{0,0,0,0,1,?,?}> {
338 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
339 "add\t$dst, $rhs", []>,
340 T1Special<{0,0,?,?}> {
341 // A8.6.9 Encoding T1
343 let Inst{7} = dst{3};
344 let Inst{6-3} = 0b1101;
345 let Inst{2-0} = dst{2-0};
349 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
350 "add\t$dst, $rhs", []>,
351 T1Special<{0,0,?,?}> {
352 // A8.6.9 Encoding T2
356 let Inst{2-0} = 0b101;
359 //===----------------------------------------------------------------------===//
360 // Control Flow Instructions.
363 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
364 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
366 T1Special<{1,1,0,?}> {
368 let Inst{6-3} = 0b1110; // Rm = lr
369 let Inst{2-0} = 0b000;
372 def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm",
373 [/* for disassembly only */]>,
374 T1Special<{1,1,0,?}> {
378 let Inst{2-0} = 0b000;
381 // Alternative return instruction used by vararg functions.
382 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
385 T1Special<{1,1,0,?}> {
389 let Inst{2-0} = 0b000;
394 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
395 def tBRIND : TI<(outs), (ins GPR:$Rm),
399 T1Special<{1,0,?,?}> {
402 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc
404 let Inst{2-0} = 0b111;
408 // FIXME: remove when we have a way to marking a MI with these properties.
409 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
410 hasExtraDefRegAllocReq = 1 in
411 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
413 "pop${p}\t$regs", []>,
414 T1Misc<{1,1,0,?,?,?,?}> {
417 let Inst{8} = regs{15}; // registers = P:'0000000':register_list
418 let Inst{7-0} = regs{7-0};
421 // All calls clobber the non-callee saved registers. SP is marked as a use to
422 // prevent stack-pointer assignments that appear immediately before calls from
423 // potentially appearing dead.
425 // On non-Darwin platforms R9 is callee-saved.
426 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
428 // Also used for Thumb2
429 def tBL : TIx2<0b11110, 0b11, 1,
430 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
432 [(ARMtcall tglobaladdr:$func)]>,
433 Requires<[IsThumb, IsNotDarwin]> {
435 let Inst{25-16} = func{20-11};
438 let Inst{10-0} = func{10-0};
441 // ARMv5T and above, also used for Thumb2
442 def tBLXi : TIx2<0b11110, 0b11, 0,
443 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
445 [(ARMcall tglobaladdr:$func)]>,
446 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
448 let Inst{25-16} = func{20-11};
451 let Inst{10-1} = func{10-1};
452 let Inst{0} = 0; // func{0} is assumed zero
455 // Also used for Thumb2
456 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
458 [(ARMtcall GPR:$func)]>,
459 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
460 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
462 let Inst{6-3} = func;
463 let Inst{2-0} = 0b000;
467 // FIXME: Should be a pseudo.
468 let isCodeGenOnly = 1 in
469 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
470 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
471 "mov\tlr, pc\n\tbx\t$func",
472 [(ARMcall_nolink tGPR:$func)]>,
473 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
477 // On Darwin R9 is call-clobbered.
478 // R7 is marked as a use to prevent frame-pointer assignments from being
479 // moved above / below calls.
480 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
482 // Also used for Thumb2
483 def tBLr9 : TIx2<0b11110, 0b11, 1,
484 (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
485 IIC_Br, "bl${p}\t$func",
486 [(ARMtcall tglobaladdr:$func)]>,
487 Requires<[IsThumb, IsDarwin]> {
489 let Inst{25-16} = func{20-11};
492 let Inst{10-0} = func{10-0};
495 // ARMv5T and above, also used for Thumb2
496 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
497 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
498 IIC_Br, "blx${p}\t$func",
499 [(ARMcall tglobaladdr:$func)]>,
500 Requires<[IsThumb, HasV5T, IsDarwin]> {
502 let Inst{25-16} = func{20-11};
505 let Inst{10-1} = func{10-1};
506 let Inst{0} = 0; // func{0} is assumed zero
509 // Also used for Thumb2
510 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
512 [(ARMtcall GPR:$func)]>,
513 Requires<[IsThumb, HasV5T, IsDarwin]>,
514 T1Special<{1,1,1,?}> {
517 let Inst{6-3} = func;
518 let Inst{2-0} = 0b000;
522 let isCodeGenOnly = 1 in
523 // FIXME: Should be a pseudo.
524 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
525 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
526 "mov\tlr, pc\n\tbx\t$func",
527 [(ARMcall_nolink tGPR:$func)]>,
528 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
531 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
532 let isPredicable = 1 in
533 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
534 "b\t$target", [(br bb:$target)]>,
535 T1Encoding<{1,1,1,0,0,?}> {
537 let Inst{10-0} = target;
541 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
542 // the clobber of LR.
544 def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
545 Size4Bytes, IIC_Br, []>;
547 def tBR_JTr : tPseudoInst<(outs),
548 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
550 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
551 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
555 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
556 // a two-value operand where a dag node expects two operands. :(
557 let isBranch = 1, isTerminator = 1 in
558 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
560 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
561 T1Encoding<{1,1,0,1,?,?}> {
565 let Inst{7-0} = target;
568 // Compare and branch on zero / non-zero
569 let isBranch = 1, isTerminator = 1 in {
570 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
571 "cbz\t$Rn, $target", []>,
572 T1Misc<{0,0,?,1,?,?,?}> {
576 let Inst{9} = target{5};
577 let Inst{7-3} = target{4-0};
581 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
582 "cbnz\t$cmp, $target", []>,
583 T1Misc<{1,0,?,1,?,?,?}> {
587 let Inst{9} = target{5};
588 let Inst{7-3} = target{4-0};
593 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
594 // A8.6.16 B: Encoding T1
595 // If Inst{11-8} == 0b1111 then SEE SVC
596 let isCall = 1, Uses = [SP] in
597 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
598 "svc", "\t$imm", []>, Encoding16 {
600 let Inst{15-12} = 0b1101;
601 let Inst{11-8} = 0b1111;
605 // The assembler uses 0xDEFE for a trap instruction.
606 let isBarrier = 1, isTerminator = 1 in
607 def tTRAP : TI<(outs), (ins), IIC_Br,
608 "trap", [(trap)]>, Encoding16 {
612 //===----------------------------------------------------------------------===//
613 // Load Store Instructions.
616 // Loads: reg/reg and reg/imm5
617 let canFoldAsLoad = 1, isReMaterializable = 1 in
618 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
619 Operand AddrMode_r, Operand AddrMode_i,
620 AddrMode am, InstrItinClass itin_r,
621 InstrItinClass itin_i, string asm,
624 T1pILdStEncode<reg_opc,
625 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
626 am, itin_r, asm, "\t$Rt, $addr",
627 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
629 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
630 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
631 am, itin_i, asm, "\t$Rt, $addr",
632 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
634 // Stores: reg/reg and reg/imm5
635 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
636 Operand AddrMode_r, Operand AddrMode_i,
637 AddrMode am, InstrItinClass itin_r,
638 InstrItinClass itin_i, string asm,
641 T1pILdStEncode<reg_opc,
642 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
643 am, itin_r, asm, "\t$Rt, $addr",
644 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
646 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
647 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
648 am, itin_i, asm, "\t$Rt, $addr",
649 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
653 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
654 t_addrmode_is4, AddrModeT1_4,
655 IIC_iLoad_r, IIC_iLoad_i, "ldr",
656 UnOpFrag<(load node:$Src)>>;
659 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
660 t_addrmode_is1, AddrModeT1_1,
661 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
662 UnOpFrag<(zextloadi8 node:$Src)>>;
665 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
666 t_addrmode_is2, AddrModeT1_2,
667 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
668 UnOpFrag<(zextloadi16 node:$Src)>>;
670 let AddedComplexity = 10 in
671 def tLDRSB : // A8.6.80
672 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
673 AddrModeT1_1, IIC_iLoad_bh_r,
674 "ldrsb", "\t$dst, $addr",
675 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
677 let AddedComplexity = 10 in
678 def tLDRSH : // A8.6.84
679 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
680 AddrModeT1_2, IIC_iLoad_bh_r,
681 "ldrsh", "\t$dst, $addr",
682 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
684 let canFoldAsLoad = 1 in
685 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
686 "ldr", "\t$Rt, $addr",
687 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
692 let Inst{7-0} = addr;
695 // Special instruction for restore. It cannot clobber condition register
696 // when it's expanded by eliminateCallFramePseudoInstr().
697 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
698 // FIXME: Pseudo for tLDRspi
699 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
700 "ldr", "\t$dst, $addr", []>,
705 let Inst{7-0} = addr;
709 // FIXME: Use ldr.n to work around a Darwin assembler bug.
710 let canFoldAsLoad = 1, isReMaterializable = 1 in
711 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
712 "ldr", ".n\t$Rt, $addr",
713 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
714 T1Encoding<{0,1,0,0,1,?}> {
719 let Inst{7-0} = addr;
722 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
723 // For disassembly use only.
724 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
725 "ldr", "\t$Rt, $addr",
726 [/* disassembly only */]>,
727 T1Encoding<{0,1,0,0,1,?}> {
732 let Inst{7-0} = addr;
735 // A8.6.194 & A8.6.192
736 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
737 t_addrmode_is4, AddrModeT1_4,
738 IIC_iStore_r, IIC_iStore_i, "str",
739 BinOpFrag<(store node:$LHS, node:$RHS)>>;
741 // A8.6.197 & A8.6.195
742 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
743 t_addrmode_is1, AddrModeT1_1,
744 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
745 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
747 // A8.6.207 & A8.6.205
748 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
749 t_addrmode_is2, AddrModeT1_2,
750 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
751 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
754 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
755 "str", "\t$Rt, $addr",
756 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
761 let Inst{7-0} = addr;
764 let mayStore = 1, neverHasSideEffects = 1 in
765 // Special instruction for spill. It cannot clobber condition register when it's
766 // expanded by eliminateCallFramePseudoInstr().
767 // FIXME: Pseudo for tSTRspi
768 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
769 "str", "\t$src, $addr", []>,
774 let Inst{7-0} = addr;
777 //===----------------------------------------------------------------------===//
778 // Load / store multiple Instructions.
781 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
782 InstrItinClass itin_upd, bits<6> T1Enc,
785 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
786 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
791 let Inst{7-0} = regs;
794 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
795 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
800 let Inst{7-0} = regs;
804 // These require base address to be written back or one of the loaded regs.
805 let neverHasSideEffects = 1 in {
807 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
808 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
811 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
812 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
815 } // neverHasSideEffects
817 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
818 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
820 "pop${p}\t$regs", []>,
821 T1Misc<{1,1,0,?,?,?,?}> {
823 let Inst{8} = regs{15};
824 let Inst{7-0} = regs{7-0};
827 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
828 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
830 "push${p}\t$regs", []>,
831 T1Misc<{0,1,0,?,?,?,?}> {
833 let Inst{8} = regs{14};
834 let Inst{7-0} = regs{7-0};
837 //===----------------------------------------------------------------------===//
838 // Arithmetic Instructions.
841 // Helper classes for encoding T1pI patterns:
842 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
843 string opc, string asm, list<dag> pattern>
844 : T1pI<oops, iops, itin, opc, asm, pattern>,
845 T1DataProcessing<opA> {
851 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
852 string opc, string asm, list<dag> pattern>
853 : T1pI<oops, iops, itin, opc, asm, pattern>,
861 // Helper classes for encoding T1sI patterns:
862 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
863 string opc, string asm, list<dag> pattern>
864 : T1sI<oops, iops, itin, opc, asm, pattern>,
865 T1DataProcessing<opA> {
871 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
872 string opc, string asm, list<dag> pattern>
873 : T1sI<oops, iops, itin, opc, asm, pattern>,
882 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
883 string opc, string asm, list<dag> pattern>
884 : T1sI<oops, iops, itin, opc, asm, pattern>,
892 // Helper classes for encoding T1sIt patterns:
893 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
894 string opc, string asm, list<dag> pattern>
895 : T1sIt<oops, iops, itin, opc, asm, pattern>,
896 T1DataProcessing<opA> {
902 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
903 string opc, string asm, list<dag> pattern>
904 : T1sIt<oops, iops, itin, opc, asm, pattern>,
908 let Inst{10-8} = Rdn;
909 let Inst{7-0} = imm8;
912 // Add with carry register
913 let isCommutable = 1, Uses = [CPSR] in
915 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
916 "adc", "\t$Rdn, $Rm",
917 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
920 def tADDi3 : // A8.6.4 T1
921 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
922 "add", "\t$Rd, $Rm, $imm3",
923 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
925 let Inst{8-6} = imm3;
928 def tADDi8 : // A8.6.4 T2
929 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
931 "add", "\t$Rdn, $imm8",
932 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
935 let isCommutable = 1 in
936 def tADDrr : // A8.6.6 T1
937 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
939 "add", "\t$Rd, $Rn, $Rm",
940 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
942 let neverHasSideEffects = 1 in
943 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
944 "add", "\t$Rdn, $Rm", []>,
945 T1Special<{0,0,?,?}> {
949 let Inst{7} = Rdn{3};
951 let Inst{2-0} = Rdn{2-0};
955 let isCommutable = 1 in
956 def tAND : // A8.6.12
957 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
959 "and", "\t$Rdn, $Rm",
960 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
963 def tASRri : // A8.6.14
964 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
966 "asr", "\t$Rd, $Rm, $imm5",
967 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
969 let Inst{10-6} = imm5;
973 def tASRrr : // A8.6.15
974 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
976 "asr", "\t$Rdn, $Rm",
977 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
980 def tBIC : // A8.6.20
981 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
983 "bic", "\t$Rdn, $Rm",
984 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
987 let isCompare = 1, Defs = [CPSR] in {
988 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
989 // Compare-to-zero still works out, just not the relationals
990 //def tCMN : // A8.6.33
991 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
993 // "cmn", "\t$lhs, $rhs",
994 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
996 def tCMNz : // A8.6.33
997 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1000 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
1002 } // isCompare = 1, Defs = [CPSR]
1005 let isCompare = 1, Defs = [CPSR] in {
1006 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
1007 "cmp", "\t$Rn, $imm8",
1008 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
1009 T1General<{1,0,1,?,?}> {
1013 let Inst{10-8} = Rn;
1014 let Inst{7-0} = imm8;
1018 def tCMPr : // A8.6.36 T1
1019 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1021 "cmp", "\t$Rn, $Rm",
1022 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
1024 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1025 "cmp", "\t$Rn, $Rm", []>,
1026 T1Special<{0,1,?,?}> {
1030 let Inst{7} = Rn{3};
1032 let Inst{2-0} = Rn{2-0};
1034 } // isCompare = 1, Defs = [CPSR]
1038 let isCommutable = 1 in
1039 def tEOR : // A8.6.45
1040 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1042 "eor", "\t$Rdn, $Rm",
1043 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1046 def tLSLri : // A8.6.88
1047 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1049 "lsl", "\t$Rd, $Rm, $imm5",
1050 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1052 let Inst{10-6} = imm5;
1056 def tLSLrr : // A8.6.89
1057 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1059 "lsl", "\t$Rdn, $Rm",
1060 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1063 def tLSRri : // A8.6.90
1064 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1066 "lsr", "\t$Rd, $Rm, $imm5",
1067 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1069 let Inst{10-6} = imm5;
1073 def tLSRrr : // A8.6.91
1074 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1076 "lsr", "\t$Rdn, $Rm",
1077 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1080 let isMoveImm = 1 in
1081 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
1082 "mov", "\t$Rd, $imm8",
1083 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1084 T1General<{1,0,0,?,?}> {
1088 let Inst{10-8} = Rd;
1089 let Inst{7-0} = imm8;
1092 // TODO: A7-73: MOV(2) - mov setting flag.
1094 let neverHasSideEffects = 1 in {
1095 // FIXME: Make this predicable.
1096 def tMOVr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1097 "mov\t$Rd, $Rm", []>,
1102 // Bits {7-6} are encoded by the T1Special value.
1103 let Inst{5-3} = Rm{2-0};
1104 let Inst{2-0} = Rd{2-0};
1106 let Defs = [CPSR] in
1107 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1108 "movs\t$Rd, $Rm", []>, Encoding16 {
1112 let Inst{15-6} = 0b0000000000;
1117 // FIXME: Make these predicable.
1118 def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1119 "mov\t$Rd, $Rm", []>,
1120 T1Special<{1,0,0,?}> {
1124 // Bit {7} is encoded by the T1Special value.
1126 let Inst{2-0} = Rd{2-0};
1128 def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1129 "mov\t$Rd, $Rm", []>,
1130 T1Special<{1,0,?,0}> {
1134 // Bit {6} is encoded by the T1Special value.
1135 let Inst{7} = Rd{3};
1136 let Inst{5-3} = Rm{2-0};
1137 let Inst{2-0} = Rd{2-0};
1139 def tMOVgpr2gpr : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1140 "mov\t$Rd, $Rm", []>,
1141 T1Special<{1,0,?,?}> {
1145 let Inst{7} = Rd{3};
1147 let Inst{2-0} = Rd{2-0};
1149 } // neverHasSideEffects
1151 // Multiply register
1152 let isCommutable = 1 in
1153 def tMUL : // A8.6.105 T1
1154 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1156 "mul", "\t$Rdn, $Rm, $Rdn",
1157 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1159 // Move inverse register
1160 def tMVN : // A8.6.107
1161 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1162 "mvn", "\t$Rd, $Rn",
1163 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1165 // Bitwise or register
1166 let isCommutable = 1 in
1167 def tORR : // A8.6.114
1168 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1170 "orr", "\t$Rdn, $Rm",
1171 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1174 def tREV : // A8.6.134
1175 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1177 "rev", "\t$Rd, $Rm",
1178 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1179 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1181 def tREV16 : // A8.6.135
1182 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1184 "rev16", "\t$Rd, $Rm",
1186 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1187 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1188 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1189 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1190 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1192 def tREVSH : // A8.6.136
1193 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1195 "revsh", "\t$Rd, $Rm",
1198 (or (srl tGPR:$Rm, (i32 8)),
1199 (shl tGPR:$Rm, (i32 8))), i16))]>,
1200 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1202 def : T1Pat<(sext_inreg (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1203 (shl tGPR:$Rm, (i32 8))), i16),
1205 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1207 def : T1Pat<(sra (bswap tGPR:$Rm), (i32 16)), (tREVSH tGPR:$Rm)>,
1208 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1210 // Rotate right register
1211 def tROR : // A8.6.139
1212 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1214 "ror", "\t$Rdn, $Rm",
1215 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1218 def tRSB : // A8.6.141
1219 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1221 "rsb", "\t$Rd, $Rn, #0",
1222 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1224 // Subtract with carry register
1225 let Uses = [CPSR] in
1226 def tSBC : // A8.6.151
1227 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1229 "sbc", "\t$Rdn, $Rm",
1230 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1232 // Subtract immediate
1233 def tSUBi3 : // A8.6.210 T1
1234 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1236 "sub", "\t$Rd, $Rm, $imm3",
1237 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1239 let Inst{8-6} = imm3;
1242 def tSUBi8 : // A8.6.210 T2
1243 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1245 "sub", "\t$Rdn, $imm8",
1246 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1248 // Subtract register
1249 def tSUBrr : // A8.6.212
1250 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1252 "sub", "\t$Rd, $Rn, $Rm",
1253 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1255 // TODO: A7-96: STMIA - store multiple.
1258 def tSXTB : // A8.6.222
1259 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1261 "sxtb", "\t$Rd, $Rm",
1262 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1263 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1265 // Sign-extend short
1266 def tSXTH : // A8.6.224
1267 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1269 "sxth", "\t$Rd, $Rm",
1270 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1271 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1274 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1275 def tTST : // A8.6.230
1276 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1277 "tst", "\t$Rn, $Rm",
1278 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1281 def tUXTB : // A8.6.262
1282 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1284 "uxtb", "\t$Rd, $Rm",
1285 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1286 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1288 // Zero-extend short
1289 def tUXTH : // A8.6.264
1290 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1292 "uxth", "\t$Rd, $Rm",
1293 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1294 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1296 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1297 // Expanded after instruction selection into a branch sequence.
1298 let usesCustomInserter = 1 in // Expanded after instruction selection.
1299 def tMOVCCr_pseudo :
1300 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1302 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1305 // 16-bit movcc in IT blocks for Thumb2.
1306 let neverHasSideEffects = 1 in {
1307 def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1308 "mov", "\t$Rdn, $Rm", []>,
1309 T1Special<{1,0,?,?}> {
1312 let Inst{7} = Rdn{3};
1314 let Inst{2-0} = Rdn{2-0};
1317 let isMoveImm = 1 in
1318 def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1319 "mov", "\t$Rdn, $Rm", []>,
1320 T1General<{1,0,0,?,?}> {
1323 let Inst{10-8} = Rdn;
1327 } // neverHasSideEffects
1329 // tLEApcrel - Load a pc-relative address into a register without offending the
1332 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1333 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1334 T1Encoding<{1,0,1,0,0,?}> {
1337 let Inst{10-8} = Rd;
1338 let Inst{7-0} = addr;
1341 let neverHasSideEffects = 1, isReMaterializable = 1 in
1342 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1343 Size2Bytes, IIC_iALUi, []>;
1345 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1346 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1347 Size2Bytes, IIC_iALUi, []>;
1349 //===----------------------------------------------------------------------===//
1350 // Move between coprocessor and ARM core register -- for disassembly only
1353 class tMovRCopro<string opc, bit direction, dag oops, dag iops,
1355 : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1357 let Inst{27-24} = 0b1110;
1358 let Inst{20} = direction;
1368 let Inst{15-12} = Rt;
1369 let Inst{11-8} = cop;
1370 let Inst{23-21} = opc1;
1371 let Inst{7-5} = opc2;
1372 let Inst{3-0} = CRm;
1373 let Inst{19-16} = CRn;
1376 def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
1378 (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
1379 c_imm:$CRm, i32imm:$opc2),
1380 [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
1381 imm:$CRm, imm:$opc2)]>;
1382 def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
1384 (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1387 def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
1388 (tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>,
1389 Requires<[IsThumb, HasV6T2]>;
1391 class tMovRRCopro<string opc, bit direction,
1392 list<dag> pattern = [/* For disassembly only */]>
1393 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1394 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
1395 let Inst{27-24} = 0b1100;
1396 let Inst{23-21} = 0b010;
1397 let Inst{20} = direction;
1405 let Inst{15-12} = Rt;
1406 let Inst{19-16} = Rt2;
1407 let Inst{11-8} = cop;
1408 let Inst{7-4} = opc1;
1409 let Inst{3-0} = CRm;
1412 def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
1413 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
1415 def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1417 //===----------------------------------------------------------------------===//
1418 // Other Coprocessor Instructions. For disassembly only.
1420 def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1421 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1422 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1423 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
1424 imm:$CRm, imm:$opc2)]> {
1425 let Inst{27-24} = 0b1110;
1434 let Inst{3-0} = CRm;
1436 let Inst{7-5} = opc2;
1437 let Inst{11-8} = cop;
1438 let Inst{15-12} = CRd;
1439 let Inst{19-16} = CRn;
1440 let Inst{23-20} = opc1;
1443 //===----------------------------------------------------------------------===//
1447 // __aeabi_read_tp preserves the registers r1-r3.
1448 let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1449 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1450 "bl\t__aeabi_read_tp",
1451 [(set R0, ARMthread_pointer)]> {
1452 // Encoding is 0xf7fffffe.
1453 let Inst = 0xf7fffffe;
1456 //===----------------------------------------------------------------------===//
1457 // SJLJ Exception handling intrinsics
1460 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1461 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1462 // from some other function to get here, and we're using the stack frame for the
1463 // containing function to save/restore registers, we can't keep anything live in
1464 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1465 // tromped upon when we get here from a longjmp(). We force everything out of
1466 // registers except for our own input by listing the relevant registers in
1467 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1468 // preserve all of the callee-saved resgisters, which is exactly what we want.
1469 // $val is a scratch register for our use.
1470 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ],
1471 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1472 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1473 AddrModeNone, SizeSpecial, NoItinerary, "","",
1474 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1476 // FIXME: Non-Darwin version(s)
1477 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1478 Defs = [ R7, LR, SP ] in
1479 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1480 AddrModeNone, SizeSpecial, IndexModeNone,
1481 Pseudo, NoItinerary, "", "",
1482 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1483 Requires<[IsThumb, IsDarwin]>;
1485 //===----------------------------------------------------------------------===//
1486 // Non-Instruction Patterns
1490 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1491 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1492 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1493 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1496 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1497 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1498 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1499 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1500 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1501 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1503 // Subtract with carry
1504 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1505 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1506 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1507 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1508 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1509 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1511 // ConstantPool, GlobalAddress
1512 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1513 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1516 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1517 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1520 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1521 Requires<[IsThumb, IsNotDarwin]>;
1522 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1523 Requires<[IsThumb, IsDarwin]>;
1525 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1526 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1527 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1528 Requires<[IsThumb, HasV5T, IsDarwin]>;
1530 // Indirect calls to ARM routines
1531 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1532 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1533 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1534 Requires<[IsThumb, HasV5T, IsDarwin]>;
1536 // zextload i1 -> zextload i8
1537 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1538 (tLDRBr t_addrmode_rrs1:$addr)>;
1539 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1540 (tLDRBi t_addrmode_is1:$addr)>;
1542 // extload -> zextload
1543 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1544 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1545 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1546 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1547 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1548 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1550 // If it's impossible to use [r,r] address mode for sextload, select to
1551 // ldr{b|h} + sxt{b|h} instead.
1552 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1553 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1554 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1555 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1556 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1557 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1558 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1559 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1560 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1561 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1562 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1563 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1565 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1566 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1567 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1568 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1569 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1570 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1571 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1572 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1574 // Large immediate handling.
1577 def : T1Pat<(i32 thumb_immshifted:$src),
1578 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1579 (thumb_immshifted_shamt imm:$src))>;
1581 def : T1Pat<(i32 imm0_255_comp:$src),
1582 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1584 // Pseudo instruction that combines ldr from constpool and add pc. This should
1585 // be expanded into two instructions late to allow if-conversion and
1587 let isReMaterializable = 1 in
1588 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1590 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1592 Requires<[IsThumb, IsThumb1Only]>;