1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 // TI - Thumb instruction.
23 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
28 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
32 class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, ops, asm, cstr> {
36 let Pattern = pattern;
37 list<Predicate> Predicates = [IsThumb];
40 class TI<dag ops, string asm, list<dag> pattern>
41 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
42 class TI1<dag ops, string asm, list<dag> pattern>
43 : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
44 class TI2<dag ops, string asm, list<dag> pattern>
45 : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
46 class TI4<dag ops, string asm, list<dag> pattern>
47 : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
48 class TIs<dag ops, string asm, list<dag> pattern>
49 : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
51 // Two-address instructions
52 class TIt<dag ops, string asm, list<dag> pattern>
53 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
55 // BL, BLX(1) are translated by assembler into two instructions
56 class TIx2<dag ops, string asm, list<dag> pattern>
57 : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
60 class TJTI<dag ops, string asm, list<dag> pattern>
61 : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
63 def imm_neg_XFORM : SDNodeXForm<imm, [{
64 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
66 def imm_comp_XFORM : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
71 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
72 def imm0_7 : PatLeaf<(i32 imm), [{
73 return (uint32_t)N->getValue() < 8;
75 def imm0_7_neg : PatLeaf<(i32 imm), [{
76 return (uint32_t)-N->getValue() < 8;
79 def imm0_255 : PatLeaf<(i32 imm), [{
80 return (uint32_t)N->getValue() < 256;
82 def imm0_255_comp : PatLeaf<(i32 imm), [{
83 return ~((uint32_t)N->getValue()) < 256;
86 def imm8_255 : PatLeaf<(i32 imm), [{
87 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
89 def imm8_255_neg : PatLeaf<(i32 imm), [{
90 unsigned Val = -N->getValue();
91 return Val >= 8 && Val < 256;
94 // Break imm's up into two pieces: an immediate + a left shift.
95 // This uses thumb_immshifted to match and thumb_immshifted_val and
96 // thumb_immshifted_shamt to get the val/shift pieces.
97 def thumb_immshifted : PatLeaf<(imm), [{
98 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
101 def thumb_immshifted_val : SDNodeXForm<imm, [{
102 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
103 return CurDAG->getTargetConstant(V, MVT::i32);
106 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
107 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
108 return CurDAG->getTargetConstant(V, MVT::i32);
111 // Define Thumb specific addressing modes.
113 // t_addrmode_rr := reg + reg
115 def t_addrmode_rr : Operand<i32>,
116 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
117 let PrintMethod = "printThumbAddrModeRROperand";
118 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
121 // t_addrmode_s4 := reg + reg
124 def t_addrmode_s4 : Operand<i32>,
125 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
126 let PrintMethod = "printThumbAddrModeS4Operand";
127 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
130 // t_addrmode_s2 := reg + reg
133 def t_addrmode_s2 : Operand<i32>,
134 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
135 let PrintMethod = "printThumbAddrModeS2Operand";
136 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
139 // t_addrmode_s1 := reg + reg
142 def t_addrmode_s1 : Operand<i32>,
143 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
144 let PrintMethod = "printThumbAddrModeS1Operand";
145 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg, i32imm:$offsimm);
148 // t_addrmode_sp := sp + imm8 * 4
150 def t_addrmode_sp : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
152 let PrintMethod = "printThumbAddrModeSPOperand";
153 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
156 //===----------------------------------------------------------------------===//
157 // Miscellaneous Instructions.
160 def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
161 "\n$cp:\n\tadd $dst, pc",
162 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
164 //===----------------------------------------------------------------------===//
165 // Control Flow Instructions.
168 let isReturn = 1, isTerminator = 1 in
169 def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
171 // FIXME: remove when we have a way to marking a MI with these properties.
172 let isLoad = 1, isReturn = 1, isTerminator = 1 in
173 def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
176 let isCall = 1, noResults = 1,
177 Defs = [R0, R1, R2, R3, LR,
178 D0, D1, D2, D3, D4, D5, D6, D7] in {
179 def tBL : TIx2<(ops i32imm:$func, variable_ops),
181 [(ARMtcall tglobaladdr:$func)]>;
183 def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
185 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
186 def tBLXr : TI<(ops GPR:$dst, variable_ops),
188 [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
190 def tBX : TIx2<(ops GPR:$dst, variable_ops),
191 "cpy lr, pc\n\tbx $dst",
192 [(ARMcall_nolink GPR:$dst)]>;
195 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
196 def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
199 def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>;
201 def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
202 "cpy pc, $dst \n\t.align\t2\n$jt",
203 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
206 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in
207 def tBcc : TI<(ops brtarget:$dst, CCOp:$cc), "b$cc $dst",
208 [(ARMbrcond bb:$dst, imm:$cc)]>;
210 //===----------------------------------------------------------------------===//
211 // Load Store Instructions.
215 def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
217 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
219 def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
221 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
223 def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
225 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
227 def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
229 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
231 def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
233 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
235 def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
237 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
240 def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
242 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
246 def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
248 [(store GPR:$src, t_addrmode_s4:$addr)]>;
250 def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
252 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
254 def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
256 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
258 def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
260 [(store GPR:$src, t_addrmode_sp:$addr)]>;
263 //===----------------------------------------------------------------------===//
264 // Load / store multiple Instructions.
267 // TODO: A7-44: LDMIA - load multiple
270 def tPOP : TI<(ops reglist:$dst1, variable_ops),
274 def tPUSH : TI<(ops reglist:$src1, variable_ops),
277 //===----------------------------------------------------------------------===//
278 // Arithmetic Instructions.
282 def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
284 [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
286 def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
287 "adds $dst, $lhs, $rhs",
288 [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
291 def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
292 "add $dst, $lhs, $rhs",
293 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
295 def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
297 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
299 def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
300 "add $dst, $lhs, $rhs",
301 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
303 def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
304 "add $dst, $rhs", []>;
306 def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
307 "add $dst, pc, $rhs * 4", []>;
308 def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
309 "add $dst, $sp, $rhs * 4", []>;
310 def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
311 "add $dst, $rhs * 4", []>;
313 def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
315 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
317 def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
318 "asr $dst, $lhs, $rhs",
319 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
321 def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
323 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
325 def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
327 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
330 def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
332 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
334 def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
336 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
338 def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
340 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
342 // TODO: A7-37: CMP(3) - cmp hi regs
344 def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
346 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
348 def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
349 "lsl $dst, $lhs, $rhs",
350 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
352 def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
354 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
356 def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
357 "lsr $dst, $lhs, $rhs",
358 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
360 def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
362 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
364 def tMOVri8 : TI<(ops GPR:$dst, i32imm:$src),
366 [(set GPR:$dst, imm0_255:$src)]>;
368 // TODO: A7-73: MOV(2) - mov setting flag.
371 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
372 // which is MOV(3). This also supports high registers.
373 def tMOVrr : TI<(ops GPR:$dst, GPR:$src),
374 "cpy $dst, $src", []>;
376 def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
378 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
380 def tMVN : TI<(ops GPR:$dst, GPR:$src),
382 [(set GPR:$dst, (not GPR:$src))]>;
384 def tNEG : TI<(ops GPR:$dst, GPR:$src),
386 [(set GPR:$dst, (ineg GPR:$src))]>;
388 def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
390 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
393 def tREV : TI<(ops GPR:$dst, GPR:$src),
395 [(set GPR:$dst, (bswap GPR:$src))]>,
396 Requires<[IsThumb, HasV6]>;
398 def tREV16 : TI<(ops GPR:$dst, GPR:$src),
401 (or (and (srl GPR:$src, 8), 0xFF),
402 (or (and (shl GPR:$src, 8), 0xFF00),
403 (or (and (srl GPR:$src, 8), 0xFF0000),
404 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
405 Requires<[IsThumb, HasV6]>;
407 def tREVSH : TI<(ops GPR:$dst, GPR:$src),
411 (or (srl (and GPR:$src, 0xFFFF), 8),
412 (shl GPR:$src, 8)), i16))]>,
413 Requires<[IsThumb, HasV6]>;
415 def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
417 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
420 // Subtract with carry
421 def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
423 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
425 def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
426 "subs $dst, $lhs, $rhs",
427 [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
430 // TODO: A7-96: STMIA - store multiple.
432 def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
433 "sub $dst, $lhs, $rhs",
434 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
436 def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
438 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
440 def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
441 "sub $dst, $lhs, $rhs",
442 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
444 def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
445 "sub $dst, $rhs * 4", []>;
447 def tSXTB : TI<(ops GPR:$dst, GPR:$src),
449 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
450 Requires<[IsThumb, HasV6]>;
451 def tSXTH : TI<(ops GPR:$dst, GPR:$src),
453 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
454 Requires<[IsThumb, HasV6]>;
456 // TODO: A7-122: TST - test.
458 def tUXTB : TI<(ops GPR:$dst, GPR:$src),
460 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
461 Requires<[IsThumb, HasV6]>;
462 def tUXTH : TI<(ops GPR:$dst, GPR:$src),
464 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
465 Requires<[IsThumb, HasV6]>;
468 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
469 // Expanded by the scheduler into a branch sequence.
470 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
472 PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, CCOp:$cc),
474 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
476 // tLEApcrel - Load a pc-relative address into a register without offending the
478 def tLEApcrel : TI<(ops GPR:$dst, i32imm:$label),
479 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
480 "${:private}PCRELL${:uid}+4))\n"),
481 !strconcat("${:private}PCRELL${:uid}:\n\t",
482 "add $dst, pc, #PCRELV${:uid}")),
485 def tLEApcrelCall : TI<(ops GPR:$dst, i32imm:$label),
486 !strconcat(!strconcat(".set PCRELV${:uid}, (${label:call}-(",
487 "${:private}PCRELL${:uid}+4))\n"),
488 !strconcat("${:private}PCRELL${:uid}:\n\t",
489 "add $dst, pc, #PCRELV${:uid}")),
492 def tLEApcrelJT : TI<(ops GPR:$dst, i32imm:$label, i32imm:$id),
493 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
494 "${:private}PCRELL${:uid}+4))\n"),
495 !strconcat("${:private}PCRELL${:uid}:\n\t",
496 "add $dst, pc, #PCRELV${:uid}")),
499 //===----------------------------------------------------------------------===//
500 // Non-Instruction Patterns
503 // ConstantPool, GlobalAddress
504 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
505 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
506 def : ThumbPat<(ARMWrapperCall tglobaladdr :$dst),
507 (tLEApcrelCall tglobaladdr :$dst)>;
508 def : ThumbPat<(ARMWrapperCall texternalsym:$dst),
509 (tLEApcrelCall texternalsym:$dst)>;
512 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
513 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
516 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
517 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
519 // Indirect calls to ARM routines
520 def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
522 // zextload i1 -> zextload i8
523 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
524 (tLDRB t_addrmode_s1:$addr)>;
526 // extload -> zextload
527 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
528 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
529 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
531 // truncstore i1 -> truncstore i8
532 def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
533 (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
535 // Large immediate handling.
538 def : ThumbPat<(i32 thumb_immshifted:$src),
539 (tLSLri (tMOVri8 (thumb_immshifted_val imm:$src)),
540 (thumb_immshifted_shamt imm:$src))>;
542 def : ThumbPat<(i32 imm0_255_comp:$src),
543 (tMVN (tMOVri8 (imm_comp_XFORM imm:$src)))>;