1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
82 def t_imm0_1020s4 : Operand<i32> {
83 let PrintMethod = "printThumbS4ImmOperand";
84 let ParserMatchClass = t_imm0_1020s4_asmoperand;
85 let OperandType = "OPERAND_IMMEDIATE";
88 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
89 def t_imm0_508s4 : Operand<i32> {
90 let PrintMethod = "printThumbS4ImmOperand";
91 let ParserMatchClass = t_imm0_508s4_asmoperand;
92 let OperandType = "OPERAND_IMMEDIATE";
95 // Define Thumb specific addressing modes.
97 let OperandType = "OPERAND_PCREL" in {
98 def t_brtarget : Operand<OtherVT> {
99 let EncoderMethod = "getThumbBRTargetOpValue";
100 let DecoderMethod = "DecodeThumbBROperand";
103 def t_bcctarget : Operand<i32> {
104 let EncoderMethod = "getThumbBCCTargetOpValue";
105 let DecoderMethod = "DecodeThumbBCCTargetOperand";
108 def t_cbtarget : Operand<i32> {
109 let EncoderMethod = "getThumbCBTargetOpValue";
110 let DecoderMethod = "DecodeThumbCmpBROperand";
113 def t_bltarget : Operand<i32> {
114 let EncoderMethod = "getThumbBLTargetOpValue";
115 let DecoderMethod = "DecodeThumbBLTargetOperand";
118 def t_blxtarget : Operand<i32> {
119 let EncoderMethod = "getThumbBLXTargetOpValue";
120 let DecoderMethod = "DecodeThumbBLXOffset";
124 // t_addrmode_rr := reg + reg
126 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
127 def t_addrmode_rr : Operand<i32>,
128 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
129 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
130 let PrintMethod = "printThumbAddrModeRROperand";
131 let DecoderMethod = "DecodeThumbAddrModeRR";
132 let ParserMatchClass = t_addrmode_rr_asm_operand;
133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
136 // t_addrmode_rrs := reg + reg
138 // We use separate scaled versions because the Select* functions need
139 // to explicitly check for a matching constant and return false here so that
140 // the reg+imm forms will match instead. This is a horrible way to do that,
141 // as it forces tight coupling between the methods, but it's how selectiondag
143 def t_addrmode_rrs1 : Operand<i32>,
144 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
145 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
146 let PrintMethod = "printThumbAddrModeRROperand";
147 let DecoderMethod = "DecodeThumbAddrModeRR";
148 let ParserMatchClass = t_addrmode_rr_asm_operand;
149 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
151 def t_addrmode_rrs2 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
153 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
154 let DecoderMethod = "DecodeThumbAddrModeRR";
155 let PrintMethod = "printThumbAddrModeRROperand";
156 let ParserMatchClass = t_addrmode_rr_asm_operand;
157 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
159 def t_addrmode_rrs4 : Operand<i32>,
160 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
161 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
162 let DecoderMethod = "DecodeThumbAddrModeRR";
163 let PrintMethod = "printThumbAddrModeRROperand";
164 let ParserMatchClass = t_addrmode_rr_asm_operand;
165 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
168 // t_addrmode_is4 := reg + imm5 * 4
170 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
171 def t_addrmode_is4 : Operand<i32>,
172 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
173 let EncoderMethod = "getAddrModeISOpValue";
174 let DecoderMethod = "DecodeThumbAddrModeIS";
175 let PrintMethod = "printThumbAddrModeImm5S4Operand";
176 let ParserMatchClass = t_addrmode_is4_asm_operand;
177 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
180 // t_addrmode_is2 := reg + imm5 * 2
182 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
183 def t_addrmode_is2 : Operand<i32>,
184 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
185 let EncoderMethod = "getAddrModeISOpValue";
186 let DecoderMethod = "DecodeThumbAddrModeIS";
187 let PrintMethod = "printThumbAddrModeImm5S2Operand";
188 let ParserMatchClass = t_addrmode_is2_asm_operand;
189 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
192 // t_addrmode_is1 := reg + imm5
194 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
195 def t_addrmode_is1 : Operand<i32>,
196 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
197 let EncoderMethod = "getAddrModeISOpValue";
198 let DecoderMethod = "DecodeThumbAddrModeIS";
199 let PrintMethod = "printThumbAddrModeImm5S1Operand";
200 let ParserMatchClass = t_addrmode_is1_asm_operand;
201 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
204 // t_addrmode_sp := sp + imm8 * 4
206 // FIXME: This really shouldn't have an explicit SP operand at all. It should
207 // be implicit, just like in the instruction encoding itself.
208 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
209 def t_addrmode_sp : Operand<i32>,
210 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
211 let EncoderMethod = "getAddrModeThumbSPOpValue";
212 let DecoderMethod = "DecodeThumbAddrModeSP";
213 let PrintMethod = "printThumbAddrModeSPOperand";
214 let ParserMatchClass = t_addrmode_sp_asm_operand;
215 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
218 // t_addrmode_pc := <label> => pc + imm8 * 4
220 def t_addrmode_pc : Operand<i32> {
221 let EncoderMethod = "getAddrModePCOpValue";
222 let DecoderMethod = "DecodeThumbAddrModePC";
225 //===----------------------------------------------------------------------===//
226 // Miscellaneous Instructions.
229 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
230 // from removing one half of the matched pairs. That breaks PEI, which assumes
231 // these will always be in pairs, and asserts if it finds otherwise. Better way?
232 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
233 def tADJCALLSTACKUP :
234 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
235 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
236 Requires<[IsThumb, IsThumb1Only]>;
238 def tADJCALLSTACKDOWN :
239 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
240 [(ARMcallseq_start imm:$amt)]>,
241 Requires<[IsThumb, IsThumb1Only]>;
244 class T1SystemEncoding<bits<8> opc>
245 : T1Encoding<0b101111> {
246 let Inst{9-8} = 0b11;
250 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
251 T1SystemEncoding<0x00>, // A8.6.110
252 Requires<[IsThumb2]>;
254 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
255 T1SystemEncoding<0x10>; // A8.6.410
257 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
258 T1SystemEncoding<0x20>; // A8.6.408
260 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
261 T1SystemEncoding<0x30>; // A8.6.409
263 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
264 T1SystemEncoding<0x40>; // A8.6.157
266 // The imm operand $val can be used by a debugger to store more information
267 // about the breakpoint.
268 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
270 T1Encoding<0b101111> {
271 let Inst{9-8} = 0b10;
277 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
278 []>, T1Encoding<0b101101> {
281 let Inst{9-5} = 0b10010;
284 let Inst{2-0} = 0b000;
287 // Change Processor State is a system instruction -- for disassembly only.
288 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
289 NoItinerary, "cps$imod $iflags", []>,
297 let Inst{2-0} = iflags;
298 let DecoderMethod = "DecodeThumbCPS";
301 // For both thumb1 and thumb2.
302 let isNotDuplicable = 1, isCodeGenOnly = 1 in
303 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
304 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
305 T1Special<{0,0,?,?}> {
308 let Inst{6-3} = 0b1111; // Rm = pc
312 // ADD <Rd>, sp, #<imm8>
313 // FIXME: This should not be marked as having side effects, and it should be
314 // rematerializable. Clearing the side effect bit causes miscompilations,
315 // probably because the instruction can be moved around.
316 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
317 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
318 T1Encoding<{1,0,1,0,1,?}> {
322 let Inst{10-8} = dst;
324 let DecoderMethod = "DecodeThumbAddSpecialReg";
327 // ADD sp, sp, #<imm7>
328 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
329 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
330 T1Misc<{0,0,0,0,0,?,?}> {
334 let DecoderMethod = "DecodeThumbAddSPImm";
337 // SUB sp, sp, #<imm7>
338 // FIXME: The encoding and the ASM string don't match up.
339 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
340 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
341 T1Misc<{0,0,0,0,1,?,?}> {
345 let DecoderMethod = "DecodeThumbAddSPImm";
348 // Can optionally specify SP as a three operand instruction.
349 def : tInstAlias<"add${p} sp, sp, $imm",
350 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
351 def : tInstAlias<"sub${p} sp, sp, $imm",
352 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
355 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
356 "add", "\t$Rdn, $sp, $Rn", []>,
357 T1Special<{0,0,?,?}> {
358 // A8.6.9 Encoding T1
360 let Inst{7} = Rdn{3};
361 let Inst{6-3} = 0b1101;
362 let Inst{2-0} = Rdn{2-0};
363 let DecoderMethod = "DecodeThumbAddSPReg";
367 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
368 "add", "\t$Rdn, $Rm", []>,
369 T1Special<{0,0,?,?}> {
370 // A8.6.9 Encoding T2
374 let Inst{2-0} = 0b101;
375 let DecoderMethod = "DecodeThumbAddSPReg";
378 //===----------------------------------------------------------------------===//
379 // Control Flow Instructions.
383 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
384 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
385 T1Special<{1,1,0,?}> {
389 let Inst{2-0} = 0b000;
390 let Unpredictable{2-0} = 0b111;
394 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
395 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
396 [(ARMretflag)], (tBX LR, pred:$p)>;
398 // Alternative return instruction used by vararg functions.
399 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
401 (tBX GPR:$Rm, pred:$p)>;
404 // All calls clobber the non-callee saved registers. SP is marked as a use to
405 // prevent stack-pointer assignments that appear immediately before calls from
406 // potentially appearing dead.
408 // On non-IOS platforms R9 is callee-saved.
409 Defs = [R0, R1, R2, R3, R12, LR,
410 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15,
413 // Also used for Thumb2
414 def tBL : TIx2<0b11110, 0b11, 1,
415 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
417 [(ARMtcall tglobaladdr:$func)]>,
418 Requires<[IsThumb, IsNotIOS]> {
420 let Inst{26} = func{21};
421 let Inst{25-16} = func{20-11};
424 let Inst{10-0} = func{10-0};
427 // ARMv5T and above, also used for Thumb2
428 def tBLXi : TIx2<0b11110, 0b11, 0,
429 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
431 [(ARMcall tglobaladdr:$func)]>,
432 Requires<[IsThumb, HasV5T, IsNotIOS]> {
434 let Inst{25-16} = func{20-11};
437 let Inst{10-1} = func{10-1};
438 let Inst{0} = 0; // func{0} is assumed zero
441 // Also used for Thumb2
442 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
444 [(ARMtcall GPR:$func)]>,
445 Requires<[IsThumb, HasV5T, IsNotIOS]>,
446 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
448 let Inst{6-3} = func;
449 let Inst{2-0} = 0b000;
453 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
455 [(ARMcall_nolink tGPR:$func)]>,
456 Requires<[IsThumb, IsThumb1Only, IsNotIOS]>;
460 // On IOS R9 is call-clobbered.
461 // R7 is marked as a use to prevent frame-pointer assignments from being
462 // moved above / below calls.
463 Defs = [R0, R1, R2, R3, R9, R12, LR,
464 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15,
467 // Also used for Thumb2
468 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
469 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
470 (tBL pred:$p, t_bltarget:$func)>,
471 Requires<[IsThumb, IsIOS]>;
473 // ARMv5T and above, also used for Thumb2
474 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
475 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
476 (tBLXi pred:$p, t_blxtarget:$func)>,
477 Requires<[IsThumb, HasV5T, IsIOS]>;
479 // Also used for Thumb2
480 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
481 2, IIC_Br, [(ARMtcall GPR:$func)],
482 (tBLXr pred:$p, GPR:$func)>,
483 Requires<[IsThumb, HasV5T, IsIOS]>;
486 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
488 [(ARMcall_nolink tGPR:$func)]>,
489 Requires<[IsThumb, IsThumb1Only, IsIOS]>;
492 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
493 let isPredicable = 1 in
494 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
495 "b", "\t$target", [(br bb:$target)]>,
496 T1Encoding<{1,1,1,0,0,?}> {
498 let Inst{10-0} = target;
502 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
503 // the clobber of LR.
505 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
506 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
508 def tBR_JTr : tPseudoInst<(outs),
509 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
511 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
512 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
516 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
517 // a two-value operand where a dag node expects two operands. :(
518 let isBranch = 1, isTerminator = 1 in
519 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
521 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
522 T1BranchCond<{1,1,0,1}> {
526 let Inst{7-0} = target;
530 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
532 let Defs = [R0, R1, R2, R3, R9, R12,
533 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, PC],
535 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
536 // on IOS), so it's in ARMInstrThumb2.td.
537 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
539 (tBX GPR:$dst, (ops 14, zero_reg))>,
540 Requires<[IsThumb, IsIOS]>;
542 // Non-IOS versions (the difference is R9).
543 let Defs = [R0, R1, R2, R3, R12,
544 Q0, Q1, Q2, Q3, Q8, Q9, Q10, Q11, Q12, Q13, Q14, Q15, PC],
546 def tTAILJMPdND : tPseudoExpand<(outs),
547 (ins t_brtarget:$dst, pred:$p, variable_ops),
549 (tB t_brtarget:$dst, pred:$p)>,
550 Requires<[IsThumb, IsNotIOS]>;
551 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
553 (tBX GPR:$dst, (ops 14, zero_reg))>,
554 Requires<[IsThumb, IsNotIOS]>;
559 // A8.6.218 Supervisor Call (Software Interrupt)
560 // A8.6.16 B: Encoding T1
561 // If Inst{11-8} == 0b1111 then SEE SVC
562 let isCall = 1, Uses = [SP] in
563 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
564 "svc", "\t$imm", []>, Encoding16 {
566 let Inst{15-12} = 0b1101;
567 let Inst{11-8} = 0b1111;
571 // The assembler uses 0xDEFE for a trap instruction.
572 let isBarrier = 1, isTerminator = 1 in
573 def tTRAP : TI<(outs), (ins), IIC_Br,
574 "trap", [(trap)]>, Encoding16 {
578 //===----------------------------------------------------------------------===//
579 // Load Store Instructions.
582 // Loads: reg/reg and reg/imm5
583 let canFoldAsLoad = 1, isReMaterializable = 1 in
584 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
585 Operand AddrMode_r, Operand AddrMode_i,
586 AddrMode am, InstrItinClass itin_r,
587 InstrItinClass itin_i, string asm,
590 T1pILdStEncode<reg_opc,
591 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
592 am, itin_r, asm, "\t$Rt, $addr",
593 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
595 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
596 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
597 am, itin_i, asm, "\t$Rt, $addr",
598 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
600 // Stores: reg/reg and reg/imm5
601 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
602 Operand AddrMode_r, Operand AddrMode_i,
603 AddrMode am, InstrItinClass itin_r,
604 InstrItinClass itin_i, string asm,
607 T1pILdStEncode<reg_opc,
608 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
609 am, itin_r, asm, "\t$Rt, $addr",
610 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
612 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
613 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
614 am, itin_i, asm, "\t$Rt, $addr",
615 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
619 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
620 t_addrmode_is4, AddrModeT1_4,
621 IIC_iLoad_r, IIC_iLoad_i, "ldr",
622 UnOpFrag<(load node:$Src)>>;
625 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
626 t_addrmode_is1, AddrModeT1_1,
627 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
628 UnOpFrag<(zextloadi8 node:$Src)>>;
631 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
632 t_addrmode_is2, AddrModeT1_2,
633 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
634 UnOpFrag<(zextloadi16 node:$Src)>>;
636 let AddedComplexity = 10 in
637 def tLDRSB : // A8.6.80
638 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
639 AddrModeT1_1, IIC_iLoad_bh_r,
640 "ldrsb", "\t$Rt, $addr",
641 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
643 let AddedComplexity = 10 in
644 def tLDRSH : // A8.6.84
645 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
646 AddrModeT1_2, IIC_iLoad_bh_r,
647 "ldrsh", "\t$Rt, $addr",
648 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
650 let canFoldAsLoad = 1 in
651 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
652 "ldr", "\t$Rt, $addr",
653 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
658 let Inst{7-0} = addr;
662 // FIXME: Use ldr.n to work around a darwin assembler bug.
663 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
664 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
665 "ldr", ".n\t$Rt, $addr",
666 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
667 T1Encoding<{0,1,0,0,1,?}> {
672 let Inst{7-0} = addr;
675 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
676 // For assembly/disassembly use only.
677 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
678 "ldr", "\t$Rt, $addr", []>,
679 T1Encoding<{0,1,0,0,1,?}> {
684 let Inst{7-0} = addr;
687 // A8.6.194 & A8.6.192
688 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
689 t_addrmode_is4, AddrModeT1_4,
690 IIC_iStore_r, IIC_iStore_i, "str",
691 BinOpFrag<(store node:$LHS, node:$RHS)>>;
693 // A8.6.197 & A8.6.195
694 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
695 t_addrmode_is1, AddrModeT1_1,
696 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
697 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
699 // A8.6.207 & A8.6.205
700 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
701 t_addrmode_is2, AddrModeT1_2,
702 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
703 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
706 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
707 "str", "\t$Rt, $addr",
708 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
713 let Inst{7-0} = addr;
716 //===----------------------------------------------------------------------===//
717 // Load / store multiple Instructions.
720 // These require base address to be written back or one of the loaded regs.
721 let neverHasSideEffects = 1 in {
723 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
724 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
725 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
729 let Inst{7-0} = regs;
732 // Writeback version is just a pseudo, as there's no encoding difference.
733 // Writeback happens iff the base register is not in the destination register
736 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
737 "$Rn = $wb", IIC_iLoad_mu>,
738 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
740 let OutOperandList = (outs GPR:$wb);
741 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
743 let isCodeGenOnly = 1;
745 list<Predicate> Predicates = [IsThumb];
748 // There is no non-writeback version of STM for Thumb.
749 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
750 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
751 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
752 AddrModeNone, 2, IIC_iStore_mu,
753 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
754 T1Encoding<{1,1,0,0,0,?}> {
758 let Inst{7-0} = regs;
761 } // neverHasSideEffects
763 def : InstAlias<"ldm${p} $Rn!, $regs",
764 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
765 Requires<[IsThumb, IsThumb1Only]>;
767 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
768 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
770 "pop${p}\t$regs", []>,
771 T1Misc<{1,1,0,?,?,?,?}> {
773 let Inst{8} = regs{15};
774 let Inst{7-0} = regs{7-0};
777 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
778 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
780 "push${p}\t$regs", []>,
781 T1Misc<{0,1,0,?,?,?,?}> {
783 let Inst{8} = regs{14};
784 let Inst{7-0} = regs{7-0};
787 //===----------------------------------------------------------------------===//
788 // Arithmetic Instructions.
791 // Helper classes for encoding T1pI patterns:
792 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
793 string opc, string asm, list<dag> pattern>
794 : T1pI<oops, iops, itin, opc, asm, pattern>,
795 T1DataProcessing<opA> {
801 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
802 string opc, string asm, list<dag> pattern>
803 : T1pI<oops, iops, itin, opc, asm, pattern>,
811 // Helper classes for encoding T1sI patterns:
812 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
813 string opc, string asm, list<dag> pattern>
814 : T1sI<oops, iops, itin, opc, asm, pattern>,
815 T1DataProcessing<opA> {
821 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
822 string opc, string asm, list<dag> pattern>
823 : T1sI<oops, iops, itin, opc, asm, pattern>,
832 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
833 string opc, string asm, list<dag> pattern>
834 : T1sI<oops, iops, itin, opc, asm, pattern>,
842 // Helper classes for encoding T1sIt patterns:
843 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
844 string opc, string asm, list<dag> pattern>
845 : T1sIt<oops, iops, itin, opc, asm, pattern>,
846 T1DataProcessing<opA> {
852 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
853 string opc, string asm, list<dag> pattern>
854 : T1sIt<oops, iops, itin, opc, asm, pattern>,
858 let Inst{10-8} = Rdn;
859 let Inst{7-0} = imm8;
862 // Add with carry register
863 let isCommutable = 1, Uses = [CPSR] in
865 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
866 "adc", "\t$Rdn, $Rm",
867 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
870 def tADDi3 : // A8.6.4 T1
871 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
873 "add", "\t$Rd, $Rm, $imm3",
874 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
876 let Inst{8-6} = imm3;
879 def tADDi8 : // A8.6.4 T2
880 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
881 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
882 "add", "\t$Rdn, $imm8",
883 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
886 let isCommutable = 1 in
887 def tADDrr : // A8.6.6 T1
888 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
890 "add", "\t$Rd, $Rn, $Rm",
891 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
893 let neverHasSideEffects = 1 in
894 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
895 "add", "\t$Rdn, $Rm", []>,
896 T1Special<{0,0,?,?}> {
900 let Inst{7} = Rdn{3};
902 let Inst{2-0} = Rdn{2-0};
906 let isCommutable = 1 in
907 def tAND : // A8.6.12
908 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
910 "and", "\t$Rdn, $Rm",
911 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
914 def tASRri : // A8.6.14
915 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
917 "asr", "\t$Rd, $Rm, $imm5",
918 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
920 let Inst{10-6} = imm5;
924 def tASRrr : // A8.6.15
925 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
927 "asr", "\t$Rdn, $Rm",
928 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
931 def tBIC : // A8.6.20
932 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
934 "bic", "\t$Rdn, $Rm",
935 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
938 let isCompare = 1, Defs = [CPSR] in {
939 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
940 // Compare-to-zero still works out, just not the relationals
941 //def tCMN : // A8.6.33
942 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
944 // "cmn", "\t$lhs, $rhs",
945 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
947 def tCMNz : // A8.6.33
948 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
951 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
953 } // isCompare = 1, Defs = [CPSR]
956 let isCompare = 1, Defs = [CPSR] in {
957 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
958 "cmp", "\t$Rn, $imm8",
959 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
960 T1General<{1,0,1,?,?}> {
965 let Inst{7-0} = imm8;
969 def tCMPr : // A8.6.36 T1
970 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
973 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
975 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
976 "cmp", "\t$Rn, $Rm", []>,
977 T1Special<{0,1,?,?}> {
983 let Inst{2-0} = Rn{2-0};
985 } // isCompare = 1, Defs = [CPSR]
989 let isCommutable = 1 in
990 def tEOR : // A8.6.45
991 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
993 "eor", "\t$Rdn, $Rm",
994 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
997 def tLSLri : // A8.6.88
998 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
1000 "lsl", "\t$Rd, $Rm, $imm5",
1001 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1003 let Inst{10-6} = imm5;
1007 def tLSLrr : // A8.6.89
1008 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1010 "lsl", "\t$Rdn, $Rm",
1011 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1014 def tLSRri : // A8.6.90
1015 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1017 "lsr", "\t$Rd, $Rm, $imm5",
1018 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
1020 let Inst{10-6} = imm5;
1024 def tLSRrr : // A8.6.91
1025 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1027 "lsr", "\t$Rdn, $Rm",
1028 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1031 let isMoveImm = 1 in
1032 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1033 "mov", "\t$Rd, $imm8",
1034 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1035 T1General<{1,0,0,?,?}> {
1039 let Inst{10-8} = Rd;
1040 let Inst{7-0} = imm8;
1042 // Because we have an explicit tMOVSr below, we need an alias to handle
1043 // the immediate "movs" form here. Blech.
1044 def : tInstAlias <"movs $Rdn, $imm",
1045 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1047 // A7-73: MOV(2) - mov setting flag.
1049 let neverHasSideEffects = 1 in {
1050 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1052 "mov", "\t$Rd, $Rm", "", []>,
1053 T1Special<{1,0,?,?}> {
1057 let Inst{7} = Rd{3};
1059 let Inst{2-0} = Rd{2-0};
1061 let Defs = [CPSR] in
1062 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1063 "movs\t$Rd, $Rm", []>, Encoding16 {
1067 let Inst{15-6} = 0b0000000000;
1071 } // neverHasSideEffects
1073 // Multiply register
1074 let isCommutable = 1 in
1075 def tMUL : // A8.6.105 T1
1076 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1077 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1078 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1079 T1DataProcessing<0b1101> {
1084 let AsmMatchConverter = "cvtThumbMultiply";
1087 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1090 // Move inverse register
1091 def tMVN : // A8.6.107
1092 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1093 "mvn", "\t$Rd, $Rn",
1094 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1096 // Bitwise or register
1097 let isCommutable = 1 in
1098 def tORR : // A8.6.114
1099 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1101 "orr", "\t$Rdn, $Rm",
1102 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1105 def tREV : // A8.6.134
1106 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1108 "rev", "\t$Rd, $Rm",
1109 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1110 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1112 def tREV16 : // A8.6.135
1113 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1115 "rev16", "\t$Rd, $Rm",
1116 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1117 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1119 def tREVSH : // A8.6.136
1120 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1122 "revsh", "\t$Rd, $Rm",
1123 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1124 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1126 // Rotate right register
1127 def tROR : // A8.6.139
1128 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1130 "ror", "\t$Rdn, $Rm",
1131 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1134 def tRSB : // A8.6.141
1135 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1137 "rsb", "\t$Rd, $Rn, #0",
1138 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1140 // Subtract with carry register
1141 let Uses = [CPSR] in
1142 def tSBC : // A8.6.151
1143 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1145 "sbc", "\t$Rdn, $Rm",
1146 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1148 // Subtract immediate
1149 def tSUBi3 : // A8.6.210 T1
1150 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1152 "sub", "\t$Rd, $Rm, $imm3",
1153 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1155 let Inst{8-6} = imm3;
1158 def tSUBi8 : // A8.6.210 T2
1159 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1160 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1161 "sub", "\t$Rdn, $imm8",
1162 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1164 // Subtract register
1165 def tSUBrr : // A8.6.212
1166 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1168 "sub", "\t$Rd, $Rn, $Rm",
1169 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1172 def tSXTB : // A8.6.222
1173 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1175 "sxtb", "\t$Rd, $Rm",
1176 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1177 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1179 // Sign-extend short
1180 def tSXTH : // A8.6.224
1181 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1183 "sxth", "\t$Rd, $Rm",
1184 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1185 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1188 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1189 def tTST : // A8.6.230
1190 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1191 "tst", "\t$Rn, $Rm",
1192 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1195 def tUXTB : // A8.6.262
1196 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1198 "uxtb", "\t$Rd, $Rm",
1199 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1200 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1202 // Zero-extend short
1203 def tUXTH : // A8.6.264
1204 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1206 "uxth", "\t$Rd, $Rm",
1207 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1208 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1210 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1211 // Expanded after instruction selection into a branch sequence.
1212 let usesCustomInserter = 1 in // Expanded after instruction selection.
1213 def tMOVCCr_pseudo :
1214 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1216 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1218 // tLEApcrel - Load a pc-relative address into a register without offending the
1221 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1222 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1223 T1Encoding<{1,0,1,0,0,?}> {
1226 let Inst{10-8} = Rd;
1227 let Inst{7-0} = addr;
1228 let DecoderMethod = "DecodeThumbAddSpecialReg";
1231 let neverHasSideEffects = 1, isReMaterializable = 1 in
1232 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1235 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1236 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1239 //===----------------------------------------------------------------------===//
1243 // __aeabi_read_tp preserves the registers r1-r3.
1244 // This is a pseudo inst so that we can get the encoding right,
1245 // complete with fixup for the aeabi_read_tp function.
1246 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1247 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1248 [(set R0, ARMthread_pointer)]>;
1250 //===----------------------------------------------------------------------===//
1251 // SJLJ Exception handling intrinsics
1254 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1255 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1256 // from some other function to get here, and we're using the stack frame for the
1257 // containing function to save/restore registers, we can't keep anything live in
1258 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1259 // tromped upon when we get here from a longjmp(). We force everything out of
1260 // registers except for our own input by listing the relevant registers in
1261 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1262 // preserve all of the callee-saved resgisters, which is exactly what we want.
1263 // $val is a scratch register for our use.
1264 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1265 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1266 usesCustomInserter = 1 in
1267 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1268 AddrModeNone, 0, NoItinerary, "","",
1269 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1271 // FIXME: Non-IOS version(s)
1272 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1273 Defs = [ R7, LR, SP ] in
1274 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1275 AddrModeNone, 0, IndexModeNone,
1276 Pseudo, NoItinerary, "", "",
1277 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1278 Requires<[IsThumb, IsIOS]>;
1280 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1282 def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
1284 //===----------------------------------------------------------------------===//
1285 // Non-Instruction Patterns
1289 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1290 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1291 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1292 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1295 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1296 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1297 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1298 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1299 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1300 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1302 // Subtract with carry
1303 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1304 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1305 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1306 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1307 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1308 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1310 // ConstantPool, GlobalAddress
1311 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1312 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1315 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1316 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1319 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1320 Requires<[IsThumb, IsNotIOS]>;
1321 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1322 Requires<[IsThumb, IsIOS]>;
1324 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1325 Requires<[IsThumb, HasV5T, IsNotIOS]>;
1326 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1327 Requires<[IsThumb, HasV5T, IsIOS]>;
1329 // Indirect calls to ARM routines
1330 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1331 Requires<[IsThumb, HasV5T, IsNotIOS]>;
1332 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1333 Requires<[IsThumb, HasV5T, IsIOS]>;
1335 // zextload i1 -> zextload i8
1336 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1337 (tLDRBr t_addrmode_rrs1:$addr)>;
1338 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1339 (tLDRBi t_addrmode_is1:$addr)>;
1341 // extload -> zextload
1342 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1343 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1344 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1345 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1346 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1347 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1349 // If it's impossible to use [r,r] address mode for sextload, select to
1350 // ldr{b|h} + sxt{b|h} instead.
1351 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1352 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1353 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1354 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1355 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1356 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1357 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1358 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1359 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1360 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1361 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1362 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1364 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1365 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1366 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1367 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1368 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1369 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1370 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1371 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1373 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1374 (tLDRBi t_addrmode_is1:$src)>;
1375 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1376 (tLDRBr t_addrmode_rrs1:$src)>;
1377 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1378 (tLDRHi t_addrmode_is2:$src)>;
1379 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1380 (tLDRHr t_addrmode_rrs2:$src)>;
1381 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1382 (tLDRi t_addrmode_is4:$src)>;
1383 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1384 (tLDRr t_addrmode_rrs4:$src)>;
1385 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1386 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1387 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1388 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1389 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1390 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1391 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1392 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1393 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1394 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1395 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1396 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1398 // Large immediate handling.
1401 def : T1Pat<(i32 thumb_immshifted:$src),
1402 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1403 (thumb_immshifted_shamt imm:$src))>;
1405 def : T1Pat<(i32 imm0_255_comp:$src),
1406 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1408 // Pseudo instruction that combines ldr from constpool and add pc. This should
1409 // be expanded into two instructions late to allow if-conversion and
1411 let isReMaterializable = 1 in
1412 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1414 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1416 Requires<[IsThumb, IsThumb1Only]>;
1418 // Pseudo-instruction for merged POP and return.
1419 // FIXME: remove when we have a way to marking a MI with these properties.
1420 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1421 hasExtraDefRegAllocReq = 1 in
1422 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1424 (tPOP pred:$p, reglist:$regs)>;
1426 // Indirect branch using "mov pc, $Rm"
1427 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1428 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1429 2, IIC_Br, [(brind GPR:$Rm)],
1430 (tMOVr PC, GPR:$Rm, pred:$p)>;
1434 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1435 // encoding is available on ARMv6K, but we don't differentiate that finely.
1436 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1439 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1440 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1441 // a useful extention and assembles to defined behaviour (the insn does
1443 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1444 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1446 // "neg" is and alias for "rsb rd, rn, #0"
1447 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1448 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;