1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let ParserMatchClass = t_addrmode_rr_asm_operand;
124 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127 // t_addrmode_rrs := reg + reg
129 // We use separate scaled versions because the Select* functions need
130 // to explicitly check for a matching constant and return false here so that
131 // the reg+imm forms will match instead. This is a horrible way to do that,
132 // as it forces tight coupling between the methods, but it's how selectiondag
134 def t_addrmode_rrs1 : Operand<i32>,
135 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
136 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
137 let PrintMethod = "printThumbAddrModeRROperand";
138 let DecoderMethod = "DecodeThumbAddrModeRR";
139 let ParserMatchClass = t_addrmode_rr_asm_operand;
140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
142 def t_addrmode_rrs2 : Operand<i32>,
143 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
144 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
145 let DecoderMethod = "DecodeThumbAddrModeRR";
146 let PrintMethod = "printThumbAddrModeRROperand";
147 let ParserMatchClass = t_addrmode_rr_asm_operand;
148 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
150 def t_addrmode_rrs4 : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
152 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
153 let DecoderMethod = "DecodeThumbAddrModeRR";
154 let PrintMethod = "printThumbAddrModeRROperand";
155 let ParserMatchClass = t_addrmode_rr_asm_operand;
156 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
159 // t_addrmode_is4 := reg + imm5 * 4
161 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
162 def t_addrmode_is4 : Operand<i32>,
163 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
164 let EncoderMethod = "getAddrModeISOpValue";
165 let DecoderMethod = "DecodeThumbAddrModeIS";
166 let PrintMethod = "printThumbAddrModeImm5S4Operand";
167 let ParserMatchClass = t_addrmode_is4_asm_operand;
168 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171 // t_addrmode_is2 := reg + imm5 * 2
173 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
174 def t_addrmode_is2 : Operand<i32>,
175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
176 let EncoderMethod = "getAddrModeISOpValue";
177 let DecoderMethod = "DecodeThumbAddrModeIS";
178 let PrintMethod = "printThumbAddrModeImm5S2Operand";
179 let ParserMatchClass = t_addrmode_is2_asm_operand;
180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
183 // t_addrmode_is1 := reg + imm5
185 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
186 def t_addrmode_is1 : Operand<i32>,
187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
188 let EncoderMethod = "getAddrModeISOpValue";
189 let DecoderMethod = "DecodeThumbAddrModeIS";
190 let PrintMethod = "printThumbAddrModeImm5S1Operand";
191 let ParserMatchClass = t_addrmode_is1_asm_operand;
192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
195 // t_addrmode_sp := sp + imm8 * 4
197 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
198 def t_addrmode_sp : Operand<i32>,
199 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
200 let EncoderMethod = "getAddrModeThumbSPOpValue";
201 let DecoderMethod = "DecodeThumbAddrModeSP";
202 let PrintMethod = "printThumbAddrModeSPOperand";
203 let ParserMatchClass = t_addrmode_sp_asm_operand;
204 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
207 // t_addrmode_pc := <label> => pc + imm8 * 4
209 def t_addrmode_pc : Operand<i32> {
210 let EncoderMethod = "getAddrModePCOpValue";
211 let DecoderMethod = "DecodeThumbAddrModePC";
214 //===----------------------------------------------------------------------===//
215 // Miscellaneous Instructions.
218 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
219 // from removing one half of the matched pairs. That breaks PEI, which assumes
220 // these will always be in pairs, and asserts if it finds otherwise. Better way?
221 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
222 def tADJCALLSTACKUP :
223 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
224 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
225 Requires<[IsThumb, IsThumb1Only]>;
227 def tADJCALLSTACKDOWN :
228 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
229 [(ARMcallseq_start imm:$amt)]>,
230 Requires<[IsThumb, IsThumb1Only]>;
233 class T1SystemEncoding<bits<8> opc>
234 : T1Encoding<0b101111> {
235 let Inst{9-8} = 0b11;
239 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
240 T1SystemEncoding<0x00>; // A8.6.110
242 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
243 T1SystemEncoding<0x10>; // A8.6.410
245 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
246 T1SystemEncoding<0x20>; // A8.6.408
248 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
249 T1SystemEncoding<0x30>; // A8.6.409
251 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
252 T1SystemEncoding<0x40>; // A8.6.157
254 // The imm operand $val can be used by a debugger to store more information
255 // about the breakpoint.
256 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
258 T1Encoding<0b101111> {
259 let Inst{9-8} = 0b10;
265 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
266 []>, T1Encoding<0b101101> {
269 let Inst{9-5} = 0b10010;
272 let Inst{2-0} = 0b000;
275 // Change Processor State is a system instruction -- for disassembly only.
276 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
277 NoItinerary, "cps$imod $iflags",
278 [/* For disassembly only; pattern left blank */]>,
286 let Inst{2-0} = iflags;
287 let DecoderMethod = "DecodeThumbCPS";
290 // For both thumb1 and thumb2.
291 let isNotDuplicable = 1, isCodeGenOnly = 1 in
292 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
293 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
294 T1Special<{0,0,?,?}> {
297 let Inst{6-3} = 0b1111; // Rm = pc
301 // ADD <Rd>, sp, #<imm8>
302 // This is rematerializable, which is particularly useful for taking the
303 // address of locals.
304 let isReMaterializable = 1 in
305 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
306 "add\t$dst, $sp, $rhs", []>,
307 T1Encoding<{1,0,1,0,1,?}> {
311 let Inst{10-8} = dst;
313 let DecoderMethod = "DecodeThumbAddSpecialReg";
316 // ADD sp, sp, #<imm7>
317 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
318 "add\t$dst, $rhs", []>,
319 T1Misc<{0,0,0,0,0,?,?}> {
323 let DecoderMethod = "DecodeThumbAddSPImm";
326 // SUB sp, sp, #<imm7>
327 // FIXME: The encoding and the ASM string don't match up.
328 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
329 "sub\t$dst, $rhs", []>,
330 T1Misc<{0,0,0,0,1,?,?}> {
334 let DecoderMethod = "DecodeThumbAddSPImm";
338 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
339 "add\t$dst, $rhs", []>,
340 T1Special<{0,0,?,?}> {
341 // A8.6.9 Encoding T1
343 let Inst{7} = dst{3};
344 let Inst{6-3} = 0b1101;
345 let Inst{2-0} = dst{2-0};
346 let DecoderMethod = "DecodeThumbAddSPReg";
350 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
351 "add\t$dst, $rhs", []>,
352 T1Special<{0,0,?,?}> {
353 // A8.6.9 Encoding T2
357 let Inst{2-0} = 0b101;
358 let DecoderMethod = "DecodeThumbAddSPReg";
361 //===----------------------------------------------------------------------===//
362 // Control Flow Instructions.
366 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
367 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
368 T1Special<{1,1,0,?}> {
372 let Inst{2-0} = 0b000;
376 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
377 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
378 [(ARMretflag)], (tBX LR, pred:$p)>;
380 // Alternative return instruction used by vararg functions.
381 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
383 (tBX GPR:$Rm, pred:$p)>;
386 // All calls clobber the non-callee saved registers. SP is marked as a use to
387 // prevent stack-pointer assignments that appear immediately before calls from
388 // potentially appearing dead.
390 // On non-Darwin platforms R9 is callee-saved.
391 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
393 // Also used for Thumb2
394 def tBL : TIx2<0b11110, 0b11, 1,
395 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
397 [(ARMtcall tglobaladdr:$func)]>,
398 Requires<[IsThumb, IsNotDarwin]> {
400 let Inst{26} = func{21};
401 let Inst{25-16} = func{20-11};
404 let Inst{10-0} = func{10-0};
407 // ARMv5T and above, also used for Thumb2
408 def tBLXi : TIx2<0b11110, 0b11, 0,
409 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
411 [(ARMcall tglobaladdr:$func)]>,
412 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
414 let Inst{25-16} = func{20-11};
417 let Inst{10-1} = func{10-1};
418 let Inst{0} = 0; // func{0} is assumed zero
421 // Also used for Thumb2
422 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
424 [(ARMtcall GPR:$func)]>,
425 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
426 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
428 let Inst{6-3} = func;
429 let Inst{2-0} = 0b000;
433 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
435 [(ARMcall_nolink tGPR:$func)]>,
436 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
440 // On Darwin R9 is call-clobbered.
441 // R7 is marked as a use to prevent frame-pointer assignments from being
442 // moved above / below calls.
443 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
445 // Also used for Thumb2
446 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
447 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
448 (tBL pred:$p, t_bltarget:$func)>,
449 Requires<[IsThumb, IsDarwin]>;
451 // ARMv5T and above, also used for Thumb2
452 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
453 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
454 (tBLXi pred:$p, t_blxtarget:$func)>,
455 Requires<[IsThumb, HasV5T, IsDarwin]>;
457 // Also used for Thumb2
458 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
459 2, IIC_Br, [(ARMtcall GPR:$func)],
460 (tBLXr pred:$p, GPR:$func)>,
461 Requires<[IsThumb, HasV5T, IsDarwin]>;
464 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
466 [(ARMcall_nolink tGPR:$func)]>,
467 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
470 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
471 let isPredicable = 1 in
472 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
473 "b\t$target", [(br bb:$target)]>,
474 T1Encoding<{1,1,1,0,0,?}> {
476 let Inst{10-0} = target;
480 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
481 // the clobber of LR.
483 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
484 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
486 def tBR_JTr : tPseudoInst<(outs),
487 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
489 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
490 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
494 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
495 // a two-value operand where a dag node expects two operands. :(
496 let isBranch = 1, isTerminator = 1 in
497 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
499 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
500 T1BranchCond<{1,1,0,1}> {
504 let Inst{7-0} = target;
508 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
510 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
512 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
513 // on Darwin), so it's in ARMInstrThumb2.td.
514 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
516 (tBX GPR:$dst, (ops 14, zero_reg))>,
517 Requires<[IsThumb, IsDarwin]>;
519 // Non-Darwin versions (the difference is R9).
520 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
522 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
524 (tB t_brtarget:$dst)>,
525 Requires<[IsThumb, IsNotDarwin]>;
526 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
528 (tBX GPR:$dst, (ops 14, zero_reg))>,
529 Requires<[IsThumb, IsNotDarwin]>;
534 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
535 // A8.6.16 B: Encoding T1
536 // If Inst{11-8} == 0b1111 then SEE SVC
537 let isCall = 1, Uses = [SP] in
538 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
539 "svc", "\t$imm", []>, Encoding16 {
541 let Inst{15-12} = 0b1101;
542 let Inst{11-8} = 0b1111;
546 // The assembler uses 0xDEFE for a trap instruction.
547 let isBarrier = 1, isTerminator = 1 in
548 def tTRAP : TI<(outs), (ins), IIC_Br,
549 "trap", [(trap)]>, Encoding16 {
553 //===----------------------------------------------------------------------===//
554 // Load Store Instructions.
557 // Loads: reg/reg and reg/imm5
558 let canFoldAsLoad = 1, isReMaterializable = 1 in
559 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
560 Operand AddrMode_r, Operand AddrMode_i,
561 AddrMode am, InstrItinClass itin_r,
562 InstrItinClass itin_i, string asm,
565 T1pILdStEncode<reg_opc,
566 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
567 am, itin_r, asm, "\t$Rt, $addr",
568 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
570 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
571 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
572 am, itin_i, asm, "\t$Rt, $addr",
573 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
575 // Stores: reg/reg and reg/imm5
576 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
577 Operand AddrMode_r, Operand AddrMode_i,
578 AddrMode am, InstrItinClass itin_r,
579 InstrItinClass itin_i, string asm,
582 T1pILdStEncode<reg_opc,
583 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
584 am, itin_r, asm, "\t$Rt, $addr",
585 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
587 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
588 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
589 am, itin_i, asm, "\t$Rt, $addr",
590 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
594 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
595 t_addrmode_is4, AddrModeT1_4,
596 IIC_iLoad_r, IIC_iLoad_i, "ldr",
597 UnOpFrag<(load node:$Src)>>;
600 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
601 t_addrmode_is1, AddrModeT1_1,
602 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
603 UnOpFrag<(zextloadi8 node:$Src)>>;
606 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
607 t_addrmode_is2, AddrModeT1_2,
608 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
609 UnOpFrag<(zextloadi16 node:$Src)>>;
611 let AddedComplexity = 10 in
612 def tLDRSB : // A8.6.80
613 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
614 AddrModeT1_1, IIC_iLoad_bh_r,
615 "ldrsb", "\t$Rt, $addr",
616 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
618 let AddedComplexity = 10 in
619 def tLDRSH : // A8.6.84
620 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
621 AddrModeT1_2, IIC_iLoad_bh_r,
622 "ldrsh", "\t$Rt, $addr",
623 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
625 let canFoldAsLoad = 1 in
626 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
627 "ldr", "\t$Rt, $addr",
628 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
633 let Inst{7-0} = addr;
637 // FIXME: Use ldr.n to work around a Darwin assembler bug.
638 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
639 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
640 "ldr", ".n\t$Rt, $addr",
641 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
642 T1Encoding<{0,1,0,0,1,?}> {
647 let Inst{7-0} = addr;
650 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
651 // For disassembly use only.
652 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
653 "ldr", "\t$Rt, $addr",
654 [/* disassembly only */]>,
655 T1Encoding<{0,1,0,0,1,?}> {
660 let Inst{7-0} = addr;
663 // A8.6.194 & A8.6.192
664 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
665 t_addrmode_is4, AddrModeT1_4,
666 IIC_iStore_r, IIC_iStore_i, "str",
667 BinOpFrag<(store node:$LHS, node:$RHS)>>;
669 // A8.6.197 & A8.6.195
670 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
671 t_addrmode_is1, AddrModeT1_1,
672 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
673 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
675 // A8.6.207 & A8.6.205
676 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
677 t_addrmode_is2, AddrModeT1_2,
678 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
679 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
682 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
683 "str", "\t$Rt, $addr",
684 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
689 let Inst{7-0} = addr;
692 //===----------------------------------------------------------------------===//
693 // Load / store multiple Instructions.
696 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
697 InstrItinClass itin_upd, bits<6> T1Enc,
698 bit L_bit, string baseOpc> {
700 T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
701 itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
706 let Inst{7-0} = regs;
710 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
711 "$Rn = $wb", itin_upd>,
712 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
713 tGPR:$Rn, pred:$p, reglist:$regs)> {
715 let OutOperandList = (outs GPR:$wb);
716 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
718 let isCodeGenOnly = 1;
720 list<Predicate> Predicates = [IsThumb];
724 // These require base address to be written back or one of the loaded regs.
725 let neverHasSideEffects = 1 in {
727 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
728 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
729 {1,1,0,0,1,?}, 1, "tLDM">;
731 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
732 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
733 {1,1,0,0,0,?}, 0, "tSTM">;
735 } // neverHasSideEffects
737 def : InstAlias<"ldm${p} $Rn!, $regs",
738 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
739 Requires<[IsThumb, IsThumb1Only]>;
742 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
743 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
745 "pop${p}\t$regs", []>,
746 T1Misc<{1,1,0,?,?,?,?}> {
748 let Inst{8} = regs{15};
749 let Inst{7-0} = regs{7-0};
752 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
753 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
755 "push${p}\t$regs", []>,
756 T1Misc<{0,1,0,?,?,?,?}> {
758 let Inst{8} = regs{14};
759 let Inst{7-0} = regs{7-0};
762 //===----------------------------------------------------------------------===//
763 // Arithmetic Instructions.
766 // Helper classes for encoding T1pI patterns:
767 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
768 string opc, string asm, list<dag> pattern>
769 : T1pI<oops, iops, itin, opc, asm, pattern>,
770 T1DataProcessing<opA> {
776 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
777 string opc, string asm, list<dag> pattern>
778 : T1pI<oops, iops, itin, opc, asm, pattern>,
786 // Helper classes for encoding T1sI patterns:
787 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
788 string opc, string asm, list<dag> pattern>
789 : T1sI<oops, iops, itin, opc, asm, pattern>,
790 T1DataProcessing<opA> {
796 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
797 string opc, string asm, list<dag> pattern>
798 : T1sI<oops, iops, itin, opc, asm, pattern>,
807 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
808 string opc, string asm, list<dag> pattern>
809 : T1sI<oops, iops, itin, opc, asm, pattern>,
817 // Helper classes for encoding T1sIt patterns:
818 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
819 string opc, string asm, list<dag> pattern>
820 : T1sIt<oops, iops, itin, opc, asm, pattern>,
821 T1DataProcessing<opA> {
827 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
828 string opc, string asm, list<dag> pattern>
829 : T1sIt<oops, iops, itin, opc, asm, pattern>,
833 let Inst{10-8} = Rdn;
834 let Inst{7-0} = imm8;
837 // Add with carry register
838 let isCommutable = 1, Uses = [CPSR] in
840 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
841 "adc", "\t$Rdn, $Rm",
842 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
845 def tADDi3 : // A8.6.4 T1
846 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
848 "add", "\t$Rd, $Rm, $imm3",
849 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
851 let Inst{8-6} = imm3;
854 def tADDi8 : // A8.6.4 T2
855 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
856 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
857 "add", "\t$Rdn, $imm8",
858 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
861 let isCommutable = 1 in
862 def tADDrr : // A8.6.6 T1
863 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
865 "add", "\t$Rd, $Rn, $Rm",
866 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
868 let neverHasSideEffects = 1 in
869 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
870 "add", "\t$Rdn, $Rm", []>,
871 T1Special<{0,0,?,?}> {
875 let Inst{7} = Rdn{3};
877 let Inst{2-0} = Rdn{2-0};
881 let isCommutable = 1 in
882 def tAND : // A8.6.12
883 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
885 "and", "\t$Rdn, $Rm",
886 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
889 def tASRri : // A8.6.14
890 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
892 "asr", "\t$Rd, $Rm, $imm5",
893 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
895 let Inst{10-6} = imm5;
899 def tASRrr : // A8.6.15
900 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
902 "asr", "\t$Rdn, $Rm",
903 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
906 def tBIC : // A8.6.20
907 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
909 "bic", "\t$Rdn, $Rm",
910 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
913 let isCompare = 1, Defs = [CPSR] in {
914 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
915 // Compare-to-zero still works out, just not the relationals
916 //def tCMN : // A8.6.33
917 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
919 // "cmn", "\t$lhs, $rhs",
920 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
922 def tCMNz : // A8.6.33
923 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
926 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
928 } // isCompare = 1, Defs = [CPSR]
931 let isCompare = 1, Defs = [CPSR] in {
932 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
933 "cmp", "\t$Rn, $imm8",
934 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
935 T1General<{1,0,1,?,?}> {
940 let Inst{7-0} = imm8;
944 def tCMPr : // A8.6.36 T1
945 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
948 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
950 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
951 "cmp", "\t$Rn, $Rm", []>,
952 T1Special<{0,1,?,?}> {
958 let Inst{2-0} = Rn{2-0};
960 } // isCompare = 1, Defs = [CPSR]
964 let isCommutable = 1 in
965 def tEOR : // A8.6.45
966 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
968 "eor", "\t$Rdn, $Rm",
969 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
972 def tLSLri : // A8.6.88
973 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
975 "lsl", "\t$Rd, $Rm, $imm5",
976 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
978 let Inst{10-6} = imm5;
982 def tLSLrr : // A8.6.89
983 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
985 "lsl", "\t$Rdn, $Rm",
986 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
989 def tLSRri : // A8.6.90
990 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
992 "lsr", "\t$Rd, $Rm, $imm5",
993 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
995 let Inst{10-6} = imm5;
999 def tLSRrr : // A8.6.91
1000 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1002 "lsr", "\t$Rdn, $Rm",
1003 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1006 let isMoveImm = 1 in
1007 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1008 "mov", "\t$Rd, $imm8",
1009 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1010 T1General<{1,0,0,?,?}> {
1014 let Inst{10-8} = Rd;
1015 let Inst{7-0} = imm8;
1017 // Because we have an explicit tMOVSr below, we need an alias to handle
1018 // the immediate "movs" form here. Blech.
1019 def : InstAlias <"movs $Rdn, $imm",
1020 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>,
1021 Requires<[IsThumb]>;
1023 // A7-73: MOV(2) - mov setting flag.
1025 let neverHasSideEffects = 1 in {
1026 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1028 "mov", "\t$Rd, $Rm", "", []>,
1029 T1Special<{1,0,?,?}> {
1033 let Inst{7} = Rd{3};
1035 let Inst{2-0} = Rd{2-0};
1037 let Defs = [CPSR] in
1038 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1039 "movs\t$Rd, $Rm", []>, Encoding16 {
1043 let Inst{15-6} = 0b0000000000;
1047 } // neverHasSideEffects
1049 // Multiply register
1050 let isCommutable = 1 in
1051 def tMUL : // A8.6.105 T1
1052 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1053 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1054 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1055 T1DataProcessing<0b1101> {
1060 let AsmMatchConverter = "cvtThumbMultiply";
1063 def : InstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1065 Requires<[IsThumb]>;
1067 // Move inverse register
1068 def tMVN : // A8.6.107
1069 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1070 "mvn", "\t$Rd, $Rn",
1071 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1073 // Bitwise or register
1074 let isCommutable = 1 in
1075 def tORR : // A8.6.114
1076 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1078 "orr", "\t$Rdn, $Rm",
1079 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1082 def tREV : // A8.6.134
1083 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1085 "rev", "\t$Rd, $Rm",
1086 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1087 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1089 def tREV16 : // A8.6.135
1090 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1092 "rev16", "\t$Rd, $Rm",
1093 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1094 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1096 def tREVSH : // A8.6.136
1097 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1099 "revsh", "\t$Rd, $Rm",
1100 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1101 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1103 // Rotate right register
1104 def tROR : // A8.6.139
1105 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1107 "ror", "\t$Rdn, $Rm",
1108 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1111 def tRSB : // A8.6.141
1112 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1114 "rsb", "\t$Rd, $Rn, #0",
1115 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1117 def : InstAlias<"neg${s}${p} $Rd, $Rm",
1118 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>,
1119 Requires<[IsThumb]>;
1121 // Subtract with carry register
1122 let Uses = [CPSR] in
1123 def tSBC : // A8.6.151
1124 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1126 "sbc", "\t$Rdn, $Rm",
1127 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1129 // Subtract immediate
1130 def tSUBi3 : // A8.6.210 T1
1131 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1133 "sub", "\t$Rd, $Rm, $imm3",
1134 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1136 let Inst{8-6} = imm3;
1139 def tSUBi8 : // A8.6.210 T2
1140 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1142 "sub", "\t$Rdn, $imm8",
1143 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1145 // Subtract register
1146 def tSUBrr : // A8.6.212
1147 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1149 "sub", "\t$Rd, $Rn, $Rm",
1150 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1152 // TODO: A7-96: STMIA - store multiple.
1155 def tSXTB : // A8.6.222
1156 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1158 "sxtb", "\t$Rd, $Rm",
1159 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1160 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1162 // Sign-extend short
1163 def tSXTH : // A8.6.224
1164 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1166 "sxth", "\t$Rd, $Rm",
1167 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1168 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1171 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1172 def tTST : // A8.6.230
1173 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1174 "tst", "\t$Rn, $Rm",
1175 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1178 def tUXTB : // A8.6.262
1179 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1181 "uxtb", "\t$Rd, $Rm",
1182 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1183 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1185 // Zero-extend short
1186 def tUXTH : // A8.6.264
1187 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1189 "uxth", "\t$Rd, $Rm",
1190 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1191 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1193 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1194 // Expanded after instruction selection into a branch sequence.
1195 let usesCustomInserter = 1 in // Expanded after instruction selection.
1196 def tMOVCCr_pseudo :
1197 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1199 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1201 // tLEApcrel - Load a pc-relative address into a register without offending the
1204 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1205 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1206 T1Encoding<{1,0,1,0,0,?}> {
1209 let Inst{10-8} = Rd;
1210 let Inst{7-0} = addr;
1211 let DecoderMethod = "DecodeThumbAddSpecialReg";
1214 let neverHasSideEffects = 1, isReMaterializable = 1 in
1215 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1218 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1219 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1222 //===----------------------------------------------------------------------===//
1226 // __aeabi_read_tp preserves the registers r1-r3.
1227 // This is a pseudo inst so that we can get the encoding right,
1228 // complete with fixup for the aeabi_read_tp function.
1229 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1230 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1231 [(set R0, ARMthread_pointer)]>;
1233 //===----------------------------------------------------------------------===//
1234 // SJLJ Exception handling intrinsics
1237 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1238 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1239 // from some other function to get here, and we're using the stack frame for the
1240 // containing function to save/restore registers, we can't keep anything live in
1241 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1242 // tromped upon when we get here from a longjmp(). We force everything out of
1243 // registers except for our own input by listing the relevant registers in
1244 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1245 // preserve all of the callee-saved resgisters, which is exactly what we want.
1246 // $val is a scratch register for our use.
1247 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1248 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1249 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1250 AddrModeNone, 0, NoItinerary, "","",
1251 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1253 // FIXME: Non-Darwin version(s)
1254 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1255 Defs = [ R7, LR, SP ] in
1256 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1257 AddrModeNone, 0, IndexModeNone,
1258 Pseudo, NoItinerary, "", "",
1259 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1260 Requires<[IsThumb, IsDarwin]>;
1262 //===----------------------------------------------------------------------===//
1263 // Non-Instruction Patterns
1267 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1268 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1269 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1270 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1273 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1274 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1275 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1276 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1277 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1278 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1280 // Subtract with carry
1281 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1282 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1283 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1284 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1285 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1286 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1288 // ConstantPool, GlobalAddress
1289 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1290 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1293 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1294 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1297 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1298 Requires<[IsThumb, IsNotDarwin]>;
1299 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1300 Requires<[IsThumb, IsDarwin]>;
1302 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1303 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1304 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1305 Requires<[IsThumb, HasV5T, IsDarwin]>;
1307 // Indirect calls to ARM routines
1308 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1309 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1310 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1311 Requires<[IsThumb, HasV5T, IsDarwin]>;
1313 // zextload i1 -> zextload i8
1314 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1315 (tLDRBr t_addrmode_rrs1:$addr)>;
1316 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1317 (tLDRBi t_addrmode_is1:$addr)>;
1319 // extload -> zextload
1320 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1321 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1322 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1323 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1324 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1325 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1327 // If it's impossible to use [r,r] address mode for sextload, select to
1328 // ldr{b|h} + sxt{b|h} instead.
1329 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1330 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1331 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1332 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1333 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1334 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1335 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1336 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1337 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1338 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1339 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1340 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1342 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1343 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1344 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1345 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1346 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1347 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1348 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1349 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1351 // Large immediate handling.
1354 def : T1Pat<(i32 thumb_immshifted:$src),
1355 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1356 (thumb_immshifted_shamt imm:$src))>;
1358 def : T1Pat<(i32 imm0_255_comp:$src),
1359 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1361 // Pseudo instruction that combines ldr from constpool and add pc. This should
1362 // be expanded into two instructions late to allow if-conversion and
1364 let isReMaterializable = 1 in
1365 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1367 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1369 Requires<[IsThumb, IsThumb1Only]>;
1371 // Pseudo-instruction for merged POP and return.
1372 // FIXME: remove when we have a way to marking a MI with these properties.
1373 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1374 hasExtraDefRegAllocReq = 1 in
1375 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1377 (tPOP pred:$p, reglist:$regs)>;
1379 // Indirect branch using "mov pc, $Rm"
1380 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1381 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1382 2, IIC_Br, [(brind GPR:$Rm)],
1383 (tMOVr PC, GPR:$Rm, pred:$p)>;