1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
126 // t_addrmode_rrs := reg + reg
128 // We use separate scaled versions because the Select* functions need
129 // to explicitly check for a matching constant and return false here so that
130 // the reg+imm forms will match instead. This is a horrible way to do that,
131 // as it forces tight coupling between the methods, but it's how selectiondag
133 def t_addrmode_rrs1 : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
135 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
136 let PrintMethod = "printThumbAddrModeRROperand";
137 let DecoderMethod = "DecodeThumbAddrModeRR";
138 let ParserMatchClass = t_addrmode_rr_asm_operand;
139 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141 def t_addrmode_rrs2 : Operand<i32>,
142 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
143 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
144 let DecoderMethod = "DecodeThumbAddrModeRR";
145 let PrintMethod = "printThumbAddrModeRROperand";
146 let ParserMatchClass = t_addrmode_rr_asm_operand;
147 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
149 def t_addrmode_rrs4 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
151 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
152 let DecoderMethod = "DecodeThumbAddrModeRR";
153 let PrintMethod = "printThumbAddrModeRROperand";
154 let ParserMatchClass = t_addrmode_rr_asm_operand;
155 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
158 // t_addrmode_is4 := reg + imm5 * 4
160 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
161 def t_addrmode_is4 : Operand<i32>,
162 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
163 let EncoderMethod = "getAddrModeISOpValue";
164 let DecoderMethod = "DecodeThumbAddrModeIS";
165 let PrintMethod = "printThumbAddrModeImm5S4Operand";
166 let ParserMatchClass = t_addrmode_is4_asm_operand;
167 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
170 // t_addrmode_is2 := reg + imm5 * 2
172 def t_addrmode_is2 : Operand<i32>,
173 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
174 let EncoderMethod = "getAddrModeISOpValue";
175 let DecoderMethod = "DecodeThumbAddrModeIS";
176 let PrintMethod = "printThumbAddrModeImm5S2Operand";
177 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
180 // t_addrmode_is1 := reg + imm5
182 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
183 def t_addrmode_is1 : Operand<i32>,
184 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
185 let EncoderMethod = "getAddrModeISOpValue";
186 let DecoderMethod = "DecodeThumbAddrModeIS";
187 let PrintMethod = "printThumbAddrModeImm5S1Operand";
188 let ParserMatchClass = t_addrmode_is1_asm_operand;
189 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
192 // t_addrmode_sp := sp + imm8 * 4
194 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
195 def t_addrmode_sp : Operand<i32>,
196 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
197 let EncoderMethod = "getAddrModeThumbSPOpValue";
198 let DecoderMethod = "DecodeThumbAddrModeSP";
199 let PrintMethod = "printThumbAddrModeSPOperand";
200 let ParserMatchClass = t_addrmode_sp_asm_operand;
201 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
204 // t_addrmode_pc := <label> => pc + imm8 * 4
206 def t_addrmode_pc : Operand<i32> {
207 let EncoderMethod = "getAddrModePCOpValue";
208 let DecoderMethod = "DecodeThumbAddrModePC";
211 //===----------------------------------------------------------------------===//
212 // Miscellaneous Instructions.
215 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
216 // from removing one half of the matched pairs. That breaks PEI, which assumes
217 // these will always be in pairs, and asserts if it finds otherwise. Better way?
218 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
219 def tADJCALLSTACKUP :
220 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
221 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
222 Requires<[IsThumb, IsThumb1Only]>;
224 def tADJCALLSTACKDOWN :
225 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
226 [(ARMcallseq_start imm:$amt)]>,
227 Requires<[IsThumb, IsThumb1Only]>;
230 class T1SystemEncoding<bits<8> opc>
231 : T1Encoding<0b101111> {
232 let Inst{9-8} = 0b11;
236 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
237 T1SystemEncoding<0x00>; // A8.6.110
239 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
240 T1SystemEncoding<0x10>; // A8.6.410
242 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
243 T1SystemEncoding<0x20>; // A8.6.408
245 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
246 T1SystemEncoding<0x30>; // A8.6.409
248 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
249 T1SystemEncoding<0x40>; // A8.6.157
251 // The imm operand $val can be used by a debugger to store more information
252 // about the breakpoint.
253 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
255 T1Encoding<0b101111> {
256 let Inst{9-8} = 0b10;
262 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
263 []>, T1Encoding<0b101101> {
266 let Inst{9-5} = 0b10010;
269 let Inst{2-0} = 0b000;
272 // Change Processor State is a system instruction -- for disassembly only.
273 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
274 NoItinerary, "cps$imod $iflags",
275 [/* For disassembly only; pattern left blank */]>,
283 let Inst{2-0} = iflags;
284 let DecoderMethod = "DecodeThumbCPS";
287 // For both thumb1 and thumb2.
288 let isNotDuplicable = 1, isCodeGenOnly = 1 in
289 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
290 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
291 T1Special<{0,0,?,?}> {
294 let Inst{6-3} = 0b1111; // Rm = pc
298 // ADD <Rd>, sp, #<imm8>
299 // This is rematerializable, which is particularly useful for taking the
300 // address of locals.
301 let isReMaterializable = 1 in
302 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
303 "add\t$dst, $sp, $rhs", []>,
304 T1Encoding<{1,0,1,0,1,?}> {
308 let Inst{10-8} = dst;
310 let DecoderMethod = "DecodeThumbAddSpecialReg";
313 // ADD sp, sp, #<imm7>
314 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
315 "add\t$dst, $rhs", []>,
316 T1Misc<{0,0,0,0,0,?,?}> {
320 let DecoderMethod = "DecodeThumbAddSPImm";
323 // SUB sp, sp, #<imm7>
324 // FIXME: The encoding and the ASM string don't match up.
325 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
326 "sub\t$dst, $rhs", []>,
327 T1Misc<{0,0,0,0,1,?,?}> {
331 let DecoderMethod = "DecodeThumbAddSPImm";
335 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
336 "add\t$dst, $rhs", []>,
337 T1Special<{0,0,?,?}> {
338 // A8.6.9 Encoding T1
340 let Inst{7} = dst{3};
341 let Inst{6-3} = 0b1101;
342 let Inst{2-0} = dst{2-0};
343 let DecoderMethod = "DecodeThumbAddSPReg";
347 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
348 "add\t$dst, $rhs", []>,
349 T1Special<{0,0,?,?}> {
350 // A8.6.9 Encoding T2
354 let Inst{2-0} = 0b101;
355 let DecoderMethod = "DecodeThumbAddSPReg";
358 //===----------------------------------------------------------------------===//
359 // Control Flow Instructions.
363 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
364 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
365 T1Special<{1,1,0,?}> {
369 let Inst{2-0} = 0b000;
373 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
374 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
375 [(ARMretflag)], (tBX LR, pred:$p)>;
377 // Alternative return instruction used by vararg functions.
378 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
380 (tBX GPR:$Rm, pred:$p)>;
383 // All calls clobber the non-callee saved registers. SP is marked as a use to
384 // prevent stack-pointer assignments that appear immediately before calls from
385 // potentially appearing dead.
387 // On non-Darwin platforms R9 is callee-saved.
388 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
390 // Also used for Thumb2
391 def tBL : TIx2<0b11110, 0b11, 1,
392 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
394 [(ARMtcall tglobaladdr:$func)]>,
395 Requires<[IsThumb, IsNotDarwin]> {
397 let Inst{26} = func{21};
398 let Inst{25-16} = func{20-11};
401 let Inst{10-0} = func{10-0};
404 // ARMv5T and above, also used for Thumb2
405 def tBLXi : TIx2<0b11110, 0b11, 0,
406 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
408 [(ARMcall tglobaladdr:$func)]>,
409 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
411 let Inst{25-16} = func{20-11};
414 let Inst{10-1} = func{10-1};
415 let Inst{0} = 0; // func{0} is assumed zero
418 // Also used for Thumb2
419 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
421 [(ARMtcall GPR:$func)]>,
422 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
423 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
425 let Inst{6-3} = func;
426 let Inst{2-0} = 0b000;
430 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
432 [(ARMcall_nolink tGPR:$func)]>,
433 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
437 // On Darwin R9 is call-clobbered.
438 // R7 is marked as a use to prevent frame-pointer assignments from being
439 // moved above / below calls.
440 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
442 // Also used for Thumb2
443 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
444 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
445 (tBL pred:$p, t_bltarget:$func)>,
446 Requires<[IsThumb, IsDarwin]>;
448 // ARMv5T and above, also used for Thumb2
449 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
450 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
451 (tBLXi pred:$p, t_blxtarget:$func)>,
452 Requires<[IsThumb, HasV5T, IsDarwin]>;
454 // Also used for Thumb2
455 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
456 2, IIC_Br, [(ARMtcall GPR:$func)],
457 (tBLXr pred:$p, GPR:$func)>,
458 Requires<[IsThumb, HasV5T, IsDarwin]>;
461 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
463 [(ARMcall_nolink tGPR:$func)]>,
464 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
467 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
468 let isPredicable = 1 in
469 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
470 "b\t$target", [(br bb:$target)]>,
471 T1Encoding<{1,1,1,0,0,?}> {
473 let Inst{10-0} = target;
477 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
478 // the clobber of LR.
480 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
481 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
483 def tBR_JTr : tPseudoInst<(outs),
484 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
486 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
487 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
491 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
492 // a two-value operand where a dag node expects two operands. :(
493 let isBranch = 1, isTerminator = 1 in
494 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
496 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
497 T1BranchCond<{1,1,0,1}> {
501 let Inst{7-0} = target;
505 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
507 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
509 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
510 // on Darwin), so it's in ARMInstrThumb2.td.
511 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
513 (tBX GPR:$dst, (ops 14, zero_reg))>,
514 Requires<[IsThumb, IsDarwin]>;
516 // Non-Darwin versions (the difference is R9).
517 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
519 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
521 (tB t_brtarget:$dst)>,
522 Requires<[IsThumb, IsNotDarwin]>;
523 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
525 (tBX GPR:$dst, (ops 14, zero_reg))>,
526 Requires<[IsThumb, IsNotDarwin]>;
531 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
532 // A8.6.16 B: Encoding T1
533 // If Inst{11-8} == 0b1111 then SEE SVC
534 let isCall = 1, Uses = [SP] in
535 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
536 "svc", "\t$imm", []>, Encoding16 {
538 let Inst{15-12} = 0b1101;
539 let Inst{11-8} = 0b1111;
543 // The assembler uses 0xDEFE for a trap instruction.
544 let isBarrier = 1, isTerminator = 1 in
545 def tTRAP : TI<(outs), (ins), IIC_Br,
546 "trap", [(trap)]>, Encoding16 {
550 //===----------------------------------------------------------------------===//
551 // Load Store Instructions.
554 // Loads: reg/reg and reg/imm5
555 let canFoldAsLoad = 1, isReMaterializable = 1 in
556 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
557 Operand AddrMode_r, Operand AddrMode_i,
558 AddrMode am, InstrItinClass itin_r,
559 InstrItinClass itin_i, string asm,
562 T1pILdStEncode<reg_opc,
563 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
564 am, itin_r, asm, "\t$Rt, $addr",
565 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
567 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
568 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
569 am, itin_i, asm, "\t$Rt, $addr",
570 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
572 // Stores: reg/reg and reg/imm5
573 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
574 Operand AddrMode_r, Operand AddrMode_i,
575 AddrMode am, InstrItinClass itin_r,
576 InstrItinClass itin_i, string asm,
579 T1pILdStEncode<reg_opc,
580 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
581 am, itin_r, asm, "\t$Rt, $addr",
582 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
584 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
585 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
586 am, itin_i, asm, "\t$Rt, $addr",
587 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
591 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
592 t_addrmode_is4, AddrModeT1_4,
593 IIC_iLoad_r, IIC_iLoad_i, "ldr",
594 UnOpFrag<(load node:$Src)>>;
597 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
598 t_addrmode_is1, AddrModeT1_1,
599 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
600 UnOpFrag<(zextloadi8 node:$Src)>>;
603 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
604 t_addrmode_is2, AddrModeT1_2,
605 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
606 UnOpFrag<(zextloadi16 node:$Src)>>;
608 let AddedComplexity = 10 in
609 def tLDRSB : // A8.6.80
610 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
611 AddrModeT1_1, IIC_iLoad_bh_r,
612 "ldrsb", "\t$Rt, $addr",
613 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
615 let AddedComplexity = 10 in
616 def tLDRSH : // A8.6.84
617 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
618 AddrModeT1_2, IIC_iLoad_bh_r,
619 "ldrsh", "\t$Rt, $addr",
620 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
622 let canFoldAsLoad = 1 in
623 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
624 "ldr", "\t$Rt, $addr",
625 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
630 let Inst{7-0} = addr;
634 // FIXME: Use ldr.n to work around a Darwin assembler bug.
635 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
636 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
637 "ldr", ".n\t$Rt, $addr",
638 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
639 T1Encoding<{0,1,0,0,1,?}> {
644 let Inst{7-0} = addr;
647 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
648 // For disassembly use only.
649 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
650 "ldr", "\t$Rt, $addr",
651 [/* disassembly only */]>,
652 T1Encoding<{0,1,0,0,1,?}> {
657 let Inst{7-0} = addr;
660 // A8.6.194 & A8.6.192
661 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
662 t_addrmode_is4, AddrModeT1_4,
663 IIC_iStore_r, IIC_iStore_i, "str",
664 BinOpFrag<(store node:$LHS, node:$RHS)>>;
666 // A8.6.197 & A8.6.195
667 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
668 t_addrmode_is1, AddrModeT1_1,
669 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
670 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
672 // A8.6.207 & A8.6.205
673 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
674 t_addrmode_is2, AddrModeT1_2,
675 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
676 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
679 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
680 "str", "\t$Rt, $addr",
681 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
686 let Inst{7-0} = addr;
689 //===----------------------------------------------------------------------===//
690 // Load / store multiple Instructions.
693 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
694 InstrItinClass itin_upd, bits<6> T1Enc,
695 bit L_bit, string baseOpc> {
697 T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
698 itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
703 let Inst{7-0} = regs;
707 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
708 "$Rn = $wb", itin_upd>,
709 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
710 tGPR:$Rn, pred:$p, reglist:$regs)> {
712 let OutOperandList = (outs GPR:$wb);
713 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
715 let isCodeGenOnly = 1;
717 list<Predicate> Predicates = [IsThumb];
721 // These require base address to be written back or one of the loaded regs.
722 let neverHasSideEffects = 1 in {
724 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
725 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
726 {1,1,0,0,1,?}, 1, "tLDM">;
728 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
729 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
730 {1,1,0,0,0,?}, 0, "tSTM">;
732 } // neverHasSideEffects
734 def : InstAlias<"ldm${p} $Rn!, $regs",
735 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
736 Requires<[IsThumb, IsThumb1Only]>;
739 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
740 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
742 "pop${p}\t$regs", []>,
743 T1Misc<{1,1,0,?,?,?,?}> {
745 let Inst{8} = regs{15};
746 let Inst{7-0} = regs{7-0};
749 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
750 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
752 "push${p}\t$regs", []>,
753 T1Misc<{0,1,0,?,?,?,?}> {
755 let Inst{8} = regs{14};
756 let Inst{7-0} = regs{7-0};
759 //===----------------------------------------------------------------------===//
760 // Arithmetic Instructions.
763 // Helper classes for encoding T1pI patterns:
764 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
765 string opc, string asm, list<dag> pattern>
766 : T1pI<oops, iops, itin, opc, asm, pattern>,
767 T1DataProcessing<opA> {
773 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
774 string opc, string asm, list<dag> pattern>
775 : T1pI<oops, iops, itin, opc, asm, pattern>,
783 // Helper classes for encoding T1sI patterns:
784 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
785 string opc, string asm, list<dag> pattern>
786 : T1sI<oops, iops, itin, opc, asm, pattern>,
787 T1DataProcessing<opA> {
793 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
794 string opc, string asm, list<dag> pattern>
795 : T1sI<oops, iops, itin, opc, asm, pattern>,
804 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
805 string opc, string asm, list<dag> pattern>
806 : T1sI<oops, iops, itin, opc, asm, pattern>,
814 // Helper classes for encoding T1sIt patterns:
815 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
816 string opc, string asm, list<dag> pattern>
817 : T1sIt<oops, iops, itin, opc, asm, pattern>,
818 T1DataProcessing<opA> {
824 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
825 string opc, string asm, list<dag> pattern>
826 : T1sIt<oops, iops, itin, opc, asm, pattern>,
830 let Inst{10-8} = Rdn;
831 let Inst{7-0} = imm8;
834 // Add with carry register
835 let isCommutable = 1, Uses = [CPSR] in
837 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
838 "adc", "\t$Rdn, $Rm",
839 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
842 def tADDi3 : // A8.6.4 T1
843 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
845 "add", "\t$Rd, $Rm, $imm3",
846 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
848 let Inst{8-6} = imm3;
851 def tADDi8 : // A8.6.4 T2
852 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
853 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
854 "add", "\t$Rdn, $imm8",
855 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
858 let isCommutable = 1 in
859 def tADDrr : // A8.6.6 T1
860 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
862 "add", "\t$Rd, $Rn, $Rm",
863 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
865 let neverHasSideEffects = 1 in
866 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
867 "add", "\t$Rdn, $Rm", []>,
868 T1Special<{0,0,?,?}> {
872 let Inst{7} = Rdn{3};
874 let Inst{2-0} = Rdn{2-0};
878 let isCommutable = 1 in
879 def tAND : // A8.6.12
880 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
882 "and", "\t$Rdn, $Rm",
883 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
886 def tASRri : // A8.6.14
887 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
889 "asr", "\t$Rd, $Rm, $imm5",
890 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
892 let Inst{10-6} = imm5;
896 def tASRrr : // A8.6.15
897 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
899 "asr", "\t$Rdn, $Rm",
900 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
903 def tBIC : // A8.6.20
904 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
906 "bic", "\t$Rdn, $Rm",
907 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
910 let isCompare = 1, Defs = [CPSR] in {
911 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
912 // Compare-to-zero still works out, just not the relationals
913 //def tCMN : // A8.6.33
914 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
916 // "cmn", "\t$lhs, $rhs",
917 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
919 def tCMNz : // A8.6.33
920 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
923 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
925 } // isCompare = 1, Defs = [CPSR]
928 let isCompare = 1, Defs = [CPSR] in {
929 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
930 "cmp", "\t$Rn, $imm8",
931 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
932 T1General<{1,0,1,?,?}> {
937 let Inst{7-0} = imm8;
941 def tCMPr : // A8.6.36 T1
942 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
945 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
947 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
948 "cmp", "\t$Rn, $Rm", []>,
949 T1Special<{0,1,?,?}> {
955 let Inst{2-0} = Rn{2-0};
957 } // isCompare = 1, Defs = [CPSR]
961 let isCommutable = 1 in
962 def tEOR : // A8.6.45
963 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
965 "eor", "\t$Rdn, $Rm",
966 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
969 def tLSLri : // A8.6.88
970 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
972 "lsl", "\t$Rd, $Rm, $imm5",
973 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
975 let Inst{10-6} = imm5;
979 def tLSLrr : // A8.6.89
980 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
982 "lsl", "\t$Rdn, $Rm",
983 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
986 def tLSRri : // A8.6.90
987 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
989 "lsr", "\t$Rd, $Rm, $imm5",
990 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
992 let Inst{10-6} = imm5;
996 def tLSRrr : // A8.6.91
997 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
999 "lsr", "\t$Rdn, $Rm",
1000 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1003 let isMoveImm = 1 in
1004 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1005 "mov", "\t$Rd, $imm8",
1006 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1007 T1General<{1,0,0,?,?}> {
1011 let Inst{10-8} = Rd;
1012 let Inst{7-0} = imm8;
1015 // A7-73: MOV(2) - mov setting flag.
1017 let neverHasSideEffects = 1 in {
1018 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1020 "mov", "\t$Rd, $Rm", "", []>,
1021 T1Special<{1,0,?,?}> {
1025 let Inst{7} = Rd{3};
1027 let Inst{2-0} = Rd{2-0};
1029 let Defs = [CPSR] in
1030 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1031 "movs\t$Rd, $Rm", []>, Encoding16 {
1035 let Inst{15-6} = 0b0000000000;
1039 } // neverHasSideEffects
1041 // Multiply register
1042 let isCommutable = 1 in
1043 def tMUL : // A8.6.105 T1
1044 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1046 "mul", "\t$Rdn, $Rm, $Rdn",
1047 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1049 // Move inverse register
1050 def tMVN : // A8.6.107
1051 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1052 "mvn", "\t$Rd, $Rn",
1053 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1055 // Bitwise or register
1056 let isCommutable = 1 in
1057 def tORR : // A8.6.114
1058 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1060 "orr", "\t$Rdn, $Rm",
1061 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1064 def tREV : // A8.6.134
1065 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1067 "rev", "\t$Rd, $Rm",
1068 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1069 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1071 def tREV16 : // A8.6.135
1072 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1074 "rev16", "\t$Rd, $Rm",
1075 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1076 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1078 def tREVSH : // A8.6.136
1079 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1081 "revsh", "\t$Rd, $Rm",
1082 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1083 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1085 // Rotate right register
1086 def tROR : // A8.6.139
1087 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1089 "ror", "\t$Rdn, $Rm",
1090 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1093 def tRSB : // A8.6.141
1094 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1096 "rsb", "\t$Rd, $Rn, #0",
1097 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1099 // Subtract with carry register
1100 let Uses = [CPSR] in
1101 def tSBC : // A8.6.151
1102 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1104 "sbc", "\t$Rdn, $Rm",
1105 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1107 // Subtract immediate
1108 def tSUBi3 : // A8.6.210 T1
1109 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1111 "sub", "\t$Rd, $Rm, $imm3",
1112 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1114 let Inst{8-6} = imm3;
1117 def tSUBi8 : // A8.6.210 T2
1118 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1120 "sub", "\t$Rdn, $imm8",
1121 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1123 // Subtract register
1124 def tSUBrr : // A8.6.212
1125 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1127 "sub", "\t$Rd, $Rn, $Rm",
1128 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1130 // TODO: A7-96: STMIA - store multiple.
1133 def tSXTB : // A8.6.222
1134 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1136 "sxtb", "\t$Rd, $Rm",
1137 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1138 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1140 // Sign-extend short
1141 def tSXTH : // A8.6.224
1142 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1144 "sxth", "\t$Rd, $Rm",
1145 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1146 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1149 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1150 def tTST : // A8.6.230
1151 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1152 "tst", "\t$Rn, $Rm",
1153 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1156 def tUXTB : // A8.6.262
1157 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1159 "uxtb", "\t$Rd, $Rm",
1160 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1161 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1163 // Zero-extend short
1164 def tUXTH : // A8.6.264
1165 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1167 "uxth", "\t$Rd, $Rm",
1168 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1169 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1171 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1172 // Expanded after instruction selection into a branch sequence.
1173 let usesCustomInserter = 1 in // Expanded after instruction selection.
1174 def tMOVCCr_pseudo :
1175 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1177 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1179 // tLEApcrel - Load a pc-relative address into a register without offending the
1182 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1183 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1184 T1Encoding<{1,0,1,0,0,?}> {
1187 let Inst{10-8} = Rd;
1188 let Inst{7-0} = addr;
1189 let DecoderMethod = "DecodeThumbAddSpecialReg";
1192 let neverHasSideEffects = 1, isReMaterializable = 1 in
1193 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1196 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1197 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1200 //===----------------------------------------------------------------------===//
1204 // __aeabi_read_tp preserves the registers r1-r3.
1205 // This is a pseudo inst so that we can get the encoding right,
1206 // complete with fixup for the aeabi_read_tp function.
1207 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1208 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1209 [(set R0, ARMthread_pointer)]>;
1211 //===----------------------------------------------------------------------===//
1212 // SJLJ Exception handling intrinsics
1215 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1216 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1217 // from some other function to get here, and we're using the stack frame for the
1218 // containing function to save/restore registers, we can't keep anything live in
1219 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1220 // tromped upon when we get here from a longjmp(). We force everything out of
1221 // registers except for our own input by listing the relevant registers in
1222 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1223 // preserve all of the callee-saved resgisters, which is exactly what we want.
1224 // $val is a scratch register for our use.
1225 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1226 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1227 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1228 AddrModeNone, 0, NoItinerary, "","",
1229 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1231 // FIXME: Non-Darwin version(s)
1232 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1233 Defs = [ R7, LR, SP ] in
1234 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1235 AddrModeNone, 0, IndexModeNone,
1236 Pseudo, NoItinerary, "", "",
1237 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1238 Requires<[IsThumb, IsDarwin]>;
1240 //===----------------------------------------------------------------------===//
1241 // Non-Instruction Patterns
1245 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1246 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1247 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1248 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1251 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1252 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1253 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1254 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1255 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1256 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1258 // Subtract with carry
1259 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1260 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1261 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1262 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1263 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1264 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1266 // ConstantPool, GlobalAddress
1267 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1268 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1271 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1272 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1275 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1276 Requires<[IsThumb, IsNotDarwin]>;
1277 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1278 Requires<[IsThumb, IsDarwin]>;
1280 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1281 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1282 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1283 Requires<[IsThumb, HasV5T, IsDarwin]>;
1285 // Indirect calls to ARM routines
1286 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1287 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1288 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1289 Requires<[IsThumb, HasV5T, IsDarwin]>;
1291 // zextload i1 -> zextload i8
1292 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1293 (tLDRBr t_addrmode_rrs1:$addr)>;
1294 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1295 (tLDRBi t_addrmode_is1:$addr)>;
1297 // extload -> zextload
1298 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1299 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1300 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1301 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1302 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1303 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1305 // If it's impossible to use [r,r] address mode for sextload, select to
1306 // ldr{b|h} + sxt{b|h} instead.
1307 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1308 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1309 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1310 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1311 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1312 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1313 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1314 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1315 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1316 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1317 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1318 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1320 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1321 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1322 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1323 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1324 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1325 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1326 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1327 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1329 // Large immediate handling.
1332 def : T1Pat<(i32 thumb_immshifted:$src),
1333 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1334 (thumb_immshifted_shamt imm:$src))>;
1336 def : T1Pat<(i32 imm0_255_comp:$src),
1337 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1339 // Pseudo instruction that combines ldr from constpool and add pc. This should
1340 // be expanded into two instructions late to allow if-conversion and
1342 let isReMaterializable = 1 in
1343 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1345 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1347 Requires<[IsThumb, IsThumb1Only]>;
1349 // Pseudo-instruction for merged POP and return.
1350 // FIXME: remove when we have a way to marking a MI with these properties.
1351 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1352 hasExtraDefRegAllocReq = 1 in
1353 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1355 (tPOP pred:$p, reglist:$regs)>;
1357 // Indirect branch using "mov pc, $Rm"
1358 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1359 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1360 2, IIC_Br, [(brind GPR:$Rm)],
1361 (tMOVr PC, GPR:$Rm, pred:$p)>;