1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let ParserMatchClass = t_addrmode_rr_asm_operand;
124 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127 // t_addrmode_rrs := reg + reg
129 // We use separate scaled versions because the Select* functions need
130 // to explicitly check for a matching constant and return false here so that
131 // the reg+imm forms will match instead. This is a horrible way to do that,
132 // as it forces tight coupling between the methods, but it's how selectiondag
134 def t_addrmode_rrs1 : Operand<i32>,
135 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
136 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
137 let PrintMethod = "printThumbAddrModeRROperand";
138 let DecoderMethod = "DecodeThumbAddrModeRR";
139 let ParserMatchClass = t_addrmode_rr_asm_operand;
140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
142 def t_addrmode_rrs2 : Operand<i32>,
143 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
144 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
145 let DecoderMethod = "DecodeThumbAddrModeRR";
146 let PrintMethod = "printThumbAddrModeRROperand";
147 let ParserMatchClass = t_addrmode_rr_asm_operand;
148 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
150 def t_addrmode_rrs4 : Operand<i32>,
151 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
152 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
153 let DecoderMethod = "DecodeThumbAddrModeRR";
154 let PrintMethod = "printThumbAddrModeRROperand";
155 let ParserMatchClass = t_addrmode_rr_asm_operand;
156 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
159 // t_addrmode_is4 := reg + imm5 * 4
161 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
162 def t_addrmode_is4 : Operand<i32>,
163 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
164 let EncoderMethod = "getAddrModeISOpValue";
165 let DecoderMethod = "DecodeThumbAddrModeIS";
166 let PrintMethod = "printThumbAddrModeImm5S4Operand";
167 let ParserMatchClass = t_addrmode_is4_asm_operand;
168 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171 // t_addrmode_is2 := reg + imm5 * 2
173 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
174 def t_addrmode_is2 : Operand<i32>,
175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
176 let EncoderMethod = "getAddrModeISOpValue";
177 let DecoderMethod = "DecodeThumbAddrModeIS";
178 let PrintMethod = "printThumbAddrModeImm5S2Operand";
179 let ParserMatchClass = t_addrmode_is2_asm_operand;
180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
183 // t_addrmode_is1 := reg + imm5
185 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
186 def t_addrmode_is1 : Operand<i32>,
187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
188 let EncoderMethod = "getAddrModeISOpValue";
189 let DecoderMethod = "DecodeThumbAddrModeIS";
190 let PrintMethod = "printThumbAddrModeImm5S1Operand";
191 let ParserMatchClass = t_addrmode_is1_asm_operand;
192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
195 // t_addrmode_sp := sp + imm8 * 4
197 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
198 def t_addrmode_sp : Operand<i32>,
199 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
200 let EncoderMethod = "getAddrModeThumbSPOpValue";
201 let DecoderMethod = "DecodeThumbAddrModeSP";
202 let PrintMethod = "printThumbAddrModeSPOperand";
203 let ParserMatchClass = t_addrmode_sp_asm_operand;
204 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
207 // t_addrmode_pc := <label> => pc + imm8 * 4
209 def t_addrmode_pc : Operand<i32> {
210 let EncoderMethod = "getAddrModePCOpValue";
211 let DecoderMethod = "DecodeThumbAddrModePC";
214 //===----------------------------------------------------------------------===//
215 // Miscellaneous Instructions.
218 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
219 // from removing one half of the matched pairs. That breaks PEI, which assumes
220 // these will always be in pairs, and asserts if it finds otherwise. Better way?
221 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
222 def tADJCALLSTACKUP :
223 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
224 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
225 Requires<[IsThumb, IsThumb1Only]>;
227 def tADJCALLSTACKDOWN :
228 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
229 [(ARMcallseq_start imm:$amt)]>,
230 Requires<[IsThumb, IsThumb1Only]>;
233 class T1SystemEncoding<bits<8> opc>
234 : T1Encoding<0b101111> {
235 let Inst{9-8} = 0b11;
239 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
240 T1SystemEncoding<0x00>, // A8.6.110
241 Requires<[IsThumb2]>;
243 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
244 T1SystemEncoding<0x10>; // A8.6.410
246 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
247 T1SystemEncoding<0x20>; // A8.6.408
249 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
250 T1SystemEncoding<0x30>; // A8.6.409
252 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
253 T1SystemEncoding<0x40>; // A8.6.157
255 // The imm operand $val can be used by a debugger to store more information
256 // about the breakpoint.
257 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
259 T1Encoding<0b101111> {
260 let Inst{9-8} = 0b10;
266 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
267 []>, T1Encoding<0b101101> {
270 let Inst{9-5} = 0b10010;
273 let Inst{2-0} = 0b000;
276 // Change Processor State is a system instruction -- for disassembly only.
277 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
278 NoItinerary, "cps$imod $iflags",
279 [/* For disassembly only; pattern left blank */]>,
287 let Inst{2-0} = iflags;
288 let DecoderMethod = "DecodeThumbCPS";
291 // For both thumb1 and thumb2.
292 let isNotDuplicable = 1, isCodeGenOnly = 1 in
293 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
294 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
295 T1Special<{0,0,?,?}> {
298 let Inst{6-3} = 0b1111; // Rm = pc
302 // ADD <Rd>, sp, #<imm8>
303 // This is rematerializable, which is particularly useful for taking the
304 // address of locals.
305 let isReMaterializable = 1 in
306 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
307 "add\t$dst, $sp, $rhs", []>,
308 T1Encoding<{1,0,1,0,1,?}> {
312 let Inst{10-8} = dst;
314 let DecoderMethod = "DecodeThumbAddSpecialReg";
317 // ADD sp, sp, #<imm7>
318 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
319 "add\t$dst, $rhs", []>,
320 T1Misc<{0,0,0,0,0,?,?}> {
324 let DecoderMethod = "DecodeThumbAddSPImm";
327 // SUB sp, sp, #<imm7>
328 // FIXME: The encoding and the ASM string don't match up.
329 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
330 "sub\t$dst, $rhs", []>,
331 T1Misc<{0,0,0,0,1,?,?}> {
335 let DecoderMethod = "DecodeThumbAddSPImm";
339 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
340 "add\t$dst, $rhs", []>,
341 T1Special<{0,0,?,?}> {
342 // A8.6.9 Encoding T1
344 let Inst{7} = dst{3};
345 let Inst{6-3} = 0b1101;
346 let Inst{2-0} = dst{2-0};
347 let DecoderMethod = "DecodeThumbAddSPReg";
351 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
352 "add\t$dst, $rhs", []>,
353 T1Special<{0,0,?,?}> {
354 // A8.6.9 Encoding T2
358 let Inst{2-0} = 0b101;
359 let DecoderMethod = "DecodeThumbAddSPReg";
362 //===----------------------------------------------------------------------===//
363 // Control Flow Instructions.
367 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
368 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
369 T1Special<{1,1,0,?}> {
373 let Inst{2-0} = 0b000;
377 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
378 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
379 [(ARMretflag)], (tBX LR, pred:$p)>;
381 // Alternative return instruction used by vararg functions.
382 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
384 (tBX GPR:$Rm, pred:$p)>;
387 // All calls clobber the non-callee saved registers. SP is marked as a use to
388 // prevent stack-pointer assignments that appear immediately before calls from
389 // potentially appearing dead.
391 // On non-Darwin platforms R9 is callee-saved.
392 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
394 // Also used for Thumb2
395 def tBL : TIx2<0b11110, 0b11, 1,
396 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
398 [(ARMtcall tglobaladdr:$func)]>,
399 Requires<[IsThumb, IsNotDarwin]> {
401 let Inst{26} = func{21};
402 let Inst{25-16} = func{20-11};
405 let Inst{10-0} = func{10-0};
408 // ARMv5T and above, also used for Thumb2
409 def tBLXi : TIx2<0b11110, 0b11, 0,
410 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
412 [(ARMcall tglobaladdr:$func)]>,
413 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
415 let Inst{25-16} = func{20-11};
418 let Inst{10-1} = func{10-1};
419 let Inst{0} = 0; // func{0} is assumed zero
422 // Also used for Thumb2
423 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
425 [(ARMtcall GPR:$func)]>,
426 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
427 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
429 let Inst{6-3} = func;
430 let Inst{2-0} = 0b000;
434 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
436 [(ARMcall_nolink tGPR:$func)]>,
437 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
441 // On Darwin R9 is call-clobbered.
442 // R7 is marked as a use to prevent frame-pointer assignments from being
443 // moved above / below calls.
444 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
446 // Also used for Thumb2
447 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
448 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
449 (tBL pred:$p, t_bltarget:$func)>,
450 Requires<[IsThumb, IsDarwin]>;
452 // ARMv5T and above, also used for Thumb2
453 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
454 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
455 (tBLXi pred:$p, t_blxtarget:$func)>,
456 Requires<[IsThumb, HasV5T, IsDarwin]>;
458 // Also used for Thumb2
459 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
460 2, IIC_Br, [(ARMtcall GPR:$func)],
461 (tBLXr pred:$p, GPR:$func)>,
462 Requires<[IsThumb, HasV5T, IsDarwin]>;
465 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
467 [(ARMcall_nolink tGPR:$func)]>,
468 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
471 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
472 let isPredicable = 1 in
473 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
474 "b\t$target", [(br bb:$target)]>,
475 T1Encoding<{1,1,1,0,0,?}> {
477 let Inst{10-0} = target;
481 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
482 // the clobber of LR.
484 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
485 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
487 def tBR_JTr : tPseudoInst<(outs),
488 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
490 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
491 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
495 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
496 // a two-value operand where a dag node expects two operands. :(
497 let isBranch = 1, isTerminator = 1 in
498 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
500 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
501 T1BranchCond<{1,1,0,1}> {
505 let Inst{7-0} = target;
509 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
511 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
513 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
514 // on Darwin), so it's in ARMInstrThumb2.td.
515 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
517 (tBX GPR:$dst, (ops 14, zero_reg))>,
518 Requires<[IsThumb, IsDarwin]>;
520 // Non-Darwin versions (the difference is R9).
521 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
523 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
525 (tB t_brtarget:$dst)>,
526 Requires<[IsThumb, IsNotDarwin]>;
527 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
529 (tBX GPR:$dst, (ops 14, zero_reg))>,
530 Requires<[IsThumb, IsNotDarwin]>;
535 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
536 // A8.6.16 B: Encoding T1
537 // If Inst{11-8} == 0b1111 then SEE SVC
538 let isCall = 1, Uses = [SP] in
539 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
540 "svc", "\t$imm", []>, Encoding16 {
542 let Inst{15-12} = 0b1101;
543 let Inst{11-8} = 0b1111;
547 // The assembler uses 0xDEFE for a trap instruction.
548 let isBarrier = 1, isTerminator = 1 in
549 def tTRAP : TI<(outs), (ins), IIC_Br,
550 "trap", [(trap)]>, Encoding16 {
554 //===----------------------------------------------------------------------===//
555 // Load Store Instructions.
558 // Loads: reg/reg and reg/imm5
559 let canFoldAsLoad = 1, isReMaterializable = 1 in
560 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
561 Operand AddrMode_r, Operand AddrMode_i,
562 AddrMode am, InstrItinClass itin_r,
563 InstrItinClass itin_i, string asm,
566 T1pILdStEncode<reg_opc,
567 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
568 am, itin_r, asm, "\t$Rt, $addr",
569 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
571 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
572 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
573 am, itin_i, asm, "\t$Rt, $addr",
574 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
576 // Stores: reg/reg and reg/imm5
577 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
578 Operand AddrMode_r, Operand AddrMode_i,
579 AddrMode am, InstrItinClass itin_r,
580 InstrItinClass itin_i, string asm,
583 T1pILdStEncode<reg_opc,
584 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
585 am, itin_r, asm, "\t$Rt, $addr",
586 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
588 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
589 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
590 am, itin_i, asm, "\t$Rt, $addr",
591 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
595 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
596 t_addrmode_is4, AddrModeT1_4,
597 IIC_iLoad_r, IIC_iLoad_i, "ldr",
598 UnOpFrag<(load node:$Src)>>;
601 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
602 t_addrmode_is1, AddrModeT1_1,
603 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
604 UnOpFrag<(zextloadi8 node:$Src)>>;
607 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
608 t_addrmode_is2, AddrModeT1_2,
609 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
610 UnOpFrag<(zextloadi16 node:$Src)>>;
612 let AddedComplexity = 10 in
613 def tLDRSB : // A8.6.80
614 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
615 AddrModeT1_1, IIC_iLoad_bh_r,
616 "ldrsb", "\t$Rt, $addr",
617 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
619 let AddedComplexity = 10 in
620 def tLDRSH : // A8.6.84
621 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
622 AddrModeT1_2, IIC_iLoad_bh_r,
623 "ldrsh", "\t$Rt, $addr",
624 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
626 let canFoldAsLoad = 1 in
627 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
628 "ldr", "\t$Rt, $addr",
629 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
634 let Inst{7-0} = addr;
638 // FIXME: Use ldr.n to work around a Darwin assembler bug.
639 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
640 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
641 "ldr", ".n\t$Rt, $addr",
642 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
643 T1Encoding<{0,1,0,0,1,?}> {
648 let Inst{7-0} = addr;
651 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
652 // For disassembly use only.
653 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
654 "ldr", "\t$Rt, $addr",
655 [/* disassembly only */]>,
656 T1Encoding<{0,1,0,0,1,?}> {
661 let Inst{7-0} = addr;
664 // A8.6.194 & A8.6.192
665 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
666 t_addrmode_is4, AddrModeT1_4,
667 IIC_iStore_r, IIC_iStore_i, "str",
668 BinOpFrag<(store node:$LHS, node:$RHS)>>;
670 // A8.6.197 & A8.6.195
671 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
672 t_addrmode_is1, AddrModeT1_1,
673 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
674 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
676 // A8.6.207 & A8.6.205
677 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
678 t_addrmode_is2, AddrModeT1_2,
679 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
680 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
683 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
684 "str", "\t$Rt, $addr",
685 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
690 let Inst{7-0} = addr;
693 //===----------------------------------------------------------------------===//
694 // Load / store multiple Instructions.
697 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
698 InstrItinClass itin_upd, bits<6> T1Enc,
699 bit L_bit, string baseOpc> {
701 T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
702 itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
707 let Inst{7-0} = regs;
711 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
712 "$Rn = $wb", itin_upd>,
713 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
714 tGPR:$Rn, pred:$p, reglist:$regs)> {
716 let OutOperandList = (outs GPR:$wb);
717 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
719 let isCodeGenOnly = 1;
721 list<Predicate> Predicates = [IsThumb];
725 // These require base address to be written back or one of the loaded regs.
726 let neverHasSideEffects = 1 in {
728 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
729 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
730 {1,1,0,0,1,?}, 1, "tLDM">;
732 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
733 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
734 {1,1,0,0,0,?}, 0, "tSTM">;
736 } // neverHasSideEffects
738 def : InstAlias<"ldm${p} $Rn!, $regs",
739 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
740 Requires<[IsThumb, IsThumb1Only]>;
743 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
744 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
746 "pop${p}\t$regs", []>,
747 T1Misc<{1,1,0,?,?,?,?}> {
749 let Inst{8} = regs{15};
750 let Inst{7-0} = regs{7-0};
753 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
754 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
756 "push${p}\t$regs", []>,
757 T1Misc<{0,1,0,?,?,?,?}> {
759 let Inst{8} = regs{14};
760 let Inst{7-0} = regs{7-0};
763 //===----------------------------------------------------------------------===//
764 // Arithmetic Instructions.
767 // Helper classes for encoding T1pI patterns:
768 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
769 string opc, string asm, list<dag> pattern>
770 : T1pI<oops, iops, itin, opc, asm, pattern>,
771 T1DataProcessing<opA> {
777 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
778 string opc, string asm, list<dag> pattern>
779 : T1pI<oops, iops, itin, opc, asm, pattern>,
787 // Helper classes for encoding T1sI patterns:
788 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
789 string opc, string asm, list<dag> pattern>
790 : T1sI<oops, iops, itin, opc, asm, pattern>,
791 T1DataProcessing<opA> {
797 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
798 string opc, string asm, list<dag> pattern>
799 : T1sI<oops, iops, itin, opc, asm, pattern>,
808 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : T1sI<oops, iops, itin, opc, asm, pattern>,
818 // Helper classes for encoding T1sIt patterns:
819 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
820 string opc, string asm, list<dag> pattern>
821 : T1sIt<oops, iops, itin, opc, asm, pattern>,
822 T1DataProcessing<opA> {
828 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
829 string opc, string asm, list<dag> pattern>
830 : T1sIt<oops, iops, itin, opc, asm, pattern>,
834 let Inst{10-8} = Rdn;
835 let Inst{7-0} = imm8;
838 // Add with carry register
839 let isCommutable = 1, Uses = [CPSR] in
841 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
842 "adc", "\t$Rdn, $Rm",
843 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
846 def tADDi3 : // A8.6.4 T1
847 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
849 "add", "\t$Rd, $Rm, $imm3",
850 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
852 let Inst{8-6} = imm3;
855 def tADDi8 : // A8.6.4 T2
856 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
857 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
858 "add", "\t$Rdn, $imm8",
859 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
862 let isCommutable = 1 in
863 def tADDrr : // A8.6.6 T1
864 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
866 "add", "\t$Rd, $Rn, $Rm",
867 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
869 let neverHasSideEffects = 1 in
870 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
871 "add", "\t$Rdn, $Rm", []>,
872 T1Special<{0,0,?,?}> {
876 let Inst{7} = Rdn{3};
878 let Inst{2-0} = Rdn{2-0};
882 let isCommutable = 1 in
883 def tAND : // A8.6.12
884 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
886 "and", "\t$Rdn, $Rm",
887 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
890 def tASRri : // A8.6.14
891 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
893 "asr", "\t$Rd, $Rm, $imm5",
894 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
896 let Inst{10-6} = imm5;
900 def tASRrr : // A8.6.15
901 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
903 "asr", "\t$Rdn, $Rm",
904 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
907 def tBIC : // A8.6.20
908 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
910 "bic", "\t$Rdn, $Rm",
911 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
914 let isCompare = 1, Defs = [CPSR] in {
915 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
916 // Compare-to-zero still works out, just not the relationals
917 //def tCMN : // A8.6.33
918 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
920 // "cmn", "\t$lhs, $rhs",
921 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
923 def tCMNz : // A8.6.33
924 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
927 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
929 } // isCompare = 1, Defs = [CPSR]
932 let isCompare = 1, Defs = [CPSR] in {
933 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
934 "cmp", "\t$Rn, $imm8",
935 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
936 T1General<{1,0,1,?,?}> {
941 let Inst{7-0} = imm8;
945 def tCMPr : // A8.6.36 T1
946 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
949 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
951 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
952 "cmp", "\t$Rn, $Rm", []>,
953 T1Special<{0,1,?,?}> {
959 let Inst{2-0} = Rn{2-0};
961 } // isCompare = 1, Defs = [CPSR]
965 let isCommutable = 1 in
966 def tEOR : // A8.6.45
967 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
969 "eor", "\t$Rdn, $Rm",
970 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
973 def tLSLri : // A8.6.88
974 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
976 "lsl", "\t$Rd, $Rm, $imm5",
977 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
979 let Inst{10-6} = imm5;
983 def tLSLrr : // A8.6.89
984 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
986 "lsl", "\t$Rdn, $Rm",
987 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
990 def tLSRri : // A8.6.90
991 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
993 "lsr", "\t$Rd, $Rm, $imm5",
994 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
996 let Inst{10-6} = imm5;
1000 def tLSRrr : // A8.6.91
1001 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1003 "lsr", "\t$Rdn, $Rm",
1004 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1007 let isMoveImm = 1 in
1008 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1009 "mov", "\t$Rd, $imm8",
1010 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1011 T1General<{1,0,0,?,?}> {
1015 let Inst{10-8} = Rd;
1016 let Inst{7-0} = imm8;
1018 // Because we have an explicit tMOVSr below, we need an alias to handle
1019 // the immediate "movs" form here. Blech.
1020 def : tInstAlias <"movs $Rdn, $imm",
1021 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1023 // A7-73: MOV(2) - mov setting flag.
1025 let neverHasSideEffects = 1 in {
1026 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1028 "mov", "\t$Rd, $Rm", "", []>,
1029 T1Special<{1,0,?,?}> {
1033 let Inst{7} = Rd{3};
1035 let Inst{2-0} = Rd{2-0};
1037 let Defs = [CPSR] in
1038 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1039 "movs\t$Rd, $Rm", []>, Encoding16 {
1043 let Inst{15-6} = 0b0000000000;
1047 } // neverHasSideEffects
1049 // Multiply register
1050 //let isCommutable = 1 in
1051 def tMUL : // A8.6.105 T1
1052 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1053 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1054 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1055 T1DataProcessing<0b1101> {
1060 let AsmMatchConverter = "cvtThumbMultiply";
1063 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1066 // Move inverse register
1067 def tMVN : // A8.6.107
1068 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1069 "mvn", "\t$Rd, $Rn",
1070 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1072 // Bitwise or register
1073 let isCommutable = 1 in
1074 def tORR : // A8.6.114
1075 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1077 "orr", "\t$Rdn, $Rm",
1078 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1081 def tREV : // A8.6.134
1082 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1084 "rev", "\t$Rd, $Rm",
1085 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1086 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1088 def tREV16 : // A8.6.135
1089 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1091 "rev16", "\t$Rd, $Rm",
1092 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1093 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1095 def tREVSH : // A8.6.136
1096 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1098 "revsh", "\t$Rd, $Rm",
1099 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1100 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1102 // Rotate right register
1103 def tROR : // A8.6.139
1104 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1106 "ror", "\t$Rdn, $Rm",
1107 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1110 def tRSB : // A8.6.141
1111 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1113 "rsb", "\t$Rd, $Rn, #0",
1114 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1116 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1117 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1119 // Subtract with carry register
1120 let Uses = [CPSR] in
1121 def tSBC : // A8.6.151
1122 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1124 "sbc", "\t$Rdn, $Rm",
1125 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1127 // Subtract immediate
1128 def tSUBi3 : // A8.6.210 T1
1129 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1131 "sub", "\t$Rd, $Rm, $imm3",
1132 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1134 let Inst{8-6} = imm3;
1137 def tSUBi8 : // A8.6.210 T2
1138 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1140 "sub", "\t$Rdn, $imm8",
1141 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1143 // Subtract register
1144 def tSUBrr : // A8.6.212
1145 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1147 "sub", "\t$Rd, $Rn, $Rm",
1148 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1150 // TODO: A7-96: STMIA - store multiple.
1153 def tSXTB : // A8.6.222
1154 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1156 "sxtb", "\t$Rd, $Rm",
1157 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1158 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1160 // Sign-extend short
1161 def tSXTH : // A8.6.224
1162 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1164 "sxth", "\t$Rd, $Rm",
1165 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1166 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1169 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1170 def tTST : // A8.6.230
1171 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1172 "tst", "\t$Rn, $Rm",
1173 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1176 def tUXTB : // A8.6.262
1177 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1179 "uxtb", "\t$Rd, $Rm",
1180 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1181 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1183 // Zero-extend short
1184 def tUXTH : // A8.6.264
1185 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1187 "uxth", "\t$Rd, $Rm",
1188 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1189 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1191 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1192 // Expanded after instruction selection into a branch sequence.
1193 let usesCustomInserter = 1 in // Expanded after instruction selection.
1194 def tMOVCCr_pseudo :
1195 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1197 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1199 // tLEApcrel - Load a pc-relative address into a register without offending the
1202 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1203 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1204 T1Encoding<{1,0,1,0,0,?}> {
1207 let Inst{10-8} = Rd;
1208 let Inst{7-0} = addr;
1209 let DecoderMethod = "DecodeThumbAddSpecialReg";
1212 let neverHasSideEffects = 1, isReMaterializable = 1 in
1213 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1216 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1217 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1220 //===----------------------------------------------------------------------===//
1224 // __aeabi_read_tp preserves the registers r1-r3.
1225 // This is a pseudo inst so that we can get the encoding right,
1226 // complete with fixup for the aeabi_read_tp function.
1227 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1228 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1229 [(set R0, ARMthread_pointer)]>;
1231 //===----------------------------------------------------------------------===//
1232 // SJLJ Exception handling intrinsics
1235 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1236 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1237 // from some other function to get here, and we're using the stack frame for the
1238 // containing function to save/restore registers, we can't keep anything live in
1239 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1240 // tromped upon when we get here from a longjmp(). We force everything out of
1241 // registers except for our own input by listing the relevant registers in
1242 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1243 // preserve all of the callee-saved resgisters, which is exactly what we want.
1244 // $val is a scratch register for our use.
1245 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1246 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1247 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1248 AddrModeNone, 0, NoItinerary, "","",
1249 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1251 // FIXME: Non-Darwin version(s)
1252 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1253 Defs = [ R7, LR, SP ] in
1254 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1255 AddrModeNone, 0, IndexModeNone,
1256 Pseudo, NoItinerary, "", "",
1257 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1258 Requires<[IsThumb, IsDarwin]>;
1260 //===----------------------------------------------------------------------===//
1261 // Non-Instruction Patterns
1265 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1266 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1267 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1268 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1271 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1272 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1273 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1274 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1275 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1276 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1278 // Subtract with carry
1279 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1280 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1281 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1282 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1283 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1284 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1286 // ConstantPool, GlobalAddress
1287 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1288 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1291 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1292 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1295 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1296 Requires<[IsThumb, IsNotDarwin]>;
1297 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1298 Requires<[IsThumb, IsDarwin]>;
1300 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1301 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1302 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1303 Requires<[IsThumb, HasV5T, IsDarwin]>;
1305 // Indirect calls to ARM routines
1306 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1307 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1308 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1309 Requires<[IsThumb, HasV5T, IsDarwin]>;
1311 // zextload i1 -> zextload i8
1312 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1313 (tLDRBr t_addrmode_rrs1:$addr)>;
1314 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1315 (tLDRBi t_addrmode_is1:$addr)>;
1317 // extload -> zextload
1318 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1319 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1320 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1321 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1322 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1323 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1325 // If it's impossible to use [r,r] address mode for sextload, select to
1326 // ldr{b|h} + sxt{b|h} instead.
1327 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1328 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1329 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1330 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1331 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1332 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1333 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1334 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1335 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1336 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1337 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1338 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1340 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1341 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1342 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1343 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1344 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1345 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1346 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1347 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1349 // Large immediate handling.
1352 def : T1Pat<(i32 thumb_immshifted:$src),
1353 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1354 (thumb_immshifted_shamt imm:$src))>;
1356 def : T1Pat<(i32 imm0_255_comp:$src),
1357 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1359 // Pseudo instruction that combines ldr from constpool and add pc. This should
1360 // be expanded into two instructions late to allow if-conversion and
1362 let isReMaterializable = 1 in
1363 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1365 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1367 Requires<[IsThumb, IsThumb1Only]>;
1369 // Pseudo-instruction for merged POP and return.
1370 // FIXME: remove when we have a way to marking a MI with these properties.
1371 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1372 hasExtraDefRegAllocReq = 1 in
1373 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1375 (tPOP pred:$p, reglist:$regs)>;
1377 // Indirect branch using "mov pc, $Rm"
1378 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1379 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1380 2, IIC_Br, [(brind GPR:$Rm)],
1381 (tMOVr PC, GPR:$Rm, pred:$p)>;
1385 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1386 // encoding is available on ARMv6K, but we don't differentiate that finely.
1387 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;