1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr : Operand<i32>, ImmLeaf<i32, [{
23 return Imm > 0 && Imm <= 32;
25 let EncoderMethod = "getThumbSRImmOpValue";
26 let DecoderMethod = "DecodeThumbSRImm";
29 def imm_neg_XFORM : SDNodeXForm<imm, [{
30 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
32 def imm_comp_XFORM : SDNodeXForm<imm, [{
33 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
36 def imm0_7_neg : PatLeaf<(i32 imm), [{
37 return (uint32_t)-N->getZExtValue() < 8;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : ImmLeaf<i32, [{
45 return Imm >= 8 && Imm < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift. This uses
53 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54 // to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // ADR instruction labels.
70 def t_adrlabel : Operand<i32> {
71 let EncoderMethod = "getThumbAdrLabelOpValue";
74 // Scaled 4 immediate.
75 def t_imm_s4 : Operand<i32> {
76 let PrintMethod = "printThumbS4ImmOperand";
77 let OperandType = "OPERAND_IMMEDIATE";
80 // Define Thumb specific addressing modes.
82 let OperandType = "OPERAND_PCREL" in {
83 def t_brtarget : Operand<OtherVT> {
84 let EncoderMethod = "getThumbBRTargetOpValue";
87 def t_bcctarget : Operand<i32> {
88 let EncoderMethod = "getThumbBCCTargetOpValue";
91 def t_cbtarget : Operand<i32> {
92 let EncoderMethod = "getThumbCBTargetOpValue";
95 def t_bltarget : Operand<i32> {
96 let EncoderMethod = "getThumbBLTargetOpValue";
97 let DecoderMethod = "DecodeThumbBLTargetOperand";
100 def t_blxtarget : Operand<i32> {
101 let EncoderMethod = "getThumbBLXTargetOpValue";
102 let DecoderMethod = "DecodeThumbBLXOffset";
106 // t_addrmode_rr := reg + reg
108 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
109 def t_addrmode_rr : Operand<i32>,
110 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
111 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
112 let PrintMethod = "printThumbAddrModeRROperand";
113 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
116 // t_addrmode_rrs := reg + reg
118 def t_addrmode_rrs1 : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let ParserMatchClass = t_addrmode_rr_asm_operand;
123 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
125 def t_addrmode_rrs2 : Operand<i32>,
126 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
127 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
128 let PrintMethod = "printThumbAddrModeRROperand";
129 let ParserMatchClass = t_addrmode_rr_asm_operand;
130 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
132 def t_addrmode_rrs4 : Operand<i32>,
133 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
134 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
135 let PrintMethod = "printThumbAddrModeRROperand";
136 let ParserMatchClass = t_addrmode_rr_asm_operand;
137 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
140 // t_addrmode_is4 := reg + imm5 * 4
142 def t_addrmode_is4 : Operand<i32>,
143 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
144 let EncoderMethod = "getAddrModeISOpValue";
145 let PrintMethod = "printThumbAddrModeImm5S4Operand";
146 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
149 // t_addrmode_is2 := reg + imm5 * 2
151 def t_addrmode_is2 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
153 let EncoderMethod = "getAddrModeISOpValue";
154 let PrintMethod = "printThumbAddrModeImm5S2Operand";
155 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
158 // t_addrmode_is1 := reg + imm5
160 def t_addrmode_is1 : Operand<i32>,
161 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
162 let EncoderMethod = "getAddrModeISOpValue";
163 let PrintMethod = "printThumbAddrModeImm5S1Operand";
164 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
167 // t_addrmode_sp := sp + imm8 * 4
169 def t_addrmode_sp : Operand<i32>,
170 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
171 let EncoderMethod = "getAddrModeThumbSPOpValue";
172 let DecoderMethod = "DecodeThumbAddrModeSP";
173 let PrintMethod = "printThumbAddrModeSPOperand";
174 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
177 // t_addrmode_pc := <label> => pc + imm8 * 4
179 def t_addrmode_pc : Operand<i32> {
180 let EncoderMethod = "getAddrModePCOpValue";
183 //===----------------------------------------------------------------------===//
184 // Miscellaneous Instructions.
187 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
188 // from removing one half of the matched pairs. That breaks PEI, which assumes
189 // these will always be in pairs, and asserts if it finds otherwise. Better way?
190 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
191 def tADJCALLSTACKUP :
192 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
193 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
194 Requires<[IsThumb, IsThumb1Only]>;
196 def tADJCALLSTACKDOWN :
197 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
198 [(ARMcallseq_start imm:$amt)]>,
199 Requires<[IsThumb, IsThumb1Only]>;
202 // T1Disassembly - A simple class to make encoding some disassembly patterns
203 // easier and less verbose.
204 class T1Disassembly<bits<2> op1, bits<8> op2>
205 : T1Encoding<0b101111> {
210 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
211 [/* For disassembly only; pattern left blank */]>,
212 T1Disassembly<0b11, 0x00>; // A8.6.110
214 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
215 [/* For disassembly only; pattern left blank */]>,
216 T1Disassembly<0b11, 0x10>; // A8.6.410
218 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
219 [/* For disassembly only; pattern left blank */]>,
220 T1Disassembly<0b11, 0x20>; // A8.6.408
222 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
223 [/* For disassembly only; pattern left blank */]>,
224 T1Disassembly<0b11, 0x30>; // A8.6.409
226 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
227 [/* For disassembly only; pattern left blank */]>,
228 T1Disassembly<0b11, 0x40>; // A8.6.157
230 // The i32imm operand $val can be used by a debugger to store more information
231 // about the breakpoint.
232 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
233 [/* For disassembly only; pattern left blank */]>,
234 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
240 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
241 []>, T1Encoding<0b101101> {
244 let Inst{9-5} = 0b10010;
247 let Inst{2-0} = 0b000;
250 // Change Processor State is a system instruction -- for disassembly only.
251 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
252 NoItinerary, "cps$imod $iflags",
253 [/* For disassembly only; pattern left blank */]>,
261 let Inst{2-0} = iflags;
264 // For both thumb1 and thumb2.
265 let isNotDuplicable = 1, isCodeGenOnly = 1 in
266 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
267 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
268 T1Special<{0,0,?,?}> {
271 let Inst{6-3} = 0b1111; // Rm = pc
275 // PC relative add (ADR).
276 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
277 "add\t$dst, pc, $rhs", []>,
278 T1Encoding<{1,0,1,0,0,?}> {
282 let Inst{10-8} = dst;
286 // ADD <Rd>, sp, #<imm8>
287 // This is rematerializable, which is particularly useful for taking the
288 // address of locals.
289 let isReMaterializable = 1 in
290 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
291 "add\t$dst, $sp, $rhs", []>,
292 T1Encoding<{1,0,1,0,1,?}> {
296 let Inst{10-8} = dst;
300 // ADD sp, sp, #<imm7>
301 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
302 "add\t$dst, $rhs", []>,
303 T1Misc<{0,0,0,0,0,?,?}> {
309 // SUB sp, sp, #<imm7>
310 // FIXME: The encoding and the ASM string don't match up.
311 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
312 "sub\t$dst, $rhs", []>,
313 T1Misc<{0,0,0,0,1,?,?}> {
320 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
321 "add\t$dst, $rhs", []>,
322 T1Special<{0,0,?,?}> {
323 // A8.6.9 Encoding T1
325 let Inst{7} = dst{3};
326 let Inst{6-3} = 0b1101;
327 let Inst{2-0} = dst{2-0};
331 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
332 "add\t$dst, $rhs", []>,
333 T1Special<{0,0,?,?}> {
334 // A8.6.9 Encoding T2
338 let Inst{2-0} = 0b101;
341 //===----------------------------------------------------------------------===//
342 // Control Flow Instructions.
346 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
347 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
348 T1Special<{1,1,0,?}> {
352 let Inst{2-0} = 0b000;
356 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
357 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
358 [(ARMretflag)], (tBX LR, pred:$p)>;
360 // Alternative return instruction used by vararg functions.
361 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
363 (tBX GPR:$Rm, pred:$p)>;
366 // All calls clobber the non-callee saved registers. SP is marked as a use to
367 // prevent stack-pointer assignments that appear immediately before calls from
368 // potentially appearing dead.
370 // On non-Darwin platforms R9 is callee-saved.
371 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
373 // Also used for Thumb2
374 def tBL : TIx2<0b11110, 0b11, 1,
375 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
377 [(ARMtcall tglobaladdr:$func)]>,
378 Requires<[IsThumb, IsNotDarwin]> {
380 let Inst{26} = func{21};
381 let Inst{25-16} = func{20-11};
384 let Inst{10-0} = func{10-0};
387 // ARMv5T and above, also used for Thumb2
388 def tBLXi : TIx2<0b11110, 0b11, 0,
389 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
391 [(ARMcall tglobaladdr:$func)]>,
392 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
394 let Inst{25-16} = func{20-11};
397 let Inst{10-1} = func{10-1};
398 let Inst{0} = 0; // func{0} is assumed zero
401 // Also used for Thumb2
402 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
404 [(ARMtcall GPR:$func)]>,
405 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
406 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
408 let Inst{6-3} = func;
409 let Inst{2-0} = 0b000;
413 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
415 [(ARMcall_nolink tGPR:$func)]>,
416 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
420 // On Darwin R9 is call-clobbered.
421 // R7 is marked as a use to prevent frame-pointer assignments from being
422 // moved above / below calls.
423 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
425 // Also used for Thumb2
426 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
427 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
428 (tBL pred:$p, t_bltarget:$func)>,
429 Requires<[IsThumb, IsDarwin]>;
431 // ARMv5T and above, also used for Thumb2
432 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
433 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
434 (tBLXi pred:$p, t_blxtarget:$func)>,
435 Requires<[IsThumb, HasV5T, IsDarwin]>;
437 // Also used for Thumb2
438 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
439 2, IIC_Br, [(ARMtcall GPR:$func)],
440 (tBLXr pred:$p, GPR:$func)>,
441 Requires<[IsThumb, HasV5T, IsDarwin]>;
444 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
446 [(ARMcall_nolink tGPR:$func)]>,
447 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
450 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
451 let isPredicable = 1 in
452 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
453 "b\t$target", [(br bb:$target)]>,
454 T1Encoding<{1,1,1,0,0,?}> {
456 let Inst{10-0} = target;
460 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
461 // the clobber of LR.
463 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
464 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
466 def tBR_JTr : tPseudoInst<(outs),
467 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
469 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
470 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
474 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
475 // a two-value operand where a dag node expects two operands. :(
476 let isBranch = 1, isTerminator = 1 in
477 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
479 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
480 T1BranchCond<{1,1,0,1}> {
484 let Inst{7-0} = target;
487 // Compare and branch on zero / non-zero
488 let isBranch = 1, isTerminator = 1 in {
489 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
490 "cbz\t$Rn, $target", []>,
491 T1Misc<{0,0,?,1,?,?,?}> {
495 let Inst{9} = target{5};
496 let Inst{7-3} = target{4-0};
500 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
501 "cbnz\t$Rn, $target", []>,
502 T1Misc<{1,0,?,1,?,?,?}> {
506 let Inst{9} = target{5};
507 let Inst{7-3} = target{4-0};
513 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
515 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
517 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
518 // on Darwin), so it's in ARMInstrThumb2.td.
519 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
521 (tBX GPR:$dst, (ops 14, zero_reg))>,
522 Requires<[IsThumb, IsDarwin]>;
524 // Non-Darwin versions (the difference is R9).
525 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
527 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
529 (tB t_brtarget:$dst)>,
530 Requires<[IsThumb, IsNotDarwin]>;
531 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
533 (tBX GPR:$dst, (ops 14, zero_reg))>,
534 Requires<[IsThumb, IsNotDarwin]>;
539 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
540 // A8.6.16 B: Encoding T1
541 // If Inst{11-8} == 0b1111 then SEE SVC
542 let isCall = 1, Uses = [SP] in
543 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
544 "svc", "\t$imm", []>, Encoding16 {
546 let Inst{15-12} = 0b1101;
547 let Inst{11-8} = 0b1111;
551 // The assembler uses 0xDEFE for a trap instruction.
552 let isBarrier = 1, isTerminator = 1 in
553 def tTRAP : TI<(outs), (ins), IIC_Br,
554 "trap", [(trap)]>, Encoding16 {
558 //===----------------------------------------------------------------------===//
559 // Load Store Instructions.
562 // Loads: reg/reg and reg/imm5
563 let canFoldAsLoad = 1, isReMaterializable = 1 in
564 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
565 Operand AddrMode_r, Operand AddrMode_i,
566 AddrMode am, InstrItinClass itin_r,
567 InstrItinClass itin_i, string asm,
570 T1pILdStEncode<reg_opc,
571 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
572 am, itin_r, asm, "\t$Rt, $addr",
573 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
575 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
576 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
577 am, itin_i, asm, "\t$Rt, $addr",
578 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
580 // Stores: reg/reg and reg/imm5
581 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
582 Operand AddrMode_r, Operand AddrMode_i,
583 AddrMode am, InstrItinClass itin_r,
584 InstrItinClass itin_i, string asm,
587 T1pILdStEncode<reg_opc,
588 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
589 am, itin_r, asm, "\t$Rt, $addr",
590 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
592 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
593 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
594 am, itin_i, asm, "\t$Rt, $addr",
595 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
599 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
600 t_addrmode_is4, AddrModeT1_4,
601 IIC_iLoad_r, IIC_iLoad_i, "ldr",
602 UnOpFrag<(load node:$Src)>>;
605 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
606 t_addrmode_is1, AddrModeT1_1,
607 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
608 UnOpFrag<(zextloadi8 node:$Src)>>;
611 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
612 t_addrmode_is2, AddrModeT1_2,
613 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
614 UnOpFrag<(zextloadi16 node:$Src)>>;
616 let AddedComplexity = 10 in
617 def tLDRSB : // A8.6.80
618 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
619 AddrModeT1_1, IIC_iLoad_bh_r,
620 "ldrsb", "\t$dst, $addr",
621 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
623 let AddedComplexity = 10 in
624 def tLDRSH : // A8.6.84
625 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
626 AddrModeT1_2, IIC_iLoad_bh_r,
627 "ldrsh", "\t$dst, $addr",
628 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
630 let canFoldAsLoad = 1 in
631 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
632 "ldr", "\t$Rt, $addr",
633 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
638 let Inst{7-0} = addr;
642 // FIXME: Use ldr.n to work around a Darwin assembler bug.
643 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
644 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
645 "ldr", ".n\t$Rt, $addr",
646 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
647 T1Encoding<{0,1,0,0,1,?}> {
652 let Inst{7-0} = addr;
655 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
656 // For disassembly use only.
657 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
658 "ldr", "\t$Rt, $addr",
659 [/* disassembly only */]>,
660 T1Encoding<{0,1,0,0,1,?}> {
665 let Inst{7-0} = addr;
668 // A8.6.194 & A8.6.192
669 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
670 t_addrmode_is4, AddrModeT1_4,
671 IIC_iStore_r, IIC_iStore_i, "str",
672 BinOpFrag<(store node:$LHS, node:$RHS)>>;
674 // A8.6.197 & A8.6.195
675 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
676 t_addrmode_is1, AddrModeT1_1,
677 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
678 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
680 // A8.6.207 & A8.6.205
681 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
682 t_addrmode_is2, AddrModeT1_2,
683 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
684 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
687 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
688 "str", "\t$Rt, $addr",
689 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
694 let Inst{7-0} = addr;
697 //===----------------------------------------------------------------------===//
698 // Load / store multiple Instructions.
701 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
702 InstrItinClass itin_upd, bits<6> T1Enc,
703 bit L_bit, string baseOpc> {
705 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
706 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
711 let Inst{7-0} = regs;
715 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
716 "$Rn = $wb", itin_upd>,
717 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
718 GPR:$Rn, pred:$p, reglist:$regs)> {
720 let OutOperandList = (outs GPR:$wb);
721 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
723 let isCodeGenOnly = 1;
725 list<Predicate> Predicates = [IsThumb];
729 // These require base address to be written back or one of the loaded regs.
730 let neverHasSideEffects = 1 in {
732 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
733 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
734 {1,1,0,0,1,?}, 1, "tLDM">;
736 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
737 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
738 {1,1,0,0,0,?}, 0, "tSTM">;
740 } // neverHasSideEffects
742 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
743 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
745 "pop${p}\t$regs", []>,
746 T1Misc<{1,1,0,?,?,?,?}> {
748 let Inst{8} = regs{15};
749 let Inst{7-0} = regs{7-0};
752 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
753 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
755 "push${p}\t$regs", []>,
756 T1Misc<{0,1,0,?,?,?,?}> {
758 let Inst{8} = regs{14};
759 let Inst{7-0} = regs{7-0};
762 //===----------------------------------------------------------------------===//
763 // Arithmetic Instructions.
766 // Helper classes for encoding T1pI patterns:
767 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
768 string opc, string asm, list<dag> pattern>
769 : T1pI<oops, iops, itin, opc, asm, pattern>,
770 T1DataProcessing<opA> {
776 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
777 string opc, string asm, list<dag> pattern>
778 : T1pI<oops, iops, itin, opc, asm, pattern>,
786 // Helper classes for encoding T1sI patterns:
787 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
788 string opc, string asm, list<dag> pattern>
789 : T1sI<oops, iops, itin, opc, asm, pattern>,
790 T1DataProcessing<opA> {
796 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
797 string opc, string asm, list<dag> pattern>
798 : T1sI<oops, iops, itin, opc, asm, pattern>,
807 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
808 string opc, string asm, list<dag> pattern>
809 : T1sI<oops, iops, itin, opc, asm, pattern>,
817 // Helper classes for encoding T1sIt patterns:
818 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
819 string opc, string asm, list<dag> pattern>
820 : T1sIt<oops, iops, itin, opc, asm, pattern>,
821 T1DataProcessing<opA> {
827 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
828 string opc, string asm, list<dag> pattern>
829 : T1sIt<oops, iops, itin, opc, asm, pattern>,
833 let Inst{10-8} = Rdn;
834 let Inst{7-0} = imm8;
837 // Add with carry register
838 let isCommutable = 1, Uses = [CPSR] in
840 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
841 "adc", "\t$Rdn, $Rm",
842 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
845 def tADDi3 : // A8.6.4 T1
846 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
848 "add", "\t$Rd, $Rm, $imm3",
849 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
851 let Inst{8-6} = imm3;
854 def tADDi8 : // A8.6.4 T2
855 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
857 "add", "\t$Rdn, $imm8",
858 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
861 let isCommutable = 1 in
862 def tADDrr : // A8.6.6 T1
863 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
865 "add", "\t$Rd, $Rn, $Rm",
866 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
868 let neverHasSideEffects = 1 in
869 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
870 "add", "\t$Rdn, $Rm", []>,
871 T1Special<{0,0,?,?}> {
875 let Inst{7} = Rdn{3};
877 let Inst{2-0} = Rdn{2-0};
881 let isCommutable = 1 in
882 def tAND : // A8.6.12
883 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
885 "and", "\t$Rdn, $Rm",
886 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
889 def tASRri : // A8.6.14
890 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
892 "asr", "\t$Rd, $Rm, $imm5",
893 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
895 let Inst{10-6} = imm5;
899 def tASRrr : // A8.6.15
900 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
902 "asr", "\t$Rdn, $Rm",
903 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
906 def tBIC : // A8.6.20
907 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
909 "bic", "\t$Rdn, $Rm",
910 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
913 let isCompare = 1, Defs = [CPSR] in {
914 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
915 // Compare-to-zero still works out, just not the relationals
916 //def tCMN : // A8.6.33
917 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
919 // "cmn", "\t$lhs, $rhs",
920 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
922 def tCMNz : // A8.6.33
923 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
926 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
928 } // isCompare = 1, Defs = [CPSR]
931 let isCompare = 1, Defs = [CPSR] in {
932 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
933 "cmp", "\t$Rn, $imm8",
934 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
935 T1General<{1,0,1,?,?}> {
940 let Inst{7-0} = imm8;
944 def tCMPr : // A8.6.36 T1
945 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
948 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
950 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
951 "cmp", "\t$Rn, $Rm", []>,
952 T1Special<{0,1,?,?}> {
958 let Inst{2-0} = Rn{2-0};
960 } // isCompare = 1, Defs = [CPSR]
964 let isCommutable = 1 in
965 def tEOR : // A8.6.45
966 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
968 "eor", "\t$Rdn, $Rm",
969 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
972 def tLSLri : // A8.6.88
973 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
975 "lsl", "\t$Rd, $Rm, $imm5",
976 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
978 let Inst{10-6} = imm5;
982 def tLSLrr : // A8.6.89
983 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
985 "lsl", "\t$Rdn, $Rm",
986 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
989 def tLSRri : // A8.6.90
990 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
992 "lsr", "\t$Rd, $Rm, $imm5",
993 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
995 let Inst{10-6} = imm5;
999 def tLSRrr : // A8.6.91
1000 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1002 "lsr", "\t$Rdn, $Rm",
1003 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1006 let isMoveImm = 1 in
1007 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1008 "mov", "\t$Rd, $imm8",
1009 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1010 T1General<{1,0,0,?,?}> {
1014 let Inst{10-8} = Rd;
1015 let Inst{7-0} = imm8;
1018 // A7-73: MOV(2) - mov setting flag.
1020 let neverHasSideEffects = 1 in {
1021 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1023 "mov", "\t$Rd, $Rm", "", []>,
1024 T1Special<{1,0,?,?}> {
1028 let Inst{7} = Rd{3};
1030 let Inst{2-0} = Rd{2-0};
1032 let Defs = [CPSR] in
1033 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1034 "movs\t$Rd, $Rm", []>, Encoding16 {
1038 let Inst{15-6} = 0b0000000000;
1042 } // neverHasSideEffects
1044 // Multiply register
1045 let isCommutable = 1 in
1046 def tMUL : // A8.6.105 T1
1047 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1049 "mul", "\t$Rdn, $Rm, $Rdn",
1050 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1052 // Move inverse register
1053 def tMVN : // A8.6.107
1054 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1055 "mvn", "\t$Rd, $Rn",
1056 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1058 // Bitwise or register
1059 let isCommutable = 1 in
1060 def tORR : // A8.6.114
1061 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1063 "orr", "\t$Rdn, $Rm",
1064 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1067 def tREV : // A8.6.134
1068 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1070 "rev", "\t$Rd, $Rm",
1071 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1072 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1074 def tREV16 : // A8.6.135
1075 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1077 "rev16", "\t$Rd, $Rm",
1078 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1079 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1081 def tREVSH : // A8.6.136
1082 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1084 "revsh", "\t$Rd, $Rm",
1085 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1086 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1088 // Rotate right register
1089 def tROR : // A8.6.139
1090 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1092 "ror", "\t$Rdn, $Rm",
1093 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1096 def tRSB : // A8.6.141
1097 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1099 "rsb", "\t$Rd, $Rn, #0",
1100 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1102 // Subtract with carry register
1103 let Uses = [CPSR] in
1104 def tSBC : // A8.6.151
1105 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1107 "sbc", "\t$Rdn, $Rm",
1108 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1110 // Subtract immediate
1111 def tSUBi3 : // A8.6.210 T1
1112 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1114 "sub", "\t$Rd, $Rm, $imm3",
1115 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1117 let Inst{8-6} = imm3;
1120 def tSUBi8 : // A8.6.210 T2
1121 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1123 "sub", "\t$Rdn, $imm8",
1124 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1126 // Subtract register
1127 def tSUBrr : // A8.6.212
1128 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1130 "sub", "\t$Rd, $Rn, $Rm",
1131 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1133 // TODO: A7-96: STMIA - store multiple.
1136 def tSXTB : // A8.6.222
1137 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1139 "sxtb", "\t$Rd, $Rm",
1140 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1141 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1143 // Sign-extend short
1144 def tSXTH : // A8.6.224
1145 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1147 "sxth", "\t$Rd, $Rm",
1148 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1149 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1152 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1153 def tTST : // A8.6.230
1154 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1155 "tst", "\t$Rn, $Rm",
1156 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1159 def tUXTB : // A8.6.262
1160 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1162 "uxtb", "\t$Rd, $Rm",
1163 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1164 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1166 // Zero-extend short
1167 def tUXTH : // A8.6.264
1168 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1170 "uxth", "\t$Rd, $Rm",
1171 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1172 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1174 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1175 // Expanded after instruction selection into a branch sequence.
1176 let usesCustomInserter = 1 in // Expanded after instruction selection.
1177 def tMOVCCr_pseudo :
1178 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1180 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1182 // tLEApcrel - Load a pc-relative address into a register without offending the
1185 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1186 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1187 T1Encoding<{1,0,1,0,0,?}> {
1190 let Inst{10-8} = Rd;
1191 let Inst{7-0} = addr;
1194 let neverHasSideEffects = 1, isReMaterializable = 1 in
1195 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1198 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1199 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1202 //===----------------------------------------------------------------------===//
1206 // __aeabi_read_tp preserves the registers r1-r3.
1207 // This is a pseudo inst so that we can get the encoding right,
1208 // complete with fixup for the aeabi_read_tp function.
1209 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1210 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1211 [(set R0, ARMthread_pointer)]>;
1213 //===----------------------------------------------------------------------===//
1214 // SJLJ Exception handling intrinsics
1217 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1218 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1219 // from some other function to get here, and we're using the stack frame for the
1220 // containing function to save/restore registers, we can't keep anything live in
1221 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1222 // tromped upon when we get here from a longjmp(). We force everything out of
1223 // registers except for our own input by listing the relevant registers in
1224 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1225 // preserve all of the callee-saved resgisters, which is exactly what we want.
1226 // $val is a scratch register for our use.
1227 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1228 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1229 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1230 AddrModeNone, 0, NoItinerary, "","",
1231 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1233 // FIXME: Non-Darwin version(s)
1234 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1235 Defs = [ R7, LR, SP ] in
1236 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1237 AddrModeNone, 0, IndexModeNone,
1238 Pseudo, NoItinerary, "", "",
1239 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1240 Requires<[IsThumb, IsDarwin]>;
1242 //===----------------------------------------------------------------------===//
1243 // Non-Instruction Patterns
1247 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1248 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1249 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1250 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1253 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1254 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1255 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1256 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1257 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1258 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1260 // Subtract with carry
1261 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1262 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1263 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1264 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1265 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1266 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1268 // ConstantPool, GlobalAddress
1269 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1270 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1273 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1274 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1277 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1278 Requires<[IsThumb, IsNotDarwin]>;
1279 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1280 Requires<[IsThumb, IsDarwin]>;
1282 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1283 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1284 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1285 Requires<[IsThumb, HasV5T, IsDarwin]>;
1287 // Indirect calls to ARM routines
1288 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1289 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1290 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1291 Requires<[IsThumb, HasV5T, IsDarwin]>;
1293 // zextload i1 -> zextload i8
1294 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1295 (tLDRBr t_addrmode_rrs1:$addr)>;
1296 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1297 (tLDRBi t_addrmode_is1:$addr)>;
1299 // extload -> zextload
1300 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1301 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1302 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1303 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1304 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1305 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1307 // If it's impossible to use [r,r] address mode for sextload, select to
1308 // ldr{b|h} + sxt{b|h} instead.
1309 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1310 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1311 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1312 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1313 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1314 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1315 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1316 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1317 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1318 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1319 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1320 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1322 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1323 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1324 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1325 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1326 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1327 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1328 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1329 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1331 // Large immediate handling.
1334 def : T1Pat<(i32 thumb_immshifted:$src),
1335 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1336 (thumb_immshifted_shamt imm:$src))>;
1338 def : T1Pat<(i32 imm0_255_comp:$src),
1339 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1341 // Pseudo instruction that combines ldr from constpool and add pc. This should
1342 // be expanded into two instructions late to allow if-conversion and
1344 let isReMaterializable = 1 in
1345 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1347 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1349 Requires<[IsThumb, IsThumb1Only]>;
1351 // Pseudo-instruction for merged POP and return.
1352 // FIXME: remove when we have a way to marking a MI with these properties.
1353 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1354 hasExtraDefRegAllocReq = 1 in
1355 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1357 (tPOP pred:$p, reglist:$regs)>;
1359 // Indirect branch using "mov pc, $Rm"
1360 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1361 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1362 2, IIC_Br, [(brind GPR:$Rm)],
1363 (tMOVr PC, GPR:$Rm, pred:$p)>;