1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_comp_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
39 def imm0_7_neg : PatLeaf<(i32 imm), [{
40 return (uint32_t)-N->getZExtValue() < 8;
43 def imm0_255_comp : PatLeaf<(i32 imm), [{
44 return ~((uint32_t)N->getZExtValue()) < 256;
47 def imm8_255 : ImmLeaf<i32, [{
48 return Imm >= 8 && Imm < 256;
50 def imm8_255_neg : PatLeaf<(i32 imm), [{
51 unsigned Val = -N->getZExtValue();
52 return Val >= 8 && Val < 256;
55 // Break imm's up into two pieces: an immediate + a left shift. This uses
56 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
57 // to get the val/shift pieces.
58 def thumb_immshifted : PatLeaf<(imm), [{
59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
62 def thumb_immshifted_val : SDNodeXForm<imm, [{
63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
64 return CurDAG->getTargetConstant(V, MVT::i32);
67 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
69 return CurDAG->getTargetConstant(V, MVT::i32);
72 // Scaled 4 immediate.
73 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
74 def t_imm0_1020s4 : Operand<i32> {
75 let PrintMethod = "printThumbS4ImmOperand";
76 let ParserMatchClass = t_imm0_1020s4_asmoperand;
77 let OperandType = "OPERAND_IMMEDIATE";
80 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
81 def t_imm0_508s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let ParserMatchClass = t_imm0_508s4_asmoperand;
84 let OperandType = "OPERAND_IMMEDIATE";
86 // Alias use only, so no printer is necessary.
87 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
88 def t_imm0_508s4_neg : Operand<i32> {
89 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
90 let OperandType = "OPERAND_IMMEDIATE";
93 // Define Thumb specific addressing modes.
95 // unsigned 8-bit, 2-scaled memory offset
96 class OperandUnsignedOffset_b8s2 : AsmOperandClass {
97 let Name = "UnsignedOffset_b8s2";
98 let PredicateMethod = "isUnsignedOffset<8, 2>";
101 def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2;
103 // thumb style PC relative operand. signed, 8 bits magnitude,
104 // two bits shift. can be represented as either [pc, #imm], #imm,
105 // or relocatable expression...
106 def ThumbMemPC : AsmOperandClass {
107 let Name = "ThumbMemPC";
110 let OperandType = "OPERAND_PCREL" in {
111 def t_brtarget : Operand<OtherVT> {
112 let EncoderMethod = "getThumbBRTargetOpValue";
113 let DecoderMethod = "DecodeThumbBROperand";
116 // ADR instruction labels.
117 def t_adrlabel : Operand<i32> {
118 let EncoderMethod = "getThumbAdrLabelOpValue";
119 let PrintMethod = "printAdrLabelOperand<2>";
120 let ParserMatchClass = UnsignedOffset_b8s2;
123 def t_bcctarget : Operand<i32> {
124 let EncoderMethod = "getThumbBCCTargetOpValue";
125 let DecoderMethod = "DecodeThumbBCCTargetOperand";
128 def t_cbtarget : Operand<i32> {
129 let EncoderMethod = "getThumbCBTargetOpValue";
130 let DecoderMethod = "DecodeThumbCmpBROperand";
133 def t_bltarget : Operand<i32> {
134 let EncoderMethod = "getThumbBLTargetOpValue";
135 let DecoderMethod = "DecodeThumbBLTargetOperand";
138 def t_blxtarget : Operand<i32> {
139 let EncoderMethod = "getThumbBLXTargetOpValue";
140 let DecoderMethod = "DecodeThumbBLXOffset";
143 // t_addrmode_pc := <label> => pc + imm8 * 4
145 def t_addrmode_pc : Operand<i32> {
146 let EncoderMethod = "getAddrModePCOpValue";
147 let DecoderMethod = "DecodeThumbAddrModePC";
148 let PrintMethod = "printThumbLdrLabelOperand";
149 let ParserMatchClass = ThumbMemPC;
153 // t_addrmode_rr := reg + reg
155 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
156 def t_addrmode_rr : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
158 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
159 let PrintMethod = "printThumbAddrModeRROperand";
160 let DecoderMethod = "DecodeThumbAddrModeRR";
161 let ParserMatchClass = t_addrmode_rr_asm_operand;
162 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
165 // t_addrmode_rrs := reg + reg
167 // We use separate scaled versions because the Select* functions need
168 // to explicitly check for a matching constant and return false here so that
169 // the reg+imm forms will match instead. This is a horrible way to do that,
170 // as it forces tight coupling between the methods, but it's how selectiondag
172 def t_addrmode_rrs1 : Operand<i32>,
173 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
174 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
175 let PrintMethod = "printThumbAddrModeRROperand";
176 let DecoderMethod = "DecodeThumbAddrModeRR";
177 let ParserMatchClass = t_addrmode_rr_asm_operand;
178 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
180 def t_addrmode_rrs2 : Operand<i32>,
181 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
182 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
183 let DecoderMethod = "DecodeThumbAddrModeRR";
184 let PrintMethod = "printThumbAddrModeRROperand";
185 let ParserMatchClass = t_addrmode_rr_asm_operand;
186 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
188 def t_addrmode_rrs4 : Operand<i32>,
189 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
190 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
191 let DecoderMethod = "DecodeThumbAddrModeRR";
192 let PrintMethod = "printThumbAddrModeRROperand";
193 let ParserMatchClass = t_addrmode_rr_asm_operand;
194 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
197 // t_addrmode_is4 := reg + imm5 * 4
199 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
200 def t_addrmode_is4 : Operand<i32>,
201 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
202 let EncoderMethod = "getAddrModeISOpValue";
203 let DecoderMethod = "DecodeThumbAddrModeIS";
204 let PrintMethod = "printThumbAddrModeImm5S4Operand";
205 let ParserMatchClass = t_addrmode_is4_asm_operand;
206 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
209 // t_addrmode_is2 := reg + imm5 * 2
211 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
212 def t_addrmode_is2 : Operand<i32>,
213 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
214 let EncoderMethod = "getAddrModeISOpValue";
215 let DecoderMethod = "DecodeThumbAddrModeIS";
216 let PrintMethod = "printThumbAddrModeImm5S2Operand";
217 let ParserMatchClass = t_addrmode_is2_asm_operand;
218 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
221 // t_addrmode_is1 := reg + imm5
223 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
224 def t_addrmode_is1 : Operand<i32>,
225 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
226 let EncoderMethod = "getAddrModeISOpValue";
227 let DecoderMethod = "DecodeThumbAddrModeIS";
228 let PrintMethod = "printThumbAddrModeImm5S1Operand";
229 let ParserMatchClass = t_addrmode_is1_asm_operand;
230 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
233 // t_addrmode_sp := sp + imm8 * 4
235 // FIXME: This really shouldn't have an explicit SP operand at all. It should
236 // be implicit, just like in the instruction encoding itself.
237 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
238 def t_addrmode_sp : Operand<i32>,
239 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
240 let EncoderMethod = "getAddrModeThumbSPOpValue";
241 let DecoderMethod = "DecodeThumbAddrModeSP";
242 let PrintMethod = "printThumbAddrModeSPOperand";
243 let ParserMatchClass = t_addrmode_sp_asm_operand;
244 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
247 //===----------------------------------------------------------------------===//
248 // Miscellaneous Instructions.
251 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
252 // from removing one half of the matched pairs. That breaks PEI, which assumes
253 // these will always be in pairs, and asserts if it finds otherwise. Better way?
254 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
255 def tADJCALLSTACKUP :
256 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
257 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
258 Requires<[IsThumb, IsThumb1Only]>;
260 def tADJCALLSTACKDOWN :
261 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
262 [(ARMcallseq_start imm:$amt)]>,
263 Requires<[IsThumb, IsThumb1Only]>;
266 class T1SystemEncoding<bits<8> opc>
267 : T1Encoding<0b101111> {
268 let Inst{9-8} = 0b11;
272 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
273 T1SystemEncoding<0x00>, // A8.6.110
274 Requires<[IsThumb2]>;
276 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
277 T1SystemEncoding<0x10>, // A8.6.410
278 Requires<[IsThumb2]>;
280 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
281 T1SystemEncoding<0x20>, // A8.6.408
282 Requires<[IsThumb2]>;
284 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
285 T1SystemEncoding<0x30>, // A8.6.409
286 Requires<[IsThumb2]>;
288 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
289 T1SystemEncoding<0x40>, // A8.6.157
290 Requires<[IsThumb2]>;
292 def tSEVL : T1pI<(outs), (ins), NoItinerary, "sevl", "", [(int_arm_sevl)]>,
293 T1SystemEncoding<0x50>,
294 Requires<[IsThumb2, HasV8]>;
297 // The imm operand $val can be used by a debugger to store more information
298 // about the breakpoint.
299 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
301 T1Encoding<0b101111> {
302 let Inst{9-8} = 0b10;
308 def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val",
309 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> {
310 let Inst{9-6} = 0b1010;
315 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
316 []>, T1Encoding<0b101101>, Deprecated<HasV8Ops> {
319 let Inst{9-5} = 0b10010;
322 let Inst{2-0} = 0b000;
325 // Change Processor State is a system instruction -- for disassembly only.
326 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
327 NoItinerary, "cps$imod $iflags", []>,
335 let Inst{2-0} = iflags;
336 let DecoderMethod = "DecodeThumbCPS";
339 // For both thumb1 and thumb2.
340 let isNotDuplicable = 1, isCodeGenOnly = 1 in
341 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
342 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
343 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
346 let Inst{6-3} = 0b1111; // Rm = pc
350 // ADD <Rd>, sp, #<imm8>
351 // FIXME: This should not be marked as having side effects, and it should be
352 // rematerializable. Clearing the side effect bit causes miscompilations,
353 // probably because the instruction can be moved around.
354 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
355 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
356 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> {
360 let Inst{10-8} = dst;
362 let DecoderMethod = "DecodeThumbAddSpecialReg";
365 // ADD sp, sp, #<imm7>
366 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
367 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
368 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> {
372 let DecoderMethod = "DecodeThumbAddSPImm";
375 // SUB sp, sp, #<imm7>
376 // FIXME: The encoding and the ASM string don't match up.
377 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
378 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
379 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> {
383 let DecoderMethod = "DecodeThumbAddSPImm";
386 def : tInstAlias<"add${p} sp, $imm",
387 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
388 def : tInstAlias<"add${p} sp, sp, $imm",
389 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
391 // Can optionally specify SP as a three operand instruction.
392 def : tInstAlias<"add${p} sp, sp, $imm",
393 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
394 def : tInstAlias<"sub${p} sp, sp, $imm",
395 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
398 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
399 "add", "\t$Rdn, $sp, $Rn", []>,
400 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
401 // A8.6.9 Encoding T1
403 let Inst{7} = Rdn{3};
404 let Inst{6-3} = 0b1101;
405 let Inst{2-0} = Rdn{2-0};
406 let DecoderMethod = "DecodeThumbAddSPReg";
410 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
411 "add", "\t$Rdn, $Rm", []>,
412 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
413 // A8.6.9 Encoding T2
417 let Inst{2-0} = 0b101;
418 let DecoderMethod = "DecodeThumbAddSPReg";
421 //===----------------------------------------------------------------------===//
422 // Control Flow Instructions.
426 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
427 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
428 T1Special<{1,1,0,?}>, Sched<[WriteBr]> {
432 let Inst{2-0} = 0b000;
433 let Unpredictable{2-0} = 0b111;
437 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
438 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
439 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>;
441 // Alternative return instruction used by vararg functions.
442 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
444 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
447 // All calls clobber the non-callee saved registers. SP is marked as a use to
448 // prevent stack-pointer assignments that appear immediately before calls from
449 // potentially appearing dead.
451 Defs = [LR], Uses = [SP] in {
452 // Also used for Thumb2
453 def tBL : TIx2<0b11110, 0b11, 1,
454 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br,
456 [(ARMtcall tglobaladdr:$func)]>,
457 Requires<[IsThumb]>, Sched<[WriteBrL]> {
459 let Inst{26} = func{23};
460 let Inst{25-16} = func{20-11};
461 let Inst{13} = func{22};
462 let Inst{11} = func{21};
463 let Inst{10-0} = func{10-0};
466 // ARMv5T and above, also used for Thumb2
467 def tBLXi : TIx2<0b11110, 0b11, 0,
468 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br,
470 [(ARMcall tglobaladdr:$func)]>,
471 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> {
473 let Inst{26} = func{23};
474 let Inst{25-16} = func{20-11};
475 let Inst{13} = func{22};
476 let Inst{11} = func{21};
477 let Inst{10-1} = func{10-1};
478 let Inst{0} = 0; // func{0} is assumed zero
481 // Also used for Thumb2
482 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br,
484 [(ARMtcall GPR:$func)]>,
485 Requires<[IsThumb, HasV5T]>,
486 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24;
488 let Inst{6-3} = func;
489 let Inst{2-0} = 0b000;
493 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func),
495 [(ARMcall_nolink tGPR:$func)]>,
496 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>;
499 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
500 let isPredicable = 1 in
501 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
502 "b", "\t$target", [(br bb:$target)]>,
503 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> {
505 let Inst{10-0} = target;
506 let AsmMatchConverter = "cvtThumbBranches";
510 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
511 // the clobber of LR.
513 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
514 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>,
517 def tBR_JTr : tPseudoInst<(outs),
518 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
520 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
521 Sched<[WriteBrTbl]> {
522 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
526 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
527 // a two-value operand where a dag node expects two operands. :(
528 let isBranch = 1, isTerminator = 1 in
529 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
531 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
532 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> {
536 let Inst{7-0} = target;
537 let AsmMatchConverter = "cvtThumbBranches";
542 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
545 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst),
547 (tBX GPR:$dst, (ops 14, zero_reg))>,
548 Requires<[IsThumb]>, Sched<[WriteBr]>;
550 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
551 // on IOS), so it's in ARMInstrThumb2.td.
554 def tTAILJMPdND : tPseudoExpand<(outs),
555 (ins t_brtarget:$dst, pred:$p),
557 (tB t_brtarget:$dst, pred:$p)>,
558 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>;
563 // A8.6.218 Supervisor Call (Software Interrupt)
564 // A8.6.16 B: Encoding T1
565 // If Inst{11-8} == 0b1111 then SEE SVC
566 let isCall = 1, Uses = [SP] in
567 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
568 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> {
570 let Inst{15-12} = 0b1101;
571 let Inst{11-8} = 0b1111;
575 // The assembler uses 0xDEFE for a trap instruction.
576 let isBarrier = 1, isTerminator = 1 in
577 def tTRAP : TI<(outs), (ins), IIC_Br,
578 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> {
582 //===----------------------------------------------------------------------===//
583 // Load Store Instructions.
586 // Loads: reg/reg and reg/imm5
587 let canFoldAsLoad = 1, isReMaterializable = 1 in
588 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
589 Operand AddrMode_r, Operand AddrMode_i,
590 AddrMode am, InstrItinClass itin_r,
591 InstrItinClass itin_i, string asm,
594 T1pILdStEncode<reg_opc,
595 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
596 am, itin_r, asm, "\t$Rt, $addr",
597 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
599 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
600 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
601 am, itin_i, asm, "\t$Rt, $addr",
602 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
604 // Stores: reg/reg and reg/imm5
605 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
606 Operand AddrMode_r, Operand AddrMode_i,
607 AddrMode am, InstrItinClass itin_r,
608 InstrItinClass itin_i, string asm,
611 T1pILdStEncode<reg_opc,
612 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
613 am, itin_r, asm, "\t$Rt, $addr",
614 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
616 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
617 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
618 am, itin_i, asm, "\t$Rt, $addr",
619 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
623 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
624 t_addrmode_is4, AddrModeT1_4,
625 IIC_iLoad_r, IIC_iLoad_i, "ldr",
626 UnOpFrag<(load node:$Src)>>;
629 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
630 t_addrmode_is1, AddrModeT1_1,
631 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
632 UnOpFrag<(zextloadi8 node:$Src)>>;
635 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
636 t_addrmode_is2, AddrModeT1_2,
637 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
638 UnOpFrag<(zextloadi16 node:$Src)>>;
640 let AddedComplexity = 10 in
641 def tLDRSB : // A8.6.80
642 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
643 AddrModeT1_1, IIC_iLoad_bh_r,
644 "ldrsb", "\t$Rt, $addr",
645 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
647 let AddedComplexity = 10 in
648 def tLDRSH : // A8.6.84
649 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
650 AddrModeT1_2, IIC_iLoad_bh_r,
651 "ldrsh", "\t$Rt, $addr",
652 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
654 let canFoldAsLoad = 1 in
655 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
656 "ldr", "\t$Rt, $addr",
657 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
662 let Inst{7-0} = addr;
665 let canFoldAsLoad = 1, isReMaterializable = 1 in
666 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
667 "ldr", "\t$Rt, $addr",
668 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
669 T1Encoding<{0,1,0,0,1,?}> {
674 let Inst{7-0} = addr;
677 // A8.6.194 & A8.6.192
678 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
679 t_addrmode_is4, AddrModeT1_4,
680 IIC_iStore_r, IIC_iStore_i, "str",
681 BinOpFrag<(store node:$LHS, node:$RHS)>>;
683 // A8.6.197 & A8.6.195
684 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
685 t_addrmode_is1, AddrModeT1_1,
686 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
687 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
689 // A8.6.207 & A8.6.205
690 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
691 t_addrmode_is2, AddrModeT1_2,
692 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
693 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
696 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
697 "str", "\t$Rt, $addr",
698 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
703 let Inst{7-0} = addr;
706 //===----------------------------------------------------------------------===//
707 // Load / store multiple Instructions.
710 // These require base address to be written back or one of the loaded regs.
711 let neverHasSideEffects = 1 in {
713 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
714 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
715 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
719 let Inst{7-0} = regs;
722 // Writeback version is just a pseudo, as there's no encoding difference.
723 // Writeback happens iff the base register is not in the destination register
726 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
727 "$Rn = $wb", IIC_iLoad_mu>,
728 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
730 let OutOperandList = (outs GPR:$wb);
731 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
733 let isCodeGenOnly = 1;
735 list<Predicate> Predicates = [IsThumb];
738 // There is no non-writeback version of STM for Thumb.
739 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
740 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
741 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
742 AddrModeNone, 2, IIC_iStore_mu,
743 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
744 T1Encoding<{1,1,0,0,0,?}> {
748 let Inst{7-0} = regs;
751 } // neverHasSideEffects
753 def : InstAlias<"ldm${p} $Rn!, $regs",
754 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
755 Requires<[IsThumb, IsThumb1Only]>;
757 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
758 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
760 "pop${p}\t$regs", []>,
761 T1Misc<{1,1,0,?,?,?,?}> {
763 let Inst{8} = regs{15};
764 let Inst{7-0} = regs{7-0};
767 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
768 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
770 "push${p}\t$regs", []>,
771 T1Misc<{0,1,0,?,?,?,?}> {
773 let Inst{8} = regs{14};
774 let Inst{7-0} = regs{7-0};
777 //===----------------------------------------------------------------------===//
778 // Arithmetic Instructions.
781 // Helper classes for encoding T1pI patterns:
782 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
783 string opc, string asm, list<dag> pattern>
784 : T1pI<oops, iops, itin, opc, asm, pattern>,
785 T1DataProcessing<opA> {
791 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
792 string opc, string asm, list<dag> pattern>
793 : T1pI<oops, iops, itin, opc, asm, pattern>,
801 // Helper classes for encoding T1sI patterns:
802 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
803 string opc, string asm, list<dag> pattern>
804 : T1sI<oops, iops, itin, opc, asm, pattern>,
805 T1DataProcessing<opA> {
811 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
812 string opc, string asm, list<dag> pattern>
813 : T1sI<oops, iops, itin, opc, asm, pattern>,
822 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
823 string opc, string asm, list<dag> pattern>
824 : T1sI<oops, iops, itin, opc, asm, pattern>,
832 // Helper classes for encoding T1sIt patterns:
833 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
834 string opc, string asm, list<dag> pattern>
835 : T1sIt<oops, iops, itin, opc, asm, pattern>,
836 T1DataProcessing<opA> {
842 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
843 string opc, string asm, list<dag> pattern>
844 : T1sIt<oops, iops, itin, opc, asm, pattern>,
848 let Inst{10-8} = Rdn;
849 let Inst{7-0} = imm8;
852 // Add with carry register
853 let isCommutable = 1, Uses = [CPSR] in
855 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
856 "adc", "\t$Rdn, $Rm",
857 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
860 def tADDi3 : // A8.6.4 T1
861 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
863 "add", "\t$Rd, $Rm, $imm3",
864 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>,
867 let Inst{8-6} = imm3;
870 def tADDi8 : // A8.6.4 T2
871 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
872 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
873 "add", "\t$Rdn, $imm8",
874 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>,
878 let isCommutable = 1 in
879 def tADDrr : // A8.6.6 T1
880 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
882 "add", "\t$Rd, $Rn, $Rm",
883 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
885 let neverHasSideEffects = 1 in
886 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
887 "add", "\t$Rdn, $Rm", []>,
888 T1Special<{0,0,?,?}>, Sched<[WriteALU]> {
892 let Inst{7} = Rdn{3};
894 let Inst{2-0} = Rdn{2-0};
898 let isCommutable = 1 in
899 def tAND : // A8.6.12
900 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
902 "and", "\t$Rdn, $Rm",
903 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
906 def tASRri : // A8.6.14
907 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
909 "asr", "\t$Rd, $Rm, $imm5",
910 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
913 let Inst{10-6} = imm5;
917 def tASRrr : // A8.6.15
918 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
920 "asr", "\t$Rdn, $Rm",
921 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
924 def tBIC : // A8.6.20
925 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
927 "bic", "\t$Rdn, $Rm",
928 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>,
932 let isCompare = 1, Defs = [CPSR] in {
933 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
934 // Compare-to-zero still works out, just not the relationals
935 //def tCMN : // A8.6.33
936 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
938 // "cmn", "\t$lhs, $rhs",
939 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
941 def tCMNz : // A8.6.33
942 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
945 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>;
947 } // isCompare = 1, Defs = [CPSR]
950 let isCompare = 1, Defs = [CPSR] in {
951 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
952 "cmp", "\t$Rn, $imm8",
953 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
954 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> {
959 let Inst{7-0} = imm8;
963 def tCMPr : // A8.6.36 T1
964 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
967 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>;
969 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
970 "cmp", "\t$Rn, $Rm", []>,
971 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> {
977 let Inst{2-0} = Rn{2-0};
979 } // isCompare = 1, Defs = [CPSR]
983 let isCommutable = 1 in
984 def tEOR : // A8.6.45
985 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
987 "eor", "\t$Rdn, $Rm",
988 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
991 def tLSLri : // A8.6.88
992 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
994 "lsl", "\t$Rd, $Rm, $imm5",
995 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>,
998 let Inst{10-6} = imm5;
1002 def tLSLrr : // A8.6.89
1003 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1005 "lsl", "\t$Rdn, $Rm",
1006 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1009 def tLSRri : // A8.6.90
1010 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1012 "lsr", "\t$Rd, $Rm, $imm5",
1013 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>,
1016 let Inst{10-6} = imm5;
1020 def tLSRrr : // A8.6.91
1021 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1023 "lsr", "\t$Rdn, $Rm",
1024 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1027 let isMoveImm = 1 in
1028 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1029 "mov", "\t$Rd, $imm8",
1030 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1031 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> {
1035 let Inst{10-8} = Rd;
1036 let Inst{7-0} = imm8;
1038 // Because we have an explicit tMOVSr below, we need an alias to handle
1039 // the immediate "movs" form here. Blech.
1040 def : tInstAlias <"movs $Rdn, $imm",
1041 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1043 // A7-73: MOV(2) - mov setting flag.
1045 let neverHasSideEffects = 1 in {
1046 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1048 "mov", "\t$Rd, $Rm", "", []>,
1049 T1Special<{1,0,?,?}>, Sched<[WriteALU]> {
1053 let Inst{7} = Rd{3};
1055 let Inst{2-0} = Rd{2-0};
1057 let Defs = [CPSR] in
1058 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1059 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> {
1063 let Inst{15-6} = 0b0000000000;
1067 } // neverHasSideEffects
1069 // Multiply register
1070 let isCommutable = 1 in
1071 def tMUL : // A8.6.105 T1
1072 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1073 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1074 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1075 T1DataProcessing<0b1101> {
1080 let AsmMatchConverter = "cvtThumbMultiply";
1083 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1086 // Move inverse register
1087 def tMVN : // A8.6.107
1088 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1089 "mvn", "\t$Rd, $Rn",
1090 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>;
1092 // Bitwise or register
1093 let isCommutable = 1 in
1094 def tORR : // A8.6.114
1095 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1097 "orr", "\t$Rdn, $Rm",
1098 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>;
1101 def tREV : // A8.6.134
1102 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1104 "rev", "\t$Rd, $Rm",
1105 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1106 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1108 def tREV16 : // A8.6.135
1109 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1111 "rev16", "\t$Rd, $Rm",
1112 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1113 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1115 def tREVSH : // A8.6.136
1116 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1118 "revsh", "\t$Rd, $Rm",
1119 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1120 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1122 // Rotate right register
1123 def tROR : // A8.6.139
1124 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1126 "ror", "\t$Rdn, $Rm",
1127 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>,
1131 def tRSB : // A8.6.141
1132 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1134 "rsb", "\t$Rd, $Rn, #0",
1135 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>;
1137 // Subtract with carry register
1138 let Uses = [CPSR] in
1139 def tSBC : // A8.6.151
1140 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1142 "sbc", "\t$Rdn, $Rm",
1143 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>,
1146 // Subtract immediate
1147 def tSUBi3 : // A8.6.210 T1
1148 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1150 "sub", "\t$Rd, $Rm, $imm3",
1151 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>,
1154 let Inst{8-6} = imm3;
1157 def tSUBi8 : // A8.6.210 T2
1158 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1159 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1160 "sub", "\t$Rdn, $imm8",
1161 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>,
1164 // Subtract register
1165 def tSUBrr : // A8.6.212
1166 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1168 "sub", "\t$Rd, $Rn, $Rm",
1169 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>,
1173 def tSXTB : // A8.6.222
1174 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1176 "sxtb", "\t$Rd, $Rm",
1177 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1178 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1181 // Sign-extend short
1182 def tSXTH : // A8.6.224
1183 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1185 "sxth", "\t$Rd, $Rm",
1186 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1187 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1191 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1192 def tTST : // A8.6.230
1193 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1194 "tst", "\t$Rn, $Rm",
1195 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>,
1199 def tUXTB : // A8.6.262
1200 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1202 "uxtb", "\t$Rd, $Rm",
1203 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1204 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1207 // Zero-extend short
1208 def tUXTH : // A8.6.264
1209 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1211 "uxth", "\t$Rd, $Rm",
1212 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1213 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>;
1215 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1216 // Expanded after instruction selection into a branch sequence.
1217 let usesCustomInserter = 1 in // Expanded after instruction selection.
1218 def tMOVCCr_pseudo :
1219 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p),
1221 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>;
1223 // tLEApcrel - Load a pc-relative address into a register without offending the
1226 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1227 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1228 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> {
1231 let Inst{10-8} = Rd;
1232 let Inst{7-0} = addr;
1233 let DecoderMethod = "DecodeThumbAddSpecialReg";
1236 let neverHasSideEffects = 1, isReMaterializable = 1 in
1237 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1238 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1240 let hasSideEffects = 1 in
1241 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1242 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1243 2, IIC_iALUi, []>, Sched<[WriteALU]>;
1245 //===----------------------------------------------------------------------===//
1249 // __aeabi_read_tp preserves the registers r1-r3.
1250 // This is a pseudo inst so that we can get the encoding right,
1251 // complete with fixup for the aeabi_read_tp function.
1252 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1253 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1254 [(set R0, ARMthread_pointer)]>,
1257 //===----------------------------------------------------------------------===//
1258 // SJLJ Exception handling intrinsics
1261 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1262 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1263 // from some other function to get here, and we're using the stack frame for the
1264 // containing function to save/restore registers, we can't keep anything live in
1265 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1266 // tromped upon when we get here from a longjmp(). We force everything out of
1267 // registers except for our own input by listing the relevant registers in
1268 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1269 // preserve all of the callee-saved resgisters, which is exactly what we want.
1270 // $val is a scratch register for our use.
1271 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1272 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1273 usesCustomInserter = 1 in
1274 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1275 AddrModeNone, 0, NoItinerary, "","",
1276 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1278 // FIXME: Non-IOS version(s)
1279 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1280 Defs = [ R7, LR, SP ] in
1281 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1282 AddrModeNone, 0, IndexModeNone,
1283 Pseudo, NoItinerary, "", "",
1284 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1285 Requires<[IsThumb, IsIOS]>;
1287 //===----------------------------------------------------------------------===//
1288 // Non-Instruction Patterns
1292 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1293 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1294 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1295 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1298 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1299 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1300 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1301 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1302 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1303 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1305 // Subtract with carry
1306 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1307 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1308 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1309 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1310 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1311 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1313 // ConstantPool, GlobalAddress
1314 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1315 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1318 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1319 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1322 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1323 Requires<[IsThumb]>;
1325 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1326 Requires<[IsThumb, HasV5T]>;
1328 // Indirect calls to ARM routines
1329 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1330 Requires<[IsThumb, HasV5T]>;
1332 // zextload i1 -> zextload i8
1333 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1334 (tLDRBr t_addrmode_rrs1:$addr)>;
1335 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1336 (tLDRBi t_addrmode_is1:$addr)>;
1338 // extload -> zextload
1339 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1340 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1341 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1342 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1343 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1344 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1346 // If it's impossible to use [r,r] address mode for sextload, select to
1347 // ldr{b|h} + sxt{b|h} instead.
1348 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1349 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1350 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1351 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1352 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1353 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1354 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1355 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1356 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1357 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1358 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1359 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1361 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1362 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1363 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1364 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1365 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1366 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1367 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1368 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1370 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1371 (tLDRBi t_addrmode_is1:$src)>;
1372 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1373 (tLDRBr t_addrmode_rrs1:$src)>;
1374 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1375 (tLDRHi t_addrmode_is2:$src)>;
1376 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1377 (tLDRHr t_addrmode_rrs2:$src)>;
1378 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1379 (tLDRi t_addrmode_is4:$src)>;
1380 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1381 (tLDRr t_addrmode_rrs4:$src)>;
1382 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1383 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1384 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1385 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1386 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1387 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1388 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1389 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1390 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1391 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1392 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1393 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1395 // Large immediate handling.
1398 def : T1Pat<(i32 thumb_immshifted:$src),
1399 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1400 (thumb_immshifted_shamt imm:$src))>;
1402 def : T1Pat<(i32 imm0_255_comp:$src),
1403 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1405 // Pseudo instruction that combines ldr from constpool and add pc. This should
1406 // be expanded into two instructions late to allow if-conversion and
1408 let isReMaterializable = 1 in
1409 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1411 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1413 Requires<[IsThumb, IsThumb1Only]>;
1415 // Pseudo-instruction for merged POP and return.
1416 // FIXME: remove when we have a way to marking a MI with these properties.
1417 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1418 hasExtraDefRegAllocReq = 1 in
1419 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1421 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>;
1423 // Indirect branch using "mov pc, $Rm"
1424 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1425 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1426 2, IIC_Br, [(brind GPR:$Rm)],
1427 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>;
1431 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1432 // encoding is available on ARMv6K, but we don't differentiate that finely.
1433 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1436 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1437 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1438 // a useful extension and assembles to defined behaviour (the insn does
1440 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1441 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1443 // "neg" is and alias for "rsb rd, rn, #0"
1444 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1445 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1448 // Implied destination operand forms for shifts.
1449 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1450 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1451 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1452 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1453 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1454 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;