1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
82 def t_imm0_1020s4 : Operand<i32> {
83 let PrintMethod = "printThumbS4ImmOperand";
84 let ParserMatchClass = t_imm0_1020s4_asmoperand;
85 let OperandType = "OPERAND_IMMEDIATE";
88 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
89 def t_imm0_508s4 : Operand<i32> {
90 let PrintMethod = "printThumbS4ImmOperand";
91 let ParserMatchClass = t_imm0_508s4_asmoperand;
92 let OperandType = "OPERAND_IMMEDIATE";
95 // Define Thumb specific addressing modes.
97 let OperandType = "OPERAND_PCREL" in {
98 def t_brtarget : Operand<OtherVT> {
99 let EncoderMethod = "getThumbBRTargetOpValue";
100 let DecoderMethod = "DecodeThumbBROperand";
103 def t_bcctarget : Operand<i32> {
104 let EncoderMethod = "getThumbBCCTargetOpValue";
105 let DecoderMethod = "DecodeThumbBCCTargetOperand";
108 def t_cbtarget : Operand<i32> {
109 let EncoderMethod = "getThumbCBTargetOpValue";
110 let DecoderMethod = "DecodeThumbCmpBROperand";
113 def t_bltarget : Operand<i32> {
114 let EncoderMethod = "getThumbBLTargetOpValue";
115 let DecoderMethod = "DecodeThumbBLTargetOperand";
118 def t_blxtarget : Operand<i32> {
119 let EncoderMethod = "getThumbBLXTargetOpValue";
120 let DecoderMethod = "DecodeThumbBLXOffset";
124 // t_addrmode_rr := reg + reg
126 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
127 def t_addrmode_rr : Operand<i32>,
128 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
129 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
130 let PrintMethod = "printThumbAddrModeRROperand";
131 let DecoderMethod = "DecodeThumbAddrModeRR";
132 let ParserMatchClass = t_addrmode_rr_asm_operand;
133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
136 // t_addrmode_rrs := reg + reg
138 // We use separate scaled versions because the Select* functions need
139 // to explicitly check for a matching constant and return false here so that
140 // the reg+imm forms will match instead. This is a horrible way to do that,
141 // as it forces tight coupling between the methods, but it's how selectiondag
143 def t_addrmode_rrs1 : Operand<i32>,
144 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
145 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
146 let PrintMethod = "printThumbAddrModeRROperand";
147 let DecoderMethod = "DecodeThumbAddrModeRR";
148 let ParserMatchClass = t_addrmode_rr_asm_operand;
149 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
151 def t_addrmode_rrs2 : Operand<i32>,
152 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
153 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
154 let DecoderMethod = "DecodeThumbAddrModeRR";
155 let PrintMethod = "printThumbAddrModeRROperand";
156 let ParserMatchClass = t_addrmode_rr_asm_operand;
157 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
159 def t_addrmode_rrs4 : Operand<i32>,
160 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
161 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
162 let DecoderMethod = "DecodeThumbAddrModeRR";
163 let PrintMethod = "printThumbAddrModeRROperand";
164 let ParserMatchClass = t_addrmode_rr_asm_operand;
165 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
168 // t_addrmode_is4 := reg + imm5 * 4
170 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
171 def t_addrmode_is4 : Operand<i32>,
172 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
173 let EncoderMethod = "getAddrModeISOpValue";
174 let DecoderMethod = "DecodeThumbAddrModeIS";
175 let PrintMethod = "printThumbAddrModeImm5S4Operand";
176 let ParserMatchClass = t_addrmode_is4_asm_operand;
177 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
180 // t_addrmode_is2 := reg + imm5 * 2
182 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
183 def t_addrmode_is2 : Operand<i32>,
184 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
185 let EncoderMethod = "getAddrModeISOpValue";
186 let DecoderMethod = "DecodeThumbAddrModeIS";
187 let PrintMethod = "printThumbAddrModeImm5S2Operand";
188 let ParserMatchClass = t_addrmode_is2_asm_operand;
189 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
192 // t_addrmode_is1 := reg + imm5
194 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
195 def t_addrmode_is1 : Operand<i32>,
196 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
197 let EncoderMethod = "getAddrModeISOpValue";
198 let DecoderMethod = "DecodeThumbAddrModeIS";
199 let PrintMethod = "printThumbAddrModeImm5S1Operand";
200 let ParserMatchClass = t_addrmode_is1_asm_operand;
201 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
204 // t_addrmode_sp := sp + imm8 * 4
206 // FIXME: This really shouldn't have an explicit SP operand at all. It should
207 // be implicit, just like in the instruction encoding itself.
208 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
209 def t_addrmode_sp : Operand<i32>,
210 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
211 let EncoderMethod = "getAddrModeThumbSPOpValue";
212 let DecoderMethod = "DecodeThumbAddrModeSP";
213 let PrintMethod = "printThumbAddrModeSPOperand";
214 let ParserMatchClass = t_addrmode_sp_asm_operand;
215 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
218 // t_addrmode_pc := <label> => pc + imm8 * 4
220 def t_addrmode_pc : Operand<i32> {
221 let EncoderMethod = "getAddrModePCOpValue";
222 let DecoderMethod = "DecodeThumbAddrModePC";
225 //===----------------------------------------------------------------------===//
226 // Miscellaneous Instructions.
229 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
230 // from removing one half of the matched pairs. That breaks PEI, which assumes
231 // these will always be in pairs, and asserts if it finds otherwise. Better way?
232 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
233 def tADJCALLSTACKUP :
234 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
235 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
236 Requires<[IsThumb, IsThumb1Only]>;
238 def tADJCALLSTACKDOWN :
239 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
240 [(ARMcallseq_start imm:$amt)]>,
241 Requires<[IsThumb, IsThumb1Only]>;
244 class T1SystemEncoding<bits<8> opc>
245 : T1Encoding<0b101111> {
246 let Inst{9-8} = 0b11;
250 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
251 T1SystemEncoding<0x00>, // A8.6.110
252 Requires<[IsThumb2]>;
254 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
255 T1SystemEncoding<0x10>; // A8.6.410
257 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
258 T1SystemEncoding<0x20>; // A8.6.408
260 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
261 T1SystemEncoding<0x30>; // A8.6.409
263 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
264 T1SystemEncoding<0x40>; // A8.6.157
266 // The imm operand $val can be used by a debugger to store more information
267 // about the breakpoint.
268 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
270 T1Encoding<0b101111> {
271 let Inst{9-8} = 0b10;
277 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
278 []>, T1Encoding<0b101101> {
281 let Inst{9-5} = 0b10010;
284 let Inst{2-0} = 0b000;
287 // Change Processor State is a system instruction -- for disassembly only.
288 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
289 NoItinerary, "cps$imod $iflags",
290 [/* For disassembly only; pattern left blank */]>,
298 let Inst{2-0} = iflags;
299 let DecoderMethod = "DecodeThumbCPS";
302 // For both thumb1 and thumb2.
303 let isNotDuplicable = 1, isCodeGenOnly = 1 in
304 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
305 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
306 T1Special<{0,0,?,?}> {
309 let Inst{6-3} = 0b1111; // Rm = pc
313 // ADD <Rd>, sp, #<imm8>
314 // This is rematerializable, which is particularly useful for taking the
315 // address of locals.
316 let isReMaterializable = 1 in
317 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
318 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
319 T1Encoding<{1,0,1,0,1,?}> {
323 let Inst{10-8} = dst;
325 let DecoderMethod = "DecodeThumbAddSpecialReg";
328 // ADD sp, sp, #<imm7>
329 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
330 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
331 T1Misc<{0,0,0,0,0,?,?}> {
335 let DecoderMethod = "DecodeThumbAddSPImm";
338 // Can optionally specify SP as a three operand instruction.
339 def : tInstAlias<"add${p} sp, sp, $imm",
340 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
342 // SUB sp, sp, #<imm7>
343 // FIXME: The encoding and the ASM string don't match up.
344 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
345 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
346 T1Misc<{0,0,0,0,1,?,?}> {
350 let DecoderMethod = "DecodeThumbAddSPImm";
354 def tADDrSP : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPRsp:$sp), IIC_iALUr,
355 "add", "\t$Rdn, $sp, $Rn", []>,
356 T1Special<{0,0,?,?}> {
357 // A8.6.9 Encoding T1
359 let Inst{7} = Rdn{3};
360 let Inst{6-3} = 0b1101;
361 let Inst{2-0} = Rdn{2-0};
362 let DecoderMethod = "DecodeThumbAddSPReg";
366 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
367 "add", "\t$Rdn, $Rm", []>,
368 T1Special<{0,0,?,?}> {
369 // A8.6.9 Encoding T2
373 let Inst{2-0} = 0b101;
374 let DecoderMethod = "DecodeThumbAddSPReg";
377 //===----------------------------------------------------------------------===//
378 // Control Flow Instructions.
382 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
383 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
384 T1Special<{1,1,0,?}> {
388 let Inst{2-0} = 0b000;
392 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
393 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
394 [(ARMretflag)], (tBX LR, pred:$p)>;
396 // Alternative return instruction used by vararg functions.
397 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
399 (tBX GPR:$Rm, pred:$p)>;
402 // All calls clobber the non-callee saved registers. SP is marked as a use to
403 // prevent stack-pointer assignments that appear immediately before calls from
404 // potentially appearing dead.
406 // On non-Darwin platforms R9 is callee-saved.
407 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
409 // Also used for Thumb2
410 def tBL : TIx2<0b11110, 0b11, 1,
411 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
413 [(ARMtcall tglobaladdr:$func)]>,
414 Requires<[IsThumb, IsNotDarwin]> {
416 let Inst{26} = func{21};
417 let Inst{25-16} = func{20-11};
420 let Inst{10-0} = func{10-0};
423 // ARMv5T and above, also used for Thumb2
424 def tBLXi : TIx2<0b11110, 0b11, 0,
425 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
427 [(ARMcall tglobaladdr:$func)]>,
428 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
430 let Inst{25-16} = func{20-11};
433 let Inst{10-1} = func{10-1};
434 let Inst{0} = 0; // func{0} is assumed zero
437 // Also used for Thumb2
438 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
440 [(ARMtcall GPR:$func)]>,
441 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
442 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
444 let Inst{6-3} = func;
445 let Inst{2-0} = 0b000;
449 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
451 [(ARMcall_nolink tGPR:$func)]>,
452 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
456 // On Darwin R9 is call-clobbered.
457 // R7 is marked as a use to prevent frame-pointer assignments from being
458 // moved above / below calls.
459 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
461 // Also used for Thumb2
462 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
463 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
464 (tBL pred:$p, t_bltarget:$func)>,
465 Requires<[IsThumb, IsDarwin]>;
467 // ARMv5T and above, also used for Thumb2
468 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
469 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
470 (tBLXi pred:$p, t_blxtarget:$func)>,
471 Requires<[IsThumb, HasV5T, IsDarwin]>;
473 // Also used for Thumb2
474 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
475 2, IIC_Br, [(ARMtcall GPR:$func)],
476 (tBLXr pred:$p, GPR:$func)>,
477 Requires<[IsThumb, HasV5T, IsDarwin]>;
480 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
482 [(ARMcall_nolink tGPR:$func)]>,
483 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
486 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
487 let isPredicable = 1 in
488 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
489 "b\t$target", [(br bb:$target)]>,
490 T1Encoding<{1,1,1,0,0,?}> {
492 let Inst{10-0} = target;
496 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
497 // the clobber of LR.
499 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
500 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
502 def tBR_JTr : tPseudoInst<(outs),
503 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
505 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
506 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
510 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
511 // a two-value operand where a dag node expects two operands. :(
512 let isBranch = 1, isTerminator = 1 in
513 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
515 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
516 T1BranchCond<{1,1,0,1}> {
520 let Inst{7-0} = target;
524 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
526 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
528 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
529 // on Darwin), so it's in ARMInstrThumb2.td.
530 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
532 (tBX GPR:$dst, (ops 14, zero_reg))>,
533 Requires<[IsThumb, IsDarwin]>;
535 // Non-Darwin versions (the difference is R9).
536 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
538 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
540 (tB t_brtarget:$dst)>,
541 Requires<[IsThumb, IsNotDarwin]>;
542 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
544 (tBX GPR:$dst, (ops 14, zero_reg))>,
545 Requires<[IsThumb, IsNotDarwin]>;
550 // A8.6.218 Supervisor Call (Software Interrupt)
551 // A8.6.16 B: Encoding T1
552 // If Inst{11-8} == 0b1111 then SEE SVC
553 let isCall = 1, Uses = [SP] in
554 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
555 "svc", "\t$imm", []>, Encoding16 {
557 let Inst{15-12} = 0b1101;
558 let Inst{11-8} = 0b1111;
562 // The assembler uses 0xDEFE for a trap instruction.
563 let isBarrier = 1, isTerminator = 1 in
564 def tTRAP : TI<(outs), (ins), IIC_Br,
565 "trap", [(trap)]>, Encoding16 {
569 //===----------------------------------------------------------------------===//
570 // Load Store Instructions.
573 // Loads: reg/reg and reg/imm5
574 let canFoldAsLoad = 1, isReMaterializable = 1 in
575 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
576 Operand AddrMode_r, Operand AddrMode_i,
577 AddrMode am, InstrItinClass itin_r,
578 InstrItinClass itin_i, string asm,
581 T1pILdStEncode<reg_opc,
582 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
583 am, itin_r, asm, "\t$Rt, $addr",
584 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
586 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
587 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
588 am, itin_i, asm, "\t$Rt, $addr",
589 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
591 // Stores: reg/reg and reg/imm5
592 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
593 Operand AddrMode_r, Operand AddrMode_i,
594 AddrMode am, InstrItinClass itin_r,
595 InstrItinClass itin_i, string asm,
598 T1pILdStEncode<reg_opc,
599 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
600 am, itin_r, asm, "\t$Rt, $addr",
601 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
603 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
604 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
605 am, itin_i, asm, "\t$Rt, $addr",
606 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
610 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
611 t_addrmode_is4, AddrModeT1_4,
612 IIC_iLoad_r, IIC_iLoad_i, "ldr",
613 UnOpFrag<(load node:$Src)>>;
616 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
617 t_addrmode_is1, AddrModeT1_1,
618 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
619 UnOpFrag<(zextloadi8 node:$Src)>>;
622 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
623 t_addrmode_is2, AddrModeT1_2,
624 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
625 UnOpFrag<(zextloadi16 node:$Src)>>;
627 let AddedComplexity = 10 in
628 def tLDRSB : // A8.6.80
629 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
630 AddrModeT1_1, IIC_iLoad_bh_r,
631 "ldrsb", "\t$Rt, $addr",
632 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
634 let AddedComplexity = 10 in
635 def tLDRSH : // A8.6.84
636 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
637 AddrModeT1_2, IIC_iLoad_bh_r,
638 "ldrsh", "\t$Rt, $addr",
639 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
641 let canFoldAsLoad = 1 in
642 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
643 "ldr", "\t$Rt, $addr",
644 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
649 let Inst{7-0} = addr;
653 // FIXME: Use ldr.n to work around a Darwin assembler bug.
654 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
655 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
656 "ldr", ".n\t$Rt, $addr",
657 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
658 T1Encoding<{0,1,0,0,1,?}> {
663 let Inst{7-0} = addr;
666 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
667 // For disassembly use only.
668 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
669 "ldr", "\t$Rt, $addr",
670 [/* disassembly only */]>,
671 T1Encoding<{0,1,0,0,1,?}> {
676 let Inst{7-0} = addr;
679 // A8.6.194 & A8.6.192
680 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
681 t_addrmode_is4, AddrModeT1_4,
682 IIC_iStore_r, IIC_iStore_i, "str",
683 BinOpFrag<(store node:$LHS, node:$RHS)>>;
685 // A8.6.197 & A8.6.195
686 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
687 t_addrmode_is1, AddrModeT1_1,
688 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
689 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
691 // A8.6.207 & A8.6.205
692 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
693 t_addrmode_is2, AddrModeT1_2,
694 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
695 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
698 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
699 "str", "\t$Rt, $addr",
700 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
705 let Inst{7-0} = addr;
708 //===----------------------------------------------------------------------===//
709 // Load / store multiple Instructions.
712 // These require base address to be written back or one of the loaded regs.
713 let neverHasSideEffects = 1 in {
715 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
716 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
717 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
721 let Inst{7-0} = regs;
724 // Writeback version is just a pseudo, as there's no encoding difference.
725 // Writeback happens iff the base register is not in the destination register
728 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
729 "$Rn = $wb", IIC_iLoad_mu>,
730 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
732 let OutOperandList = (outs GPR:$wb);
733 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
735 let isCodeGenOnly = 1;
737 list<Predicate> Predicates = [IsThumb];
740 // There is no non-writeback version of STM for Thumb.
741 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
742 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
743 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
744 AddrModeNone, 2, IIC_iStore_mu,
745 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
746 T1Encoding<{1,1,0,0,0,?}> {
750 let Inst{7-0} = regs;
753 } // neverHasSideEffects
755 def : InstAlias<"ldm${p} $Rn!, $regs",
756 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
757 Requires<[IsThumb, IsThumb1Only]>;
759 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
760 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
762 "pop${p}\t$regs", []>,
763 T1Misc<{1,1,0,?,?,?,?}> {
765 let Inst{8} = regs{15};
766 let Inst{7-0} = regs{7-0};
769 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
770 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
772 "push${p}\t$regs", []>,
773 T1Misc<{0,1,0,?,?,?,?}> {
775 let Inst{8} = regs{14};
776 let Inst{7-0} = regs{7-0};
779 //===----------------------------------------------------------------------===//
780 // Arithmetic Instructions.
783 // Helper classes for encoding T1pI patterns:
784 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
785 string opc, string asm, list<dag> pattern>
786 : T1pI<oops, iops, itin, opc, asm, pattern>,
787 T1DataProcessing<opA> {
793 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
794 string opc, string asm, list<dag> pattern>
795 : T1pI<oops, iops, itin, opc, asm, pattern>,
803 // Helper classes for encoding T1sI patterns:
804 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
805 string opc, string asm, list<dag> pattern>
806 : T1sI<oops, iops, itin, opc, asm, pattern>,
807 T1DataProcessing<opA> {
813 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
814 string opc, string asm, list<dag> pattern>
815 : T1sI<oops, iops, itin, opc, asm, pattern>,
824 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
825 string opc, string asm, list<dag> pattern>
826 : T1sI<oops, iops, itin, opc, asm, pattern>,
834 // Helper classes for encoding T1sIt patterns:
835 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
836 string opc, string asm, list<dag> pattern>
837 : T1sIt<oops, iops, itin, opc, asm, pattern>,
838 T1DataProcessing<opA> {
844 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
845 string opc, string asm, list<dag> pattern>
846 : T1sIt<oops, iops, itin, opc, asm, pattern>,
850 let Inst{10-8} = Rdn;
851 let Inst{7-0} = imm8;
854 // Add with carry register
855 let isCommutable = 1, Uses = [CPSR] in
857 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
858 "adc", "\t$Rdn, $Rm",
859 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
862 def tADDi3 : // A8.6.4 T1
863 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
865 "add", "\t$Rd, $Rm, $imm3",
866 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
868 let Inst{8-6} = imm3;
871 def tADDi8 : // A8.6.4 T2
872 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
873 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
874 "add", "\t$Rdn, $imm8",
875 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
878 let isCommutable = 1 in
879 def tADDrr : // A8.6.6 T1
880 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
882 "add", "\t$Rd, $Rn, $Rm",
883 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
885 let neverHasSideEffects = 1 in
886 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
887 "add", "\t$Rdn, $Rm", []>,
888 T1Special<{0,0,?,?}> {
892 let Inst{7} = Rdn{3};
894 let Inst{2-0} = Rdn{2-0};
898 let isCommutable = 1 in
899 def tAND : // A8.6.12
900 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
902 "and", "\t$Rdn, $Rm",
903 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
906 def tASRri : // A8.6.14
907 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
909 "asr", "\t$Rd, $Rm, $imm5",
910 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
912 let Inst{10-6} = imm5;
916 def tASRrr : // A8.6.15
917 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
919 "asr", "\t$Rdn, $Rm",
920 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
923 def tBIC : // A8.6.20
924 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
926 "bic", "\t$Rdn, $Rm",
927 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
930 let isCompare = 1, Defs = [CPSR] in {
931 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
932 // Compare-to-zero still works out, just not the relationals
933 //def tCMN : // A8.6.33
934 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
936 // "cmn", "\t$lhs, $rhs",
937 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
939 def tCMNz : // A8.6.33
940 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
943 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
945 } // isCompare = 1, Defs = [CPSR]
948 let isCompare = 1, Defs = [CPSR] in {
949 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
950 "cmp", "\t$Rn, $imm8",
951 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
952 T1General<{1,0,1,?,?}> {
957 let Inst{7-0} = imm8;
961 def tCMPr : // A8.6.36 T1
962 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
965 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
967 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
968 "cmp", "\t$Rn, $Rm", []>,
969 T1Special<{0,1,?,?}> {
975 let Inst{2-0} = Rn{2-0};
977 } // isCompare = 1, Defs = [CPSR]
981 let isCommutable = 1 in
982 def tEOR : // A8.6.45
983 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
985 "eor", "\t$Rdn, $Rm",
986 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
989 def tLSLri : // A8.6.88
990 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
992 "lsl", "\t$Rd, $Rm, $imm5",
993 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
995 let Inst{10-6} = imm5;
999 def tLSLrr : // A8.6.89
1000 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1002 "lsl", "\t$Rdn, $Rm",
1003 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1006 def tLSRri : // A8.6.90
1007 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
1009 "lsr", "\t$Rd, $Rm, $imm5",
1010 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
1012 let Inst{10-6} = imm5;
1016 def tLSRrr : // A8.6.91
1017 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1019 "lsr", "\t$Rdn, $Rm",
1020 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1023 let isMoveImm = 1 in
1024 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1025 "mov", "\t$Rd, $imm8",
1026 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1027 T1General<{1,0,0,?,?}> {
1031 let Inst{10-8} = Rd;
1032 let Inst{7-0} = imm8;
1034 // Because we have an explicit tMOVSr below, we need an alias to handle
1035 // the immediate "movs" form here. Blech.
1036 def : tInstAlias <"movs $Rdn, $imm",
1037 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1039 // A7-73: MOV(2) - mov setting flag.
1041 let neverHasSideEffects = 1 in {
1042 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1044 "mov", "\t$Rd, $Rm", "", []>,
1045 T1Special<{1,0,?,?}> {
1049 let Inst{7} = Rd{3};
1051 let Inst{2-0} = Rd{2-0};
1053 let Defs = [CPSR] in
1054 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1055 "movs\t$Rd, $Rm", []>, Encoding16 {
1059 let Inst{15-6} = 0b0000000000;
1063 } // neverHasSideEffects
1065 // Multiply register
1066 let isCommutable = 1 in
1067 def tMUL : // A8.6.105 T1
1068 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1069 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1070 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1071 T1DataProcessing<0b1101> {
1076 let AsmMatchConverter = "cvtThumbMultiply";
1079 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1082 // Move inverse register
1083 def tMVN : // A8.6.107
1084 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1085 "mvn", "\t$Rd, $Rn",
1086 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1088 // Bitwise or register
1089 let isCommutable = 1 in
1090 def tORR : // A8.6.114
1091 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1093 "orr", "\t$Rdn, $Rm",
1094 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1097 def tREV : // A8.6.134
1098 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1100 "rev", "\t$Rd, $Rm",
1101 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1102 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1104 def tREV16 : // A8.6.135
1105 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1107 "rev16", "\t$Rd, $Rm",
1108 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1109 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1111 def tREVSH : // A8.6.136
1112 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1114 "revsh", "\t$Rd, $Rm",
1115 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1116 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1118 // Rotate right register
1119 def tROR : // A8.6.139
1120 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1122 "ror", "\t$Rdn, $Rm",
1123 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1126 def tRSB : // A8.6.141
1127 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1129 "rsb", "\t$Rd, $Rn, #0",
1130 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1132 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1133 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1135 // Subtract with carry register
1136 let Uses = [CPSR] in
1137 def tSBC : // A8.6.151
1138 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1140 "sbc", "\t$Rdn, $Rm",
1141 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1143 // Subtract immediate
1144 def tSUBi3 : // A8.6.210 T1
1145 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1147 "sub", "\t$Rd, $Rm, $imm3",
1148 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1150 let Inst{8-6} = imm3;
1153 def tSUBi8 : // A8.6.210 T2
1154 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1156 "sub", "\t$Rdn, $imm8",
1157 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1159 // Subtract register
1160 def tSUBrr : // A8.6.212
1161 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1163 "sub", "\t$Rd, $Rn, $Rm",
1164 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1167 def tSXTB : // A8.6.222
1168 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1170 "sxtb", "\t$Rd, $Rm",
1171 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1172 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1174 // Sign-extend short
1175 def tSXTH : // A8.6.224
1176 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1178 "sxth", "\t$Rd, $Rm",
1179 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1180 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1183 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1184 def tTST : // A8.6.230
1185 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1186 "tst", "\t$Rn, $Rm",
1187 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1190 def tUXTB : // A8.6.262
1191 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1193 "uxtb", "\t$Rd, $Rm",
1194 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1195 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1197 // Zero-extend short
1198 def tUXTH : // A8.6.264
1199 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1201 "uxth", "\t$Rd, $Rm",
1202 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1203 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1205 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1206 // Expanded after instruction selection into a branch sequence.
1207 let usesCustomInserter = 1 in // Expanded after instruction selection.
1208 def tMOVCCr_pseudo :
1209 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1211 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1213 // tLEApcrel - Load a pc-relative address into a register without offending the
1216 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1217 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1218 T1Encoding<{1,0,1,0,0,?}> {
1221 let Inst{10-8} = Rd;
1222 let Inst{7-0} = addr;
1223 let DecoderMethod = "DecodeThumbAddSpecialReg";
1226 let neverHasSideEffects = 1, isReMaterializable = 1 in
1227 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1230 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1231 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1234 //===----------------------------------------------------------------------===//
1238 // __aeabi_read_tp preserves the registers r1-r3.
1239 // This is a pseudo inst so that we can get the encoding right,
1240 // complete with fixup for the aeabi_read_tp function.
1241 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1242 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1243 [(set R0, ARMthread_pointer)]>;
1245 //===----------------------------------------------------------------------===//
1246 // SJLJ Exception handling intrinsics
1249 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1250 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1251 // from some other function to get here, and we're using the stack frame for the
1252 // containing function to save/restore registers, we can't keep anything live in
1253 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1254 // tromped upon when we get here from a longjmp(). We force everything out of
1255 // registers except for our own input by listing the relevant registers in
1256 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1257 // preserve all of the callee-saved resgisters, which is exactly what we want.
1258 // $val is a scratch register for our use.
1259 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1260 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1261 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1262 AddrModeNone, 0, NoItinerary, "","",
1263 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1265 // FIXME: Non-Darwin version(s)
1266 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1267 Defs = [ R7, LR, SP ] in
1268 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1269 AddrModeNone, 0, IndexModeNone,
1270 Pseudo, NoItinerary, "", "",
1271 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1272 Requires<[IsThumb, IsDarwin]>;
1274 //===----------------------------------------------------------------------===//
1275 // Non-Instruction Patterns
1279 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1280 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1281 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1282 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1285 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1286 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1287 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1288 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1289 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1290 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1292 // Subtract with carry
1293 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1294 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1295 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1296 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1297 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1298 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1300 // ConstantPool, GlobalAddress
1301 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1302 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1305 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1306 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1309 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1310 Requires<[IsThumb, IsNotDarwin]>;
1311 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1312 Requires<[IsThumb, IsDarwin]>;
1314 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1315 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1316 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1317 Requires<[IsThumb, HasV5T, IsDarwin]>;
1319 // Indirect calls to ARM routines
1320 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1321 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1322 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1323 Requires<[IsThumb, HasV5T, IsDarwin]>;
1325 // zextload i1 -> zextload i8
1326 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1327 (tLDRBr t_addrmode_rrs1:$addr)>;
1328 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1329 (tLDRBi t_addrmode_is1:$addr)>;
1331 // extload -> zextload
1332 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1333 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1334 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1335 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1336 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1337 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1339 // If it's impossible to use [r,r] address mode for sextload, select to
1340 // ldr{b|h} + sxt{b|h} instead.
1341 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1342 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1343 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1344 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1345 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1346 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1347 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1348 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1349 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1350 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1351 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1352 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1354 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1355 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1356 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1357 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1358 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1359 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1360 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1361 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1363 // Large immediate handling.
1366 def : T1Pat<(i32 thumb_immshifted:$src),
1367 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1368 (thumb_immshifted_shamt imm:$src))>;
1370 def : T1Pat<(i32 imm0_255_comp:$src),
1371 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1373 // Pseudo instruction that combines ldr from constpool and add pc. This should
1374 // be expanded into two instructions late to allow if-conversion and
1376 let isReMaterializable = 1 in
1377 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1379 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1381 Requires<[IsThumb, IsThumb1Only]>;
1383 // Pseudo-instruction for merged POP and return.
1384 // FIXME: remove when we have a way to marking a MI with these properties.
1385 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1386 hasExtraDefRegAllocReq = 1 in
1387 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1389 (tPOP pred:$p, reglist:$regs)>;
1391 // Indirect branch using "mov pc, $Rm"
1392 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1393 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1394 2, IIC_Br, [(brind GPR:$Rm)],
1395 (tMOVr PC, GPR:$Rm, pred:$p)>;
1399 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1400 // encoding is available on ARMv6K, but we don't differentiate that finely.
1401 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;