1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, "",
130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
131 Requires<[IsThumb, IsThumb1Only]>;
133 def tADJCALLSTACKDOWN :
134 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, "",
135 [(ARMcallseq_start imm:$amt)]>,
136 Requires<[IsThumb, IsThumb1Only]>;
139 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
140 [/* For disassembly only; pattern left blank */]>,
141 T1Encoding<0b101111> {
142 let Inst{9-8} = 0b11;
143 let Inst{7-0} = 0b00000000;
146 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
147 [/* For disassembly only; pattern left blank */]>,
148 T1Encoding<0b101111> {
149 let Inst{9-8} = 0b11;
150 let Inst{7-0} = 0b00010000;
153 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
154 [/* For disassembly only; pattern left blank */]>,
155 T1Encoding<0b101111> {
156 let Inst{9-8} = 0b11;
157 let Inst{7-0} = 0b00100000;
160 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
161 [/* For disassembly only; pattern left blank */]>,
162 T1Encoding<0b101111> {
163 let Inst{9-8} = 0b11;
164 let Inst{7-0} = 0b00110000;
167 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
168 [/* For disassembly only; pattern left blank */]>,
169 T1Encoding<0b101111> {
170 let Inst{9-8} = 0b11;
171 let Inst{7-0} = 0b01000000;
174 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
175 [/* For disassembly only; pattern left blank */]>,
176 T1Encoding<0b101101> {
177 let Inst{9-5} = 0b10010;
181 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
182 [/* For disassembly only; pattern left blank */]>,
183 T1Encoding<0b101101> {
184 let Inst{9-5} = 0b10010;
188 // The i32imm operand $val can be used by a debugger to store more information
189 // about the breakpoint.
190 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
191 [/* For disassembly only; pattern left blank */]>,
192 T1Encoding<0b101111> {
193 let Inst{9-8} = 0b10;
196 // Change Processor State is a system instruction -- for disassembly only.
197 // The singleton $opt operand contains the following information:
198 // opt{4-0} = mode ==> don't care
199 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
200 // opt{8-6} = AIF from Inst{2-0}
201 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
203 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
204 // CPS which has more options.
205 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
206 [/* For disassembly only; pattern left blank */]>,
209 // For both thumb1 and thumb2.
210 let isNotDuplicable = 1, isCodeGenOnly = 1 in
211 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
212 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
213 T1Special<{0,0,?,?}> {
214 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc
218 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
219 "add\t$dst, pc, $rhs", []>,
220 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
223 // This is rematerializable, which is particularly useful for taking the
224 // address of locals.
225 let isReMaterializable = 1 in {
226 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
227 "add\t$dst, $sp, $rhs", []>,
228 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8
232 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
233 "add\t$dst, $rhs", []>,
234 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8
237 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
238 "sub\t$dst, $rhs", []>,
239 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215
242 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
243 "add\t$dst, $rhs", []>,
244 T1Special<{0,0,?,?}> {
245 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1
249 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
250 "add\t$dst, $rhs", []>,
251 T1Special<{0,0,?,?}> {
252 // A8.6.9 Encoding T2
254 let Inst{2-0} = 0b101;
257 //===----------------------------------------------------------------------===//
258 // Control Flow Instructions.
261 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
262 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>,
263 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
264 let Inst{6-3} = 0b1110; // Rm = lr
266 // Alternative return instruction used by vararg functions.
267 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>,
268 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25
272 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
273 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst",
275 T1Special<{1,0,1,?}> {
276 // <Rd> = Inst{7:2-0} = pc
277 let Inst{2-0} = 0b111;
281 // FIXME: remove when we have a way to marking a MI with these properties.
282 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
283 hasExtraDefRegAllocReq = 1 in
284 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops),
286 "pop${p}\t$dsts", []>,
287 T1Misc<{1,1,0,?,?,?,?}>;
290 Defs = [R0, R1, R2, R3, R12, LR,
291 D0, D1, D2, D3, D4, D5, D6, D7,
292 D16, D17, D18, D19, D20, D21, D22, D23,
293 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
294 // Also used for Thumb2
295 def tBL : TIx2<0b11110, 0b11, 1,
296 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
298 [(ARMtcall tglobaladdr:$func)]>,
299 Requires<[IsThumb, IsNotDarwin]>;
301 // ARMv5T and above, also used for Thumb2
302 def tBLXi : TIx2<0b11110, 0b11, 0,
303 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
305 [(ARMcall tglobaladdr:$func)]>,
306 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
308 // Also used for Thumb2
309 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
311 [(ARMtcall GPR:$func)]>,
312 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
313 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
316 let isCodeGenOnly = 1 in
317 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
318 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
319 "mov\tlr, pc\n\tbx\t$func",
320 [(ARMcall_nolink tGPR:$func)]>,
321 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
324 // On Darwin R9 is call-clobbered.
326 Defs = [R0, R1, R2, R3, R9, R12, LR,
327 D0, D1, D2, D3, D4, D5, D6, D7,
328 D16, D17, D18, D19, D20, D21, D22, D23,
329 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
330 // Also used for Thumb2
331 def tBLr9 : TIx2<0b11110, 0b11, 1,
332 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
334 [(ARMtcall tglobaladdr:$func)]>,
335 Requires<[IsThumb, IsDarwin]>;
337 // ARMv5T and above, also used for Thumb2
338 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
339 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
341 [(ARMcall tglobaladdr:$func)]>,
342 Requires<[IsThumb, HasV5T, IsDarwin]>;
344 // Also used for Thumb2
345 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
347 [(ARMtcall GPR:$func)]>,
348 Requires<[IsThumb, HasV5T, IsDarwin]>,
349 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
352 let isCodeGenOnly = 1 in
353 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
354 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
355 "mov\tlr, pc\n\tbx\t$func",
356 [(ARMcall_nolink tGPR:$func)]>,
357 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
360 let isBranch = 1, isTerminator = 1 in {
361 let isBarrier = 1 in {
362 let isPredicable = 1 in
363 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
364 "b\t$target", [(br bb:$target)]>,
365 T1Encoding<{1,1,1,0,0,?}>;
369 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
372 let isCodeGenOnly = 1 in
373 def tBR_JTr : T1JTI<(outs),
374 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
375 IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
376 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
378 let Inst{15-7} = 0b010001101;
379 let Inst{2-0} = 0b111;
384 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
385 // a two-value operand where a dag node expects two operands. :(
386 let isBranch = 1, isTerminator = 1 in
387 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
389 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
390 T1Encoding<{1,1,0,1,?,?}>;
392 // Compare and branch on zero / non-zero
393 let isBranch = 1, isTerminator = 1 in {
394 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
395 "cbz\t$cmp, $target", []>,
396 T1Misc<{0,0,?,1,?,?,?}>;
398 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
399 "cbnz\t$cmp, $target", []>,
400 T1Misc<{1,0,?,1,?,?,?}>;
403 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
404 // A8.6.16 B: Encoding T1
405 // If Inst{11-8} == 0b1111 then SEE SVC
407 def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>,
409 let Inst{15-12} = 0b1101;
410 let Inst{11-8} = 0b1111;
414 // A8.6.16 B: Encoding T1
415 // If Inst{11-8} == 0b1110 then UNDEFINED
416 let isBarrier = 1, isTerminator = 1 in
417 def tTRAP : TI<(outs), (ins), IIC_Br,
418 "trap", [(trap)]>, Encoding16 {
419 let Inst{15-12} = 0b1101;
420 let Inst{11-8} = 0b1110;
423 //===----------------------------------------------------------------------===//
424 // Load Store Instructions.
427 let canFoldAsLoad = 1, isReMaterializable = 1 in
428 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
429 "ldr", "\t$dst, $addr",
430 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>,
432 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
433 "ldr", "\t$dst, $addr",
437 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
438 "ldrb", "\t$dst, $addr",
439 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
441 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
442 "ldrb", "\t$dst, $addr",
446 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
447 "ldrh", "\t$dst, $addr",
448 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
450 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
451 "ldrh", "\t$dst, $addr",
455 let AddedComplexity = 10 in
456 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
457 "ldrsb", "\t$dst, $addr",
458 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
461 let AddedComplexity = 10 in
462 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
463 "ldrsh", "\t$dst, $addr",
464 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
467 let canFoldAsLoad = 1 in
468 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
469 "ldr", "\t$dst, $addr",
470 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
473 // Special instruction for restore. It cannot clobber condition register
474 // when it's expanded by eliminateCallFramePseudoInstr().
475 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
476 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
477 "ldr", "\t$dst, $addr", []>,
481 // FIXME: Use ldr.n to work around a Darwin assembler bug.
482 let canFoldAsLoad = 1, isReMaterializable = 1 in
483 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
484 "ldr", ".n\t$dst, $addr",
485 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
486 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
488 // Special LDR for loads from non-pc-relative constpools.
489 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
490 isReMaterializable = 1 in
491 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
492 "ldr", "\t$dst, $addr", []>,
495 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
496 "str", "\t$src, $addr",
497 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
499 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
500 "str", "\t$src, $addr",
504 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
505 "strb", "\t$src, $addr",
506 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
508 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
509 "strb", "\t$src, $addr",
513 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
514 "strh", "\t$src, $addr",
515 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
517 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
518 "strh", "\t$src, $addr",
522 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
523 "str", "\t$src, $addr",
524 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
527 let mayStore = 1, neverHasSideEffects = 1 in {
528 // Special instruction for spill. It cannot clobber condition register
529 // when it's expanded by eliminateCallFramePseudoInstr().
530 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
531 "str", "\t$src, $addr", []>,
535 //===----------------------------------------------------------------------===//
536 // Load / store multiple Instructions.
539 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
540 InstrItinClass itin_upd, bits<6> T1Enc,
543 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
544 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
547 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
548 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
552 // These require base address to be written back or one of the loaded regs.
553 let neverHasSideEffects = 1 in {
555 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
556 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
559 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
560 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
563 } // neverHasSideEffects
565 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
566 def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops),
568 "pop${p}\t$dsts", []>,
569 T1Misc<{1,1,0,?,?,?,?}>;
571 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
572 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops),
574 "push${p}\t$srcs", []>,
575 T1Misc<{0,1,0,?,?,?,?}>;
577 //===----------------------------------------------------------------------===//
578 // Arithmetic Instructions.
581 // Add with carry register
582 let isCommutable = 1, Uses = [CPSR] in
583 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
584 "adc", "\t$dst, $rhs",
585 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
586 T1DataProcessing<0b0101>;
589 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
590 "add", "\t$dst, $lhs, $rhs",
591 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>,
594 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
595 "add", "\t$dst, $rhs",
596 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
597 T1General<{1,1,0,?,?}>;
600 let isCommutable = 1 in
601 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
602 "add", "\t$dst, $lhs, $rhs",
603 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>,
606 let neverHasSideEffects = 1 in
607 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
608 "add", "\t$dst, $rhs", []>,
609 T1Special<{0,0,?,?}>;
612 let isCommutable = 1 in
613 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
614 "and", "\t$dst, $rhs",
615 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
616 T1DataProcessing<0b0000>;
619 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
620 "asr", "\t$dst, $lhs, $rhs",
621 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>,
622 T1General<{0,1,0,?,?}>;
625 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
626 "asr", "\t$dst, $rhs",
627 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
628 T1DataProcessing<0b0100>;
631 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
632 "bic", "\t$dst, $rhs",
633 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
634 T1DataProcessing<0b1110>;
637 let isCompare = 1, Defs = [CPSR] in {
638 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
639 // Compare-to-zero still works out, just not the relationals
640 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
641 // "cmn", "\t$lhs, $rhs",
642 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
643 // T1DataProcessing<0b1011>;
644 def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
645 "cmn", "\t$lhs, $rhs",
646 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>,
647 T1DataProcessing<0b1011>;
651 let isCompare = 1, Defs = [CPSR] in {
652 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
653 "cmp", "\t$lhs, $rhs",
654 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>,
655 T1General<{1,0,1,?,?}>;
656 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
657 "cmp", "\t$lhs, $rhs",
658 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>,
659 T1General<{1,0,1,?,?}>;
663 let isCompare = 1, Defs = [CPSR] in {
664 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
665 "cmp", "\t$lhs, $rhs",
666 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>,
667 T1DataProcessing<0b1010>;
668 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
669 "cmp", "\t$lhs, $rhs",
670 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
671 T1DataProcessing<0b1010>;
673 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
674 "cmp", "\t$lhs, $rhs", []>,
675 T1Special<{0,1,?,?}>;
676 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
677 "cmp", "\t$lhs, $rhs", []>,
678 T1Special<{0,1,?,?}>;
683 let isCommutable = 1 in
684 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
685 "eor", "\t$dst, $rhs",
686 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
687 T1DataProcessing<0b0001>;
690 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
691 "lsl", "\t$dst, $lhs, $rhs",
692 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
693 T1General<{0,0,0,?,?}>;
696 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
697 "lsl", "\t$dst, $rhs",
698 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
699 T1DataProcessing<0b0010>;
702 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
703 "lsr", "\t$dst, $lhs, $rhs",
704 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
705 T1General<{0,0,1,?,?}>;
708 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
709 "lsr", "\t$dst, $rhs",
710 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
711 T1DataProcessing<0b0011>;
714 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
715 "mov", "\t$dst, $src",
716 [(set tGPR:$dst, imm0_255:$src)]>,
717 T1General<{1,0,0,?,?}>;
719 // TODO: A7-73: MOV(2) - mov setting flag.
722 let neverHasSideEffects = 1 in {
723 // FIXME: Make this predicable.
724 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
725 "mov\t$dst, $src", []>,
728 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
729 "movs\t$dst, $src", []>, Encoding16 {
730 let Inst{15-6} = 0b0000000000;
733 // FIXME: Make these predicable.
734 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
735 "mov\t$dst, $src", []>,
736 T1Special<{1,0,0,?}>;
737 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
738 "mov\t$dst, $src", []>,
739 T1Special<{1,0,?,0}>;
740 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
741 "mov\t$dst, $src", []>,
742 T1Special<{1,0,?,?}>;
743 } // neverHasSideEffects
746 let isCommutable = 1 in
747 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
748 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
749 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
750 T1DataProcessing<0b1101>;
752 // move inverse register
753 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMVNr,
754 "mvn", "\t$dst, $src",
755 [(set tGPR:$dst, (not tGPR:$src))]>,
756 T1DataProcessing<0b1111>;
758 // bitwise or register
759 let isCommutable = 1 in
760 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
761 "orr", "\t$dst, $rhs",
762 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
763 T1DataProcessing<0b1100>;
766 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
767 "rev", "\t$dst, $src",
768 [(set tGPR:$dst, (bswap tGPR:$src))]>,
769 Requires<[IsThumb, IsThumb1Only, HasV6]>,
770 T1Misc<{1,0,1,0,0,0,?}>;
772 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
773 "rev16", "\t$dst, $src",
775 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
776 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
777 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
778 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
779 Requires<[IsThumb, IsThumb1Only, HasV6]>,
780 T1Misc<{1,0,1,0,0,1,?}>;
782 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
783 "revsh", "\t$dst, $src",
786 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
787 (shl tGPR:$src, (i32 8))), i16))]>,
788 Requires<[IsThumb, IsThumb1Only, HasV6]>,
789 T1Misc<{1,0,1,0,1,1,?}>;
791 // rotate right register
792 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
793 "ror", "\t$dst, $rhs",
794 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
795 T1DataProcessing<0b0111>;
798 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
799 "rsb", "\t$dst, $src, #0",
800 [(set tGPR:$dst, (ineg tGPR:$src))]>,
801 T1DataProcessing<0b1001>;
803 // Subtract with carry register
805 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
806 "sbc", "\t$dst, $rhs",
807 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
808 T1DataProcessing<0b0110>;
810 // Subtract immediate
811 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
812 "sub", "\t$dst, $lhs, $rhs",
813 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
816 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
817 "sub", "\t$dst, $rhs",
818 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
819 T1General<{1,1,1,?,?}>;
822 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
823 "sub", "\t$dst, $lhs, $rhs",
824 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
827 // TODO: A7-96: STMIA - store multiple.
830 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
831 "sxtb", "\t$dst, $src",
832 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
833 Requires<[IsThumb, IsThumb1Only, HasV6]>,
834 T1Misc<{0,0,1,0,0,1,?}>;
837 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
838 "sxth", "\t$dst, $src",
839 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
840 Requires<[IsThumb, IsThumb1Only, HasV6]>,
841 T1Misc<{0,0,1,0,0,0,?}>;
844 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
845 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iTSTr,
846 "tst", "\t$lhs, $rhs",
847 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>,
848 T1DataProcessing<0b1000>;
851 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
852 "uxtb", "\t$dst, $src",
853 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
854 Requires<[IsThumb, IsThumb1Only, HasV6]>,
855 T1Misc<{0,0,1,0,1,1,?}>;
858 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
859 "uxth", "\t$dst, $src",
860 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
861 Requires<[IsThumb, IsThumb1Only, HasV6]>,
862 T1Misc<{0,0,1,0,1,0,?}>;
865 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
866 // Expanded after instruction selection into a branch sequence.
867 let usesCustomInserter = 1 in // Expanded after instruction selection.
869 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
871 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
874 // 16-bit movcc in IT blocks for Thumb2.
875 let neverHasSideEffects = 1 in {
876 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
877 "mov", "\t$dst, $rhs", []>,
878 T1Special<{1,0,?,?}>;
880 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
881 "mov", "\t$dst, $rhs", []>,
882 T1General<{1,0,0,?,?}>;
883 } // neverHasSideEffects
885 // tLEApcrel - Load a pc-relative address into a register without offending the
887 let neverHasSideEffects = 1 in {
888 let isReMaterializable = 1 in
889 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
890 "adr$p\t$dst, #$label", []>,
891 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
893 } // neverHasSideEffects
894 def tLEApcrelJT : T1I<(outs tGPR:$dst),
895 (ins i32imm:$label, nohash_imm:$id, pred:$p),
896 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
897 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
899 //===----------------------------------------------------------------------===//
903 // __aeabi_read_tp preserves the registers r1-r3.
906 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
907 "bl\t__aeabi_read_tp",
908 [(set R0, ARMthread_pointer)]>;
911 // SJLJ Exception handling intrinsics
912 // eh_sjlj_setjmp() is an instruction sequence to store the return
913 // address and save #0 in R0 for the non-longjmp case.
914 // Since by its nature we may be coming from some other function to get
915 // here, and we're using the stack frame for the containing function to
916 // save/restore registers, we can't keep anything live in regs across
917 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
918 // when we get here from a longjmp(). We force everthing out of registers
919 // except for our own input by listing the relevant registers in Defs. By
920 // doing so, we also cause the prologue/epilogue code to actively preserve
921 // all of the callee-saved resgisters, which is exactly what we want.
922 // $val is a scratch register for our use.
924 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
925 isBarrier = 1, isCodeGenOnly = 1 in {
926 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
927 AddrModeNone, SizeSpecial, NoItinerary, "", "",
928 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
931 // FIXME: Non-Darwin version(s)
932 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
933 Defs = [ R7, LR, SP ] in {
934 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
935 AddrModeNone, SizeSpecial, IndexModeNone,
936 Pseudo, NoItinerary, "", "",
937 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
938 Requires<[IsThumb, IsDarwin]>;
941 //===----------------------------------------------------------------------===//
942 // Non-Instruction Patterns
946 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
947 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
948 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
949 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
950 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
951 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
953 // Subtract with carry
954 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
955 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
956 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
957 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
958 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
959 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
961 // ConstantPool, GlobalAddress
962 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
963 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
966 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
967 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
970 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
971 Requires<[IsThumb, IsNotDarwin]>;
972 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
973 Requires<[IsThumb, IsDarwin]>;
975 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
976 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
977 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
978 Requires<[IsThumb, HasV5T, IsDarwin]>;
980 // Indirect calls to ARM routines
981 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
982 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
983 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
984 Requires<[IsThumb, HasV5T, IsDarwin]>;
986 // zextload i1 -> zextload i8
987 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
988 (tLDRB t_addrmode_s1:$addr)>;
990 // extload -> zextload
991 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
992 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
993 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
995 // If it's impossible to use [r,r] address mode for sextload, select to
996 // ldr{b|h} + sxt{b|h} instead.
997 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
998 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
999 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1000 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1001 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1002 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1004 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1005 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1006 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1007 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1009 // Large immediate handling.
1012 def : T1Pat<(i32 thumb_immshifted:$src),
1013 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1014 (thumb_immshifted_shamt imm:$src))>;
1016 def : T1Pat<(i32 imm0_255_comp:$src),
1017 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1019 // Pseudo instruction that combines ldr from constpool and add pc. This should
1020 // be expanded into two instructions late to allow if-conversion and
1022 let isReMaterializable = 1 in
1023 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1025 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1027 Requires<[IsThumb, IsThumb1Only]>;