1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
30 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
31 def imm0_7 : PatLeaf<(i32 imm), [{
32 return (uint32_t)N->getZExtValue() < 8;
34 def imm0_7_neg : PatLeaf<(i32 imm), [{
35 return (uint32_t)-N->getZExtValue() < 8;
38 def imm0_255 : PatLeaf<(i32 imm), [{
39 return (uint32_t)N->getZExtValue() < 256;
41 def imm0_255_comp : PatLeaf<(i32 imm), [{
42 return ~((uint32_t)N->getZExtValue()) < 256;
45 def imm8_255 : PatLeaf<(i32 imm), [{
46 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
48 def imm8_255_neg : PatLeaf<(i32 imm), [{
49 unsigned Val = -N->getZExtValue();
50 return Val >= 8 && Val < 256;
53 // Break imm's up into two pieces: an immediate + a left shift.
54 // This uses thumb_immshifted to match and thumb_immshifted_val and
55 // thumb_immshifted_shamt to get the val/shift pieces.
56 def thumb_immshifted : PatLeaf<(imm), [{
57 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
60 def thumb_immshifted_val : SDNodeXForm<imm, [{
61 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
62 return CurDAG->getTargetConstant(V, MVT::i32);
65 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 // Scaled 4 immediate.
71 def t_imm_s4 : Operand<i32> {
72 let PrintMethod = "printThumbS4ImmOperand";
75 // Define Thumb specific addressing modes.
77 // t_addrmode_rr := reg + reg
79 def t_addrmode_rr : Operand<i32>,
80 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
81 let PrintMethod = "printThumbAddrModeRROperand";
82 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
85 // t_addrmode_s4 := reg + reg
88 def t_addrmode_s4 : Operand<i32>,
89 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
90 let PrintMethod = "printThumbAddrModeS4Operand";
91 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
94 // t_addrmode_s2 := reg + reg
97 def t_addrmode_s2 : Operand<i32>,
98 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
99 let PrintMethod = "printThumbAddrModeS2Operand";
100 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
103 // t_addrmode_s1 := reg + reg
106 def t_addrmode_s1 : Operand<i32>,
107 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
108 let PrintMethod = "printThumbAddrModeS1Operand";
109 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
112 // t_addrmode_sp := sp + imm8 * 4
114 def t_addrmode_sp : Operand<i32>,
115 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
116 let PrintMethod = "printThumbAddrModeSPOperand";
117 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
120 //===----------------------------------------------------------------------===//
121 // Miscellaneous Instructions.
124 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
125 // from removing one half of the matched pairs. That breaks PEI, which assumes
126 // these will always be in pairs, and asserts if it finds otherwise. Better way?
127 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
128 def tADJCALLSTACKUP :
129 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
131 Requires<[IsThumb, IsThumb1Only]>;
133 def tADJCALLSTACKDOWN :
134 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
135 [(ARMcallseq_start imm:$amt)]>,
136 Requires<[IsThumb, IsThumb1Only]>;
139 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
140 [/* For disassembly only; pattern left blank */]>,
141 T1Encoding<0b101111> {
143 let Inst{9-8} = 0b11;
144 let Inst{7-0} = 0x00;
147 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
148 [/* For disassembly only; pattern left blank */]>,
149 T1Encoding<0b101111> {
151 let Inst{9-8} = 0b11;
152 let Inst{7-0} = 0x10;
155 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
156 [/* For disassembly only; pattern left blank */]>,
157 T1Encoding<0b101111> {
159 let Inst{9-8} = 0b11;
160 let Inst{7-0} = 0x20;
163 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
164 [/* For disassembly only; pattern left blank */]>,
165 T1Encoding<0b101111> {
167 let Inst{9-8} = 0b11;
168 let Inst{7-0} = 0x30;
171 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
172 [/* For disassembly only; pattern left blank */]>,
173 T1Encoding<0b101111> {
175 let Inst{9-8} = 0b11;
176 let Inst{7-0} = 0x40;
179 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
180 [/* For disassembly only; pattern left blank */]>,
181 T1Encoding<0b101101> {
183 let Inst{9-5} = 0b10010;
185 let Inst{3} = 1; // Big-Endian
186 let Inst{2-0} = 0b000;
189 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
190 [/* For disassembly only; pattern left blank */]>,
191 T1Encoding<0b101101> {
193 let Inst{9-5} = 0b10010;
195 let Inst{3} = 0; // Little-Endian
196 let Inst{2-0} = 0b000;
199 // The i32imm operand $val can be used by a debugger to store more information
200 // about the breakpoint.
201 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
202 [/* For disassembly only; pattern left blank */]>,
203 T1Encoding<0b101111> {
206 let Inst{9-8} = 0b10;
210 // Change Processor State is a system instruction -- for disassembly only.
211 // The singleton $opt operand contains the following information:
212 // opt{4-0} = mode ==> don't care
213 // opt{5} = changemode ==> 0 (false for 16-bit Thumb instr)
214 // opt{8-6} = AIF from Inst{2-0}
215 // opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable
217 // The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM
218 // CPS which has more options.
219 def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt",
220 [/* For disassembly only; pattern left blank */]>,
221 T1Misc<0b0110011>; // A8.6.38
223 // For both thumb1 and thumb2.
224 let isNotDuplicable = 1, isCodeGenOnly = 1 in
225 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
226 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
227 T1Special<{0,0,?,?}> {
230 let Inst{6-3} = 0b1111;
235 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
236 "add\t$dst, pc, $rhs", []>,
237 T1Encoding<{1,0,1,0,0,?}> {
241 let Inst{10-8} = dst;
245 // ADD <Rd>, sp, #<imm8>
246 // This is rematerializable, which is particularly useful for taking the
247 // address of locals.
248 let isReMaterializable = 1 in
249 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
250 "add\t$dst, $sp, $rhs", []>,
251 T1Encoding<{1,0,1,0,1,?}> {
255 let Inst{10-8} = dst;
259 // ADD sp, sp, #<imm7>
260 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
261 "add\t$dst, $rhs", []>,
262 T1Misc<{0,0,0,0,0,?,?}> {
268 // SUB sp, sp, #<imm7>
269 // FIXME: The encoding and the ASM string don't match up.
270 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
271 "sub\t$dst, $rhs", []>,
272 T1Misc<{0,0,0,0,1,?,?}> {
279 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
280 "add\t$dst, $rhs", []>,
281 T1Special<{0,0,?,?}> {
282 // A8.6.9 Encoding T1
284 let Inst{7} = dst{3};
285 let Inst{6-3} = 0b1101;
286 let Inst{2-0} = dst{2-0};
290 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
291 "add\t$dst, $rhs", []>,
292 T1Special<{0,0,?,?}> {
293 // A8.6.9 Encoding T2
297 let Inst{2-0} = 0b101;
300 //===----------------------------------------------------------------------===//
301 // Control Flow Instructions.
304 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
305 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
307 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
308 let Inst{6-3} = 0b1110; // Rm = lr
309 let Inst{2-0} = 0b000;
312 // Alternative return instruction used by vararg functions.
313 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
316 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25
319 let Inst{2-0} = 0b000;
324 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
325 def tBRIND : TI<(outs), (ins GPR:$Rm), IIC_Br, "mov\tpc, $Rm",
327 T1Special<{1,0,?,?}> {
330 let Inst{7} = 0b1; // <Rd> = Inst{7:2-0} = pc
331 let Inst{2-0} = 0b111;
335 // FIXME: remove when we have a way to marking a MI with these properties.
336 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
337 hasExtraDefRegAllocReq = 1 in
338 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
340 "pop${p}\t$regs", []>,
341 T1Misc<{1,1,0,?,?,?,?}> {
343 let Inst{8} = regs{15};
344 let Inst{7-0} = regs{7-0};
348 Defs = [R0, R1, R2, R3, R12, LR,
349 D0, D1, D2, D3, D4, D5, D6, D7,
350 D16, D17, D18, D19, D20, D21, D22, D23,
351 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
352 // Also used for Thumb2
353 def tBL : TIx2<0b11110, 0b11, 1,
354 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
356 [(ARMtcall tglobaladdr:$func)]>,
357 Requires<[IsThumb, IsNotDarwin]>;
359 // ARMv5T and above, also used for Thumb2
360 def tBLXi : TIx2<0b11110, 0b11, 0,
361 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
363 [(ARMcall tglobaladdr:$func)]>,
364 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
366 // Also used for Thumb2
367 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
369 [(ARMtcall GPR:$func)]>,
370 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
371 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24;
374 let isCodeGenOnly = 1 in
375 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?,
376 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
377 "mov\tlr, pc\n\tbx\t$func",
378 [(ARMcall_nolink tGPR:$func)]>,
379 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
382 // On Darwin R9 is call-clobbered.
384 Defs = [R0, R1, R2, R3, R9, R12, LR,
385 D0, D1, D2, D3, D4, D5, D6, D7,
386 D16, D17, D18, D19, D20, D21, D22, D23,
387 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
388 // Also used for Thumb2
389 def tBLr9 : TIx2<0b11110, 0b11, 1,
390 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
392 [(ARMtcall tglobaladdr:$func)]>,
393 Requires<[IsThumb, IsDarwin]>;
395 // ARMv5T and above, also used for Thumb2
396 def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
397 (outs), (ins i32imm:$func, variable_ops), IIC_Br,
399 [(ARMcall tglobaladdr:$func)]>,
400 Requires<[IsThumb, HasV5T, IsDarwin]>;
402 // Also used for Thumb2
403 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
405 [(ARMtcall GPR:$func)]>,
406 Requires<[IsThumb, HasV5T, IsDarwin]>,
407 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24
410 let isCodeGenOnly = 1 in
411 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?,
412 (outs), (ins tGPR:$func, variable_ops), IIC_Br,
413 "mov\tlr, pc\n\tbx\t$func",
414 [(ARMcall_nolink tGPR:$func)]>,
415 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
418 let isBranch = 1, isTerminator = 1 in {
419 let isBarrier = 1 in {
420 let isPredicable = 1 in
421 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
422 "b\t$target", [(br bb:$target)]>,
423 T1Encoding<{1,1,1,0,0,?}>;
427 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br,
430 let isCodeGenOnly = 1 in
431 def tBR_JTr : T1JTI<(outs),
432 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
433 IIC_Br, "mov\tpc, $target\n\t.align\t2$jt",
434 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>,
436 let Inst{15-7} = 0b010001101;
437 let Inst{2-0} = 0b111;
442 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
443 // a two-value operand where a dag node expects two operands. :(
444 let isBranch = 1, isTerminator = 1 in
445 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
447 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
448 T1Encoding<{1,1,0,1,?,?}>;
450 // Compare and branch on zero / non-zero
451 let isBranch = 1, isTerminator = 1 in {
452 def tCBZ : T1I<(outs), (ins tGPR:$Rn, brtarget:$target), IIC_Br,
453 "cbz\t$Rn, $target", []>,
454 T1Misc<{0,0,?,1,?,?,?}> {
457 let Inst{9} = target{5};
458 let Inst{7-3} = target{4-0};
462 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br,
463 "cbnz\t$cmp, $target", []>,
464 T1Misc<{1,0,?,1,?,?,?}> {
467 let Inst{9} = target{5};
468 let Inst{7-3} = target{4-0};
473 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
474 // A8.6.16 B: Encoding T1
475 // If Inst{11-8} == 0b1111 then SEE SVC
477 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
478 "svc", "\t$imm", []>, Encoding16 {
480 let Inst{15-12} = 0b1101;
481 let Inst{11-8} = 0b1111;
485 // A8.6.16 B: Encoding T1
486 // If Inst{11-8} == 0b1110 then UNDEFINED
487 let isBarrier = 1, isTerminator = 1 in
488 def tTRAP : TI<(outs), (ins), IIC_Br,
489 "trap", [(trap)]>, Encoding16 {
493 //===----------------------------------------------------------------------===//
494 // Load Store Instructions.
497 let canFoldAsLoad = 1, isReMaterializable = 1 in
498 def tLDR : T1pI4<(outs tGPR:$Rt), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
499 "ldr", "\t$Rt, $addr",
500 [(set tGPR:$Rt, (load t_addrmode_s4:$addr))]>,
503 def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoad_r,
504 "ldr", "\t$dst, $addr",
508 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
509 "ldrb", "\t$dst, $addr",
510 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>,
512 def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoad_bh_r,
513 "ldrb", "\t$dst, $addr",
517 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
518 "ldrh", "\t$dst, $addr",
519 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>,
521 def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoad_bh_r,
522 "ldrh", "\t$dst, $addr",
526 let AddedComplexity = 10 in
527 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
528 "ldrsb", "\t$dst, $addr",
529 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>,
532 let AddedComplexity = 10 in
533 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoad_bh_r,
534 "ldrsh", "\t$dst, $addr",
535 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>,
538 let canFoldAsLoad = 1 in
539 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
540 "ldr", "\t$dst, $addr",
541 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>,
544 // Special instruction for restore. It cannot clobber condition register
545 // when it's expanded by eliminateCallFramePseudoInstr().
546 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
547 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
548 "ldr", "\t$dst, $addr", []>,
552 // FIXME: Use ldr.n to work around a Darwin assembler bug.
553 let canFoldAsLoad = 1, isReMaterializable = 1 in
554 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
555 "ldr", ".n\t$dst, $addr",
556 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>,
557 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59
559 // Special LDR for loads from non-pc-relative constpools.
560 let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1,
561 isReMaterializable = 1 in
562 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoad_i,
563 "ldr", "\t$dst, $addr", []>,
566 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
567 "str", "\t$src, $addr",
568 [(store tGPR:$src, t_addrmode_s4:$addr)]>,
570 def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStore_r,
571 "str", "\t$src, $addr",
575 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
576 "strb", "\t$src, $addr",
577 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>,
579 def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStore_bh_r,
580 "strb", "\t$src, $addr",
584 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
585 "strh", "\t$src, $addr",
586 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>,
588 def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStore_bh_r,
589 "strh", "\t$src, $addr",
593 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
594 "str", "\t$src, $addr",
595 [(store tGPR:$src, t_addrmode_sp:$addr)]>,
598 let mayStore = 1, neverHasSideEffects = 1 in {
599 // Special instruction for spill. It cannot clobber condition register
600 // when it's expanded by eliminateCallFramePseudoInstr().
601 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
602 "str", "\t$src, $addr", []>,
606 //===----------------------------------------------------------------------===//
607 // Load / store multiple Instructions.
610 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
611 InstrItinClass itin_upd, bits<6> T1Enc,
614 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
615 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
620 let Inst{7-0} = regs;
623 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
624 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
629 let Inst{7-0} = regs;
633 // These require base address to be written back or one of the loaded regs.
634 let neverHasSideEffects = 1 in {
636 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
637 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
640 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
641 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
644 } // neverHasSideEffects
646 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
647 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
649 "pop${p}\t$regs", []>,
650 T1Misc<{1,1,0,?,?,?,?}> {
652 let Inst{8} = regs{15};
653 let Inst{7-0} = regs{7-0};
656 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
657 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
659 "push${p}\t$regs", []>,
660 T1Misc<{0,1,0,?,?,?,?}> {
662 let Inst{8} = regs{14};
663 let Inst{7-0} = regs{7-0};
666 //===----------------------------------------------------------------------===//
667 // Arithmetic Instructions.
670 // Add with carry register
671 let isCommutable = 1, Uses = [CPSR] in
672 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
673 "adc", "\t$dst, $rhs",
674 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>,
675 T1DataProcessing<0b0101> {
684 def tADDi3 : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, i32imm:$imm3), IIC_iALUi,
685 "add", "\t$Rd, $Rn, $imm3",
686 [(set tGPR:$Rd, (add tGPR:$Rn, imm0_7:$imm3))]>,
692 let Inst{8-6} = imm3;
697 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
698 "add", "\t$dst, $rhs",
699 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>,
700 T1General<{1,1,0,?,?}> {
704 let Inst{10-8} = lhs;
709 let isCommutable = 1 in
710 def tADDrr : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
711 "add", "\t$Rd, $Rn, $Rm",
712 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>,
723 let neverHasSideEffects = 1 in
724 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
725 "add", "\t$dst, $rhs", []>,
726 T1Special<{0,0,?,?}> {
731 let Inst{7} = dst{3};
732 let Inst{2-0} = dst{2-0};
736 let isCommutable = 1 in
737 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
738 "and", "\t$dst, $rhs",
739 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>,
740 T1DataProcessing<0b0000> {
749 def tASRri : T1sI<(outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), IIC_iMOVsi,
750 "asr", "\t$Rd, $Rm, $imm5",
751 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]>,
752 T1General<{0,1,0,?,?}> {
757 let Inst{10-6} = imm5;
763 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
764 "asr", "\t$dst, $rhs",
765 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>,
766 T1DataProcessing<0b0100> {
775 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
776 "bic", "\t$dst, $rhs",
777 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>,
778 T1DataProcessing<0b1110> {
787 let isCompare = 1, Defs = [CPSR] in {
788 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
789 // Compare-to-zero still works out, just not the relationals
790 //def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
791 // "cmn", "\t$lhs, $rhs",
792 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>,
793 // T1DataProcessing<0b1011>;
794 def tCMNz : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
796 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>,
797 T1DataProcessing<0b1011> {
807 let isCompare = 1, Defs = [CPSR] in {
808 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
809 "cmp", "\t$Rn, $imm8",
810 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
811 T1General<{1,0,1,?,?}> {
816 let Inst{7-0} = imm8;
819 def tCMPzi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
820 "cmp", "\t$Rn, $imm8",
821 [(ARMcmpZ tGPR:$Rn, imm0_255:$imm8)]>,
822 T1General<{1,0,1,?,?}> {
826 let Inst{7-0} = 0x00;
830 def tCMPr : T1pI<(outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iCMPr,
832 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>,
833 T1DataProcessing<0b1010> {
841 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
842 "cmp", "\t$lhs, $rhs",
843 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>,
844 T1DataProcessing<0b1010>;
846 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
847 "cmp", "\t$lhs, $rhs", []>,
848 T1Special<{0,1,?,?}>;
849 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
850 "cmp", "\t$lhs, $rhs", []>,
851 T1Special<{0,1,?,?}>;
852 } // isCompare = 1, Defs = [CPSR]
856 let isCommutable = 1 in
857 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
858 "eor", "\t$dst, $rhs",
859 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>,
860 T1DataProcessing<0b0001>;
863 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
864 "lsl", "\t$dst, $lhs, $rhs",
865 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>,
866 T1General<{0,0,0,?,?}>;
869 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
870 "lsl", "\t$dst, $rhs",
871 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>,
872 T1DataProcessing<0b0010>;
875 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
876 "lsr", "\t$dst, $lhs, $rhs",
877 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>,
878 T1General<{0,0,1,?,?}>;
881 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
882 "lsr", "\t$dst, $rhs",
883 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>,
884 T1DataProcessing<0b0011>;
888 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
889 "mov", "\t$dst, $src",
890 [(set tGPR:$dst, imm0_255:$src)]>,
891 T1General<{1,0,0,?,?}>;
893 // TODO: A7-73: MOV(2) - mov setting flag.
896 let neverHasSideEffects = 1 in {
897 // FIXME: Make this predicable.
898 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
899 "mov\t$dst, $src", []>,
902 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
903 "movs\t$dst, $src", []>, Encoding16 {
904 let Inst{15-6} = 0b0000000000;
907 // FIXME: Make these predicable.
908 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
909 "mov\t$dst, $src", []>,
910 T1Special<{1,0,0,?}>;
911 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
912 "mov\t$dst, $src", []>,
913 T1Special<{1,0,?,0}>;
914 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
915 "mov\t$dst, $src", []>,
916 T1Special<{1,0,?,?}>;
917 } // neverHasSideEffects
920 let isCommutable = 1 in
921 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
922 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */
923 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>,
924 T1DataProcessing<0b1101>;
926 // move inverse register
927 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMVNr,
928 "mvn", "\t$dst, $src",
929 [(set tGPR:$dst, (not tGPR:$src))]>,
930 T1DataProcessing<0b1111>;
932 // bitwise or register
933 let isCommutable = 1 in
934 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iBITr,
935 "orr", "\t$dst, $rhs",
936 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>,
937 T1DataProcessing<0b1100>;
940 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
941 "rev", "\t$dst, $src",
942 [(set tGPR:$dst, (bswap tGPR:$src))]>,
943 Requires<[IsThumb, IsThumb1Only, HasV6]>,
944 T1Misc<{1,0,1,0,0,0,?}>;
946 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
947 "rev16", "\t$dst, $src",
949 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
950 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
951 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
952 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
953 Requires<[IsThumb, IsThumb1Only, HasV6]>,
954 T1Misc<{1,0,1,0,0,1,?}>;
956 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
957 "revsh", "\t$dst, $src",
960 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
961 (shl tGPR:$src, (i32 8))), i16))]>,
962 Requires<[IsThumb, IsThumb1Only, HasV6]>,
963 T1Misc<{1,0,1,0,1,1,?}>;
965 // rotate right register
966 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
967 "ror", "\t$dst, $rhs",
968 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>,
969 T1DataProcessing<0b0111>;
972 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
973 "rsb", "\t$dst, $src, #0",
974 [(set tGPR:$dst, (ineg tGPR:$src))]>,
975 T1DataProcessing<0b1001>;
977 // Subtract with carry register
979 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
980 "sbc", "\t$dst, $rhs",
981 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>,
982 T1DataProcessing<0b0110>;
984 // Subtract immediate
985 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
986 "sub", "\t$dst, $lhs, $rhs",
987 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>,
990 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
991 "sub", "\t$dst, $rhs",
992 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>,
993 T1General<{1,1,1,?,?}>;
996 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
997 "sub", "\t$dst, $lhs, $rhs",
998 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>,
1001 // TODO: A7-96: STMIA - store multiple.
1004 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
1005 "sxtb", "\t$dst, $src",
1006 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
1007 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1008 T1Misc<{0,0,1,0,0,1,?}>;
1010 // sign-extend short
1011 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
1012 "sxth", "\t$dst, $src",
1013 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
1014 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1015 T1Misc<{0,0,1,0,0,0,?}>;
1018 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1019 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iTSTr,
1020 "tst", "\t$lhs, $rhs",
1021 [(ARMcmpZ (and_su tGPR:$lhs, tGPR:$rhs), 0)]>,
1022 T1DataProcessing<0b1000>;
1025 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
1026 "uxtb", "\t$dst, $src",
1027 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
1028 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1029 T1Misc<{0,0,1,0,1,1,?}>;
1031 // zero-extend short
1032 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
1033 "uxth", "\t$dst, $src",
1034 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
1035 Requires<[IsThumb, IsThumb1Only, HasV6]>,
1036 T1Misc<{0,0,1,0,1,0,?}>;
1039 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1040 // Expanded after instruction selection into a branch sequence.
1041 let usesCustomInserter = 1 in // Expanded after instruction selection.
1042 def tMOVCCr_pseudo :
1043 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1045 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1048 // 16-bit movcc in IT blocks for Thumb2.
1049 let neverHasSideEffects = 1 in {
1050 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
1051 "mov", "\t$dst, $rhs", []>,
1052 T1Special<{1,0,?,?}>;
1054 let isMoveImm = 1 in
1055 def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
1056 "mov", "\t$dst, $rhs", []>,
1057 T1General<{1,0,0,?,?}>;
1058 } // neverHasSideEffects
1060 // tLEApcrel - Load a pc-relative address into a register without offending the
1062 let neverHasSideEffects = 1 in {
1063 let isReMaterializable = 1 in
1064 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
1065 "adr$p\t$dst, #$label", []>,
1066 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
1068 } // neverHasSideEffects
1069 def tLEApcrelJT : T1I<(outs tGPR:$dst),
1070 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1071 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>,
1072 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10
1074 //===----------------------------------------------------------------------===//
1078 // __aeabi_read_tp preserves the registers r1-r3.
1080 Defs = [R0, LR] in {
1081 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1082 "bl\t__aeabi_read_tp",
1083 [(set R0, ARMthread_pointer)]>;
1086 // SJLJ Exception handling intrinsics
1087 // eh_sjlj_setjmp() is an instruction sequence to store the return
1088 // address and save #0 in R0 for the non-longjmp case.
1089 // Since by its nature we may be coming from some other function to get
1090 // here, and we're using the stack frame for the containing function to
1091 // save/restore registers, we can't keep anything live in regs across
1092 // the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon
1093 // when we get here from a longjmp(). We force everthing out of registers
1094 // except for our own input by listing the relevant registers in Defs. By
1095 // doing so, we also cause the prologue/epilogue code to actively preserve
1096 // all of the callee-saved resgisters, which is exactly what we want.
1097 // $val is a scratch register for our use.
1099 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], hasSideEffects = 1,
1100 isBarrier = 1, isCodeGenOnly = 1 in {
1101 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1102 AddrModeNone, SizeSpecial, NoItinerary, "", "",
1103 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1106 // FIXME: Non-Darwin version(s)
1107 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1108 Defs = [ R7, LR, SP ] in {
1109 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1110 AddrModeNone, SizeSpecial, IndexModeNone,
1111 Pseudo, NoItinerary, "", "",
1112 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1113 Requires<[IsThumb, IsDarwin]>;
1116 //===----------------------------------------------------------------------===//
1117 // Non-Instruction Patterns
1121 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1122 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1123 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1124 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1125 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1126 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1128 // Subtract with carry
1129 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1130 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1131 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1132 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1133 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1134 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1136 // ConstantPool, GlobalAddress
1137 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1138 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1141 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1142 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1145 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1146 Requires<[IsThumb, IsNotDarwin]>;
1147 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1148 Requires<[IsThumb, IsDarwin]>;
1150 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1151 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1152 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1153 Requires<[IsThumb, HasV5T, IsDarwin]>;
1155 // Indirect calls to ARM routines
1156 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1157 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1158 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1159 Requires<[IsThumb, HasV5T, IsDarwin]>;
1161 // zextload i1 -> zextload i8
1162 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
1163 (tLDRB t_addrmode_s1:$addr)>;
1165 // extload -> zextload
1166 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1167 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
1168 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
1170 // If it's impossible to use [r,r] address mode for sextload, select to
1171 // ldr{b|h} + sxt{b|h} instead.
1172 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1173 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
1174 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1175 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
1176 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
1177 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1179 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
1180 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
1181 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
1182 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
1184 // Large immediate handling.
1187 def : T1Pat<(i32 thumb_immshifted:$src),
1188 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1189 (thumb_immshifted_shamt imm:$src))>;
1191 def : T1Pat<(i32 imm0_255_comp:$src),
1192 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1194 // Pseudo instruction that combines ldr from constpool and add pc. This should
1195 // be expanded into two instructions late to allow if-conversion and
1197 let isReMaterializable = 1 in
1198 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1200 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1202 Requires<[IsThumb, IsThumb1Only]>;