1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 // For both thumb1 and thumb2.
131 let isNotDuplicable = 1 in
132 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr,
133 "\n$cp:\n\tadd\t$dst, pc",
134 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
137 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs), IIC_iALUi,
138 "add\t$dst, pc, $rhs * 4", []>;
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs), IIC_iALUi,
142 "add\t$dst, $sp, $rhs * 4", []>;
145 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
146 "add\t$dst, $rhs * 4", []>;
149 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iALUi,
150 "sub\t$dst, $rhs * 4", []>;
153 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
154 "add\t$dst, $rhs", []>;
157 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
158 "add\t$dst, $rhs", []>;
160 // Pseudo instruction that will expand into a tSUBspi + a copy.
161 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
162 def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
163 NoItinerary, "@ sub\t$dst, $rhs * 4", []>;
165 def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
166 NoItinerary, "@ add\t$dst, $rhs", []>;
169 def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
170 NoItinerary, "@ and\t$dst, $rhs", []>;
171 } // usesCustomDAGSchedInserter
173 //===----------------------------------------------------------------------===//
174 // Control Flow Instructions.
177 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
178 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>;
179 // Alternative return instruction used by vararg functions.
180 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>;
184 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
185 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "bx\t$dst",
189 // FIXME: remove when we have a way to marking a MI with these properties.
190 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
191 hasExtraDefRegAllocReq = 1 in
192 def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
196 Defs = [R0, R1, R2, R3, R12, LR,
197 D0, D1, D2, D3, D4, D5, D6, D7,
198 D16, D17, D18, D19, D20, D21, D22, D23,
199 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
200 // Also used for Thumb2
201 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
203 [(ARMtcall tglobaladdr:$func)]>,
204 Requires<[IsThumb, IsNotDarwin]>;
206 // ARMv5T and above, also used for Thumb2
207 def tBLXi : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
209 [(ARMcall tglobaladdr:$func)]>,
210 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
212 // Also used for Thumb2
213 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
215 [(ARMtcall GPR:$func)]>,
216 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
219 def tBX : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
220 "mov\tlr, pc\n\tbx\t$func",
221 [(ARMcall_nolink tGPR:$func)]>,
222 Requires<[IsThumb1Only, IsNotDarwin]>;
225 // On Darwin R9 is call-clobbered.
227 Defs = [R0, R1, R2, R3, R9, R12, LR,
228 D0, D1, D2, D3, D4, D5, D6, D7,
229 D16, D17, D18, D19, D20, D21, D22, D23,
230 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in {
231 // Also used for Thumb2
232 def tBLr9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
234 [(ARMtcall tglobaladdr:$func)]>,
235 Requires<[IsThumb, IsDarwin]>;
237 // ARMv5T and above, also used for Thumb2
238 def tBLXi_r9 : TIx2<(outs), (ins i32imm:$func, variable_ops), IIC_Br,
240 [(ARMcall tglobaladdr:$func)]>,
241 Requires<[IsThumb, HasV5T, IsDarwin]>;
243 // Also used for Thumb2
244 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
246 [(ARMtcall GPR:$func)]>,
247 Requires<[IsThumb, HasV5T, IsDarwin]>;
250 def tBXr9 : TIx2<(outs), (ins tGPR:$func, variable_ops), IIC_Br,
251 "mov\tlr, pc\n\tbx\t$func",
252 [(ARMcall_nolink tGPR:$func)]>,
253 Requires<[IsThumb1Only, IsDarwin]>;
256 let isBranch = 1, isTerminator = 1 in {
257 let isBarrier = 1 in {
258 let isPredicable = 1 in
259 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br,
260 "b\t$target", [(br bb:$target)]>;
264 def tBfar : TIx2<(outs), (ins brtarget:$target), IIC_Br,
265 "bl\t$target\t@ far jump",[]>;
267 def tBR_JTr : T1JTI<(outs),
268 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
269 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt",
270 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
274 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
275 // a two-value operand where a dag node expects two operands. :(
276 let isBranch = 1, isTerminator = 1 in
277 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br,
279 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
281 //===----------------------------------------------------------------------===//
282 // Load Store Instructions.
285 let canFoldAsLoad = 1 in
286 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr,
287 "ldr", "\t$dst, $addr",
288 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
290 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr,
291 "ldrb", "\t$dst, $addr",
292 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
294 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr,
295 "ldrh", "\t$dst, $addr",
296 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
298 let AddedComplexity = 10 in
299 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
300 "ldrsb", "\t$dst, $addr",
301 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
303 let AddedComplexity = 10 in
304 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr,
305 "ldrsh", "\t$dst, $addr",
306 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
308 let canFoldAsLoad = 1 in
309 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
310 "ldr", "\t$dst, $addr",
311 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
313 // Special instruction for restore. It cannot clobber condition register
314 // when it's expanded by eliminateCallFramePseudoInstr().
315 let canFoldAsLoad = 1, mayLoad = 1 in
316 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi,
317 "ldr", "\t$dst, $addr", []>;
320 let canFoldAsLoad = 1 in
321 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
322 "ldr", "\t$dst, $addr",
323 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
325 // Special LDR for loads from non-pc-relative constpools.
326 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
327 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi,
328 "ldr", "\t$dst, $addr", []>;
330 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer,
331 "str", "\t$src, $addr",
332 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
334 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer,
335 "strb", "\t$src, $addr",
336 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
338 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer,
339 "strh", "\t$src, $addr",
340 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
342 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
343 "str", "\t$src, $addr",
344 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
346 let mayStore = 1 in {
347 // Special instruction for spill. It cannot clobber condition register
348 // when it's expanded by eliminateCallFramePseudoInstr().
349 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei,
350 "str", "\t$src, $addr", []>;
353 //===----------------------------------------------------------------------===//
354 // Load / store multiple Instructions.
357 // These requires base address to be written back or one of the loaded regs.
358 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
359 def tLDM : T1I<(outs),
360 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
362 "ldm${addr:submode}${p}\t$addr, $wb", []>;
364 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
365 def tSTM : T1I<(outs),
366 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops),
368 "stm${addr:submode}${p}\t$addr, $wb", []>;
370 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
371 def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
374 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
375 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br,
376 "push${p}\t$wb", []>;
378 //===----------------------------------------------------------------------===//
379 // Arithmetic Instructions.
382 // Add with carry register
383 let isCommutable = 1, Uses = [CPSR] in
384 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
385 "adc", "\t$dst, $rhs",
386 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
389 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
390 "add", "\t$dst, $lhs, $rhs",
391 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
393 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
394 "add", "\t$dst, $rhs",
395 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
398 let isCommutable = 1 in
399 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
400 "add", "\t$dst, $lhs, $rhs",
401 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
403 let neverHasSideEffects = 1 in
404 def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
405 "add", "\t$dst, $rhs", []>;
408 let isCommutable = 1 in
409 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
410 "and", "\t$dst, $rhs",
411 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
414 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
415 "asr", "\t$dst, $lhs, $rhs",
416 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
419 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
420 "asr", "\t$dst, $rhs",
421 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
424 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
425 "bic", "\t$dst, $rhs",
426 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
429 let Defs = [CPSR] in {
430 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
431 "cmn", "\t$lhs, $rhs",
432 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
433 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
434 "cmn", "\t$lhs, $rhs",
435 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
439 let Defs = [CPSR] in {
440 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
441 "cmp", "\t$lhs, $rhs",
442 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
443 def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi,
444 "cmp", "\t$lhs, $rhs",
445 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
450 let Defs = [CPSR] in {
451 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
452 "cmp", "\t$lhs, $rhs",
453 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
454 def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
455 "cmp", "\t$lhs, $rhs",
456 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
458 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
459 "cmp", "\t$lhs, $rhs", []>;
460 def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr,
461 "cmp", "\t$lhs, $rhs", []>;
466 let isCommutable = 1 in
467 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
468 "eor", "\t$dst, $rhs",
469 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
472 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
473 "lsl", "\t$dst, $lhs, $rhs",
474 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
477 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
478 "lsl", "\t$dst, $rhs",
479 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
482 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi,
483 "lsr", "\t$dst, $lhs, $rhs",
484 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
487 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
488 "lsr", "\t$dst, $rhs",
489 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
492 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi,
493 "mov", "\t$dst, $src",
494 [(set tGPR:$dst, imm0_255:$src)]>;
496 // TODO: A7-73: MOV(2) - mov setting flag.
499 let neverHasSideEffects = 1 in {
500 // FIXME: Make this predicable.
501 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
502 "mov\t$dst, $src", []>;
504 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
505 "movs\t$dst, $src", []>;
507 // FIXME: Make these predicable.
508 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr,
509 "mov\t$dst, $src", []>;
510 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr,
511 "mov\t$dst, $src", []>;
512 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr,
513 "mov\t$dst, $src", []>;
514 } // neverHasSideEffects
517 let isCommutable = 1 in
518 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32,
519 "mul", "\t$dst, $rhs",
520 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
522 // move inverse register
523 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr,
524 "mvn", "\t$dst, $src",
525 [(set tGPR:$dst, (not tGPR:$src))]>;
527 // bitwise or register
528 let isCommutable = 1 in
529 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
530 "orr", "\t$dst, $rhs",
531 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
534 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
535 "rev", "\t$dst, $src",
536 [(set tGPR:$dst, (bswap tGPR:$src))]>,
537 Requires<[IsThumb1Only, HasV6]>;
539 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
540 "rev16", "\t$dst, $src",
542 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
543 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
544 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
545 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
546 Requires<[IsThumb1Only, HasV6]>;
548 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
549 "revsh", "\t$dst, $src",
552 (or (srl (and tGPR:$src, 0xFF00), (i32 8)),
553 (shl tGPR:$src, (i32 8))), i16))]>,
554 Requires<[IsThumb1Only, HasV6]>;
556 // rotate right register
557 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr,
558 "ror", "\t$dst, $rhs",
559 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
562 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi,
563 "rsb", "\t$dst, $src, #0",
564 [(set tGPR:$dst, (ineg tGPR:$src))]>;
566 // Subtract with carry register
568 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
569 "sbc", "\t$dst, $rhs",
570 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
572 // Subtract immediate
573 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
574 "sub", "\t$dst, $lhs, $rhs",
575 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
577 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi,
578 "sub", "\t$dst, $rhs",
579 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
582 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr,
583 "sub", "\t$dst, $lhs, $rhs",
584 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
586 // TODO: A7-96: STMIA - store multiple.
589 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
590 "sxtb", "\t$dst, $src",
591 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
592 Requires<[IsThumb1Only, HasV6]>;
595 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
596 "sxth", "\t$dst, $src",
597 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
598 Requires<[IsThumb1Only, HasV6]>;
601 let isCommutable = 1, Defs = [CPSR] in
602 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr,
603 "tst", "\t$lhs, $rhs",
604 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
607 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
608 "uxtb", "\t$dst, $src",
609 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
610 Requires<[IsThumb1Only, HasV6]>;
613 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr,
614 "uxth", "\t$dst, $src",
615 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
616 Requires<[IsThumb1Only, HasV6]>;
619 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
620 // Expanded by the scheduler into a branch sequence.
621 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
623 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
624 NoItinerary, "@ tMOVCCr $cc",
625 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
628 // 16-bit movcc in IT blocks for Thumb2.
629 def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr,
630 "mov", "\t$dst, $rhs", []>;
632 def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi,
633 "mov", "\t$dst, $rhs", []>;
635 // tLEApcrel - Load a pc-relative address into a register without offending the
637 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi,
638 "adr$p\t$dst, #$label", []>;
640 def tLEApcrelJT : T1I<(outs tGPR:$dst),
641 (ins i32imm:$label, nohash_imm:$id, pred:$p),
642 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>;
644 //===----------------------------------------------------------------------===//
648 // __aeabi_read_tp preserves the registers r1-r3.
651 def tTPsoft : TIx2<(outs), (ins), IIC_Br,
652 "bl\t__aeabi_read_tp",
653 [(set R0, ARMthread_pointer)]>;
656 //===----------------------------------------------------------------------===//
657 // Non-Instruction Patterns
661 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
662 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
663 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
664 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
665 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
666 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
668 // Subtract with carry
669 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
670 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
671 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
672 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
673 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
674 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
676 // ConstantPool, GlobalAddress
677 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
678 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
681 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
682 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
685 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
686 Requires<[IsThumb, IsNotDarwin]>;
687 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
688 Requires<[IsThumb, IsDarwin]>;
690 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
691 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
692 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
693 Requires<[IsThumb, HasV5T, IsDarwin]>;
695 // Indirect calls to ARM routines
696 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
697 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
698 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
699 Requires<[IsThumb, HasV5T, IsDarwin]>;
701 // zextload i1 -> zextload i8
702 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
703 (tLDRB t_addrmode_s1:$addr)>;
705 // extload -> zextload
706 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
707 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
708 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
710 // If it's impossible to use [r,r] address mode for sextload, select to
711 // ldr{b|h} + sxt{b|h} instead.
712 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
713 (tSXTB (tLDRB t_addrmode_s1:$addr))>,
714 Requires<[IsThumb1Only, HasV6]>;
715 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
716 (tSXTH (tLDRH t_addrmode_s2:$addr))>,
717 Requires<[IsThumb1Only, HasV6]>;
719 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
720 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>;
721 def : T1Pat<(sextloadi16 t_addrmode_s1:$addr),
722 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>;
724 // Large immediate handling.
727 def : T1Pat<(i32 thumb_immshifted:$src),
728 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
729 (thumb_immshifted_shamt imm:$src))>;
731 def : T1Pat<(i32 imm0_255_comp:$src),
732 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;