1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr : Operand<i32>, ImmLeaf<i32, [{
23 return Imm > 0 && Imm <= 32;
25 let EncoderMethod = "getThumbSRImmOpValue";
26 let DecoderMethod = "DecodeThumbSRImm";
29 def imm_neg_XFORM : SDNodeXForm<imm, [{
30 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
32 def imm_comp_XFORM : SDNodeXForm<imm, [{
33 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
36 def imm0_7_neg : PatLeaf<(i32 imm), [{
37 return (uint32_t)-N->getZExtValue() < 8;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : ImmLeaf<i32, [{
45 return Imm >= 8 && Imm < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift. This uses
53 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54 // to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // ADR instruction labels.
70 def t_adrlabel : Operand<i32> {
71 let EncoderMethod = "getThumbAdrLabelOpValue";
74 // Scaled 4 immediate.
75 def t_imm_s4 : Operand<i32> {
76 let PrintMethod = "printThumbS4ImmOperand";
77 let OperandType = "OPERAND_IMMEDIATE";
80 // Define Thumb specific addressing modes.
82 let OperandType = "OPERAND_PCREL" in {
83 def t_brtarget : Operand<OtherVT> {
84 let EncoderMethod = "getThumbBRTargetOpValue";
85 let DecoderMethod = "DecodeThumbBROperand";
88 def t_bcctarget : Operand<i32> {
89 let EncoderMethod = "getThumbBCCTargetOpValue";
90 let DecoderMethod = "DecodeThumbBCCTargetOperand";
93 def t_cbtarget : Operand<i32> {
94 let EncoderMethod = "getThumbCBTargetOpValue";
95 let DecoderMethod = "DecodeThumbCmpBROperand";
98 def t_bltarget : Operand<i32> {
99 let EncoderMethod = "getThumbBLTargetOpValue";
100 let DecoderMethod = "DecodeThumbBLTargetOperand";
103 def t_blxtarget : Operand<i32> {
104 let EncoderMethod = "getThumbBLXTargetOpValue";
105 let DecoderMethod = "DecodeThumbBLXOffset";
109 // t_addrmode_rr := reg + reg
111 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
112 def t_addrmode_rr : Operand<i32>,
113 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
114 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
115 let PrintMethod = "printThumbAddrModeRROperand";
116 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
119 // t_addrmode_rrs := reg + reg
121 def t_addrmode_rrs1 : Operand<i32>,
122 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
123 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
124 let PrintMethod = "printThumbAddrModeRROperand";
125 let DecoderMethod = "DecodeThumbAddrModeRR";
126 let ParserMatchClass = t_addrmode_rr_asm_operand;
127 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
129 def t_addrmode_rrs2 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132 let DecoderMethod = "DecodeThumbAddrModeRR";
133 let PrintMethod = "printThumbAddrModeRROperand";
134 let ParserMatchClass = t_addrmode_rr_asm_operand;
135 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
137 def t_addrmode_rrs4 : Operand<i32>,
138 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
139 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
140 let DecoderMethod = "DecodeThumbAddrModeRR";
141 let PrintMethod = "printThumbAddrModeRROperand";
142 let ParserMatchClass = t_addrmode_rr_asm_operand;
143 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
146 // t_addrmode_is4 := reg + imm5 * 4
148 def t_addrmode_is4 : Operand<i32>,
149 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
150 let EncoderMethod = "getAddrModeISOpValue";
151 let DecoderMethod = "DecodeThumbAddrModeIS";
152 let PrintMethod = "printThumbAddrModeImm5S4Operand";
153 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
156 // t_addrmode_is2 := reg + imm5 * 2
158 def t_addrmode_is2 : Operand<i32>,
159 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
160 let EncoderMethod = "getAddrModeISOpValue";
161 let DecoderMethod = "DecodeThumbAddrModeIS";
162 let PrintMethod = "printThumbAddrModeImm5S2Operand";
163 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
166 // t_addrmode_is1 := reg + imm5
168 def t_addrmode_is1 : Operand<i32>,
169 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
170 let EncoderMethod = "getAddrModeISOpValue";
171 let DecoderMethod = "DecodeThumbAddrModeIS";
172 let PrintMethod = "printThumbAddrModeImm5S1Operand";
173 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
176 // t_addrmode_sp := sp + imm8 * 4
178 def t_addrmode_sp : Operand<i32>,
179 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
180 let EncoderMethod = "getAddrModeThumbSPOpValue";
181 let DecoderMethod = "DecodeThumbAddrModeSP";
182 let PrintMethod = "printThumbAddrModeSPOperand";
183 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
186 // t_addrmode_pc := <label> => pc + imm8 * 4
188 def t_addrmode_pc : Operand<i32> {
189 let EncoderMethod = "getAddrModePCOpValue";
190 let DecoderMethod = "DecodeThumbAddrModePC";
193 //===----------------------------------------------------------------------===//
194 // Miscellaneous Instructions.
197 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
198 // from removing one half of the matched pairs. That breaks PEI, which assumes
199 // these will always be in pairs, and asserts if it finds otherwise. Better way?
200 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
201 def tADJCALLSTACKUP :
202 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
203 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
204 Requires<[IsThumb, IsThumb1Only]>;
206 def tADJCALLSTACKDOWN :
207 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
208 [(ARMcallseq_start imm:$amt)]>,
209 Requires<[IsThumb, IsThumb1Only]>;
212 // T1Disassembly - A simple class to make encoding some disassembly patterns
213 // easier and less verbose.
214 class T1Disassembly<bits<2> op1, bits<8> op2>
215 : T1Encoding<0b101111> {
220 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
221 [/* For disassembly only; pattern left blank */]>,
222 T1Disassembly<0b11, 0x00>; // A8.6.110
224 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
225 [/* For disassembly only; pattern left blank */]>,
226 T1Disassembly<0b11, 0x10>; // A8.6.410
228 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
229 [/* For disassembly only; pattern left blank */]>,
230 T1Disassembly<0b11, 0x20>; // A8.6.408
232 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
233 [/* For disassembly only; pattern left blank */]>,
234 T1Disassembly<0b11, 0x30>; // A8.6.409
236 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
237 [/* For disassembly only; pattern left blank */]>,
238 T1Disassembly<0b11, 0x40>; // A8.6.157
240 // The i32imm operand $val can be used by a debugger to store more information
241 // about the breakpoint.
242 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
243 [/* For disassembly only; pattern left blank */]>,
244 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
250 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
251 []>, T1Encoding<0b101101> {
254 let Inst{9-5} = 0b10010;
257 let Inst{2-0} = 0b000;
260 // Change Processor State is a system instruction -- for disassembly only.
261 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
262 NoItinerary, "cps$imod $iflags",
263 [/* For disassembly only; pattern left blank */]>,
271 let Inst{2-0} = iflags;
272 let DecoderMethod = "DecodeThumbCPS";
275 // For both thumb1 and thumb2.
276 let isNotDuplicable = 1, isCodeGenOnly = 1 in
277 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
278 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
279 T1Special<{0,0,?,?}> {
282 let Inst{6-3} = 0b1111; // Rm = pc
286 // ADD <Rd>, sp, #<imm8>
287 // This is rematerializable, which is particularly useful for taking the
288 // address of locals.
289 let isReMaterializable = 1 in
290 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
291 "add\t$dst, $sp, $rhs", []>,
292 T1Encoding<{1,0,1,0,1,?}> {
296 let Inst{10-8} = dst;
298 let DecoderMethod = "DecodeThumbAddSpecialReg";
301 // ADD sp, sp, #<imm7>
302 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
303 "add\t$dst, $rhs", []>,
304 T1Misc<{0,0,0,0,0,?,?}> {
308 let DecoderMethod = "DecodeThumbAddSPImm";
311 // SUB sp, sp, #<imm7>
312 // FIXME: The encoding and the ASM string don't match up.
313 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
314 "sub\t$dst, $rhs", []>,
315 T1Misc<{0,0,0,0,1,?,?}> {
319 let DecoderMethod = "DecodeThumbAddSPImm";
323 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
324 "add\t$dst, $rhs", []>,
325 T1Special<{0,0,?,?}> {
326 // A8.6.9 Encoding T1
328 let Inst{7} = dst{3};
329 let Inst{6-3} = 0b1101;
330 let Inst{2-0} = dst{2-0};
331 let DecoderMethod = "DecodeThumbAddSPReg";
335 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
336 "add\t$dst, $rhs", []>,
337 T1Special<{0,0,?,?}> {
338 // A8.6.9 Encoding T2
342 let Inst{2-0} = 0b101;
343 let DecoderMethod = "DecodeThumbAddSPReg";
346 //===----------------------------------------------------------------------===//
347 // Control Flow Instructions.
351 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
352 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
353 T1Special<{1,1,0,?}> {
357 let Inst{2-0} = 0b000;
361 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
362 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
363 [(ARMretflag)], (tBX LR, pred:$p)>;
365 // Alternative return instruction used by vararg functions.
366 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
368 (tBX GPR:$Rm, pred:$p)>;
371 // All calls clobber the non-callee saved registers. SP is marked as a use to
372 // prevent stack-pointer assignments that appear immediately before calls from
373 // potentially appearing dead.
375 // On non-Darwin platforms R9 is callee-saved.
376 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
378 // Also used for Thumb2
379 def tBL : TIx2<0b11110, 0b11, 1,
380 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
382 [(ARMtcall tglobaladdr:$func)]>,
383 Requires<[IsThumb, IsNotDarwin]> {
385 let Inst{26} = func{21};
386 let Inst{25-16} = func{20-11};
389 let Inst{10-0} = func{10-0};
392 // ARMv5T and above, also used for Thumb2
393 def tBLXi : TIx2<0b11110, 0b11, 0,
394 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
396 [(ARMcall tglobaladdr:$func)]>,
397 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
399 let Inst{25-16} = func{20-11};
402 let Inst{10-1} = func{10-1};
403 let Inst{0} = 0; // func{0} is assumed zero
406 // Also used for Thumb2
407 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
409 [(ARMtcall GPR:$func)]>,
410 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
411 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
413 let Inst{6-3} = func;
414 let Inst{2-0} = 0b000;
418 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
420 [(ARMcall_nolink tGPR:$func)]>,
421 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
425 // On Darwin R9 is call-clobbered.
426 // R7 is marked as a use to prevent frame-pointer assignments from being
427 // moved above / below calls.
428 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
430 // Also used for Thumb2
431 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
432 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
433 (tBL pred:$p, t_bltarget:$func)>,
434 Requires<[IsThumb, IsDarwin]>;
436 // ARMv5T and above, also used for Thumb2
437 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
438 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
439 (tBLXi pred:$p, t_blxtarget:$func)>,
440 Requires<[IsThumb, HasV5T, IsDarwin]>;
442 // Also used for Thumb2
443 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
444 2, IIC_Br, [(ARMtcall GPR:$func)],
445 (tBLXr pred:$p, GPR:$func)>,
446 Requires<[IsThumb, HasV5T, IsDarwin]>;
449 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
451 [(ARMcall_nolink tGPR:$func)]>,
452 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
455 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
456 let isPredicable = 1 in
457 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
458 "b\t$target", [(br bb:$target)]>,
459 T1Encoding<{1,1,1,0,0,?}> {
461 let Inst{10-0} = target;
465 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
466 // the clobber of LR.
468 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
469 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
471 def tBR_JTr : tPseudoInst<(outs),
472 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
474 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
475 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
479 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
480 // a two-value operand where a dag node expects two operands. :(
481 let isBranch = 1, isTerminator = 1 in
482 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
484 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
485 T1BranchCond<{1,1,0,1}> {
489 let Inst{7-0} = target;
492 // Compare and branch on zero / non-zero
493 let isBranch = 1, isTerminator = 1 in {
494 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
495 "cbz\t$Rn, $target", []>,
496 T1Misc<{0,0,?,1,?,?,?}> {
500 let Inst{9} = target{5};
501 let Inst{7-3} = target{4-0};
505 def tCBNZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
506 "cbnz\t$Rn, $target", []>,
507 T1Misc<{1,0,?,1,?,?,?}> {
511 let Inst{9} = target{5};
512 let Inst{7-3} = target{4-0};
518 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
520 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
522 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
523 // on Darwin), so it's in ARMInstrThumb2.td.
524 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
526 (tBX GPR:$dst, (ops 14, zero_reg))>,
527 Requires<[IsThumb, IsDarwin]>;
529 // Non-Darwin versions (the difference is R9).
530 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
532 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
534 (tB t_brtarget:$dst)>,
535 Requires<[IsThumb, IsNotDarwin]>;
536 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
538 (tBX GPR:$dst, (ops 14, zero_reg))>,
539 Requires<[IsThumb, IsNotDarwin]>;
544 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
545 // A8.6.16 B: Encoding T1
546 // If Inst{11-8} == 0b1111 then SEE SVC
547 let isCall = 1, Uses = [SP] in
548 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
549 "svc", "\t$imm", []>, Encoding16 {
551 let Inst{15-12} = 0b1101;
552 let Inst{11-8} = 0b1111;
556 // The assembler uses 0xDEFE for a trap instruction.
557 let isBarrier = 1, isTerminator = 1 in
558 def tTRAP : TI<(outs), (ins), IIC_Br,
559 "trap", [(trap)]>, Encoding16 {
563 //===----------------------------------------------------------------------===//
564 // Load Store Instructions.
567 // Loads: reg/reg and reg/imm5
568 let canFoldAsLoad = 1, isReMaterializable = 1 in
569 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
570 Operand AddrMode_r, Operand AddrMode_i,
571 AddrMode am, InstrItinClass itin_r,
572 InstrItinClass itin_i, string asm,
575 T1pILdStEncode<reg_opc,
576 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
577 am, itin_r, asm, "\t$Rt, $addr",
578 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
580 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
581 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
582 am, itin_i, asm, "\t$Rt, $addr",
583 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
585 // Stores: reg/reg and reg/imm5
586 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
587 Operand AddrMode_r, Operand AddrMode_i,
588 AddrMode am, InstrItinClass itin_r,
589 InstrItinClass itin_i, string asm,
592 T1pILdStEncode<reg_opc,
593 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
594 am, itin_r, asm, "\t$Rt, $addr",
595 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
597 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
598 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
599 am, itin_i, asm, "\t$Rt, $addr",
600 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
604 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
605 t_addrmode_is4, AddrModeT1_4,
606 IIC_iLoad_r, IIC_iLoad_i, "ldr",
607 UnOpFrag<(load node:$Src)>>;
610 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
611 t_addrmode_is1, AddrModeT1_1,
612 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
613 UnOpFrag<(zextloadi8 node:$Src)>>;
616 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
617 t_addrmode_is2, AddrModeT1_2,
618 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
619 UnOpFrag<(zextloadi16 node:$Src)>>;
621 let AddedComplexity = 10 in
622 def tLDRSB : // A8.6.80
623 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
624 AddrModeT1_1, IIC_iLoad_bh_r,
625 "ldrsb", "\t$dst, $addr",
626 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
628 let AddedComplexity = 10 in
629 def tLDRSH : // A8.6.84
630 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
631 AddrModeT1_2, IIC_iLoad_bh_r,
632 "ldrsh", "\t$dst, $addr",
633 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
635 let canFoldAsLoad = 1 in
636 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
637 "ldr", "\t$Rt, $addr",
638 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
643 let Inst{7-0} = addr;
647 // FIXME: Use ldr.n to work around a Darwin assembler bug.
648 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
649 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
650 "ldr", ".n\t$Rt, $addr",
651 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
652 T1Encoding<{0,1,0,0,1,?}> {
657 let Inst{7-0} = addr;
660 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
661 // For disassembly use only.
662 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
663 "ldr", "\t$Rt, $addr",
664 [/* disassembly only */]>,
665 T1Encoding<{0,1,0,0,1,?}> {
670 let Inst{7-0} = addr;
673 // A8.6.194 & A8.6.192
674 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
675 t_addrmode_is4, AddrModeT1_4,
676 IIC_iStore_r, IIC_iStore_i, "str",
677 BinOpFrag<(store node:$LHS, node:$RHS)>>;
679 // A8.6.197 & A8.6.195
680 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
681 t_addrmode_is1, AddrModeT1_1,
682 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
683 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
685 // A8.6.207 & A8.6.205
686 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
687 t_addrmode_is2, AddrModeT1_2,
688 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
689 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
692 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
693 "str", "\t$Rt, $addr",
694 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
699 let Inst{7-0} = addr;
702 //===----------------------------------------------------------------------===//
703 // Load / store multiple Instructions.
706 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
707 InstrItinClass itin_upd, bits<6> T1Enc,
708 bit L_bit, string baseOpc> {
710 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
711 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
716 let Inst{7-0} = regs;
720 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
721 "$Rn = $wb", itin_upd>,
722 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
723 GPR:$Rn, pred:$p, reglist:$regs)> {
725 let OutOperandList = (outs GPR:$wb);
726 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
728 let isCodeGenOnly = 1;
730 list<Predicate> Predicates = [IsThumb];
734 // These require base address to be written back or one of the loaded regs.
735 let neverHasSideEffects = 1 in {
737 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
738 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
739 {1,1,0,0,1,?}, 1, "tLDM">;
741 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
742 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
743 {1,1,0,0,0,?}, 0, "tSTM">;
745 } // neverHasSideEffects
747 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
748 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
750 "pop${p}\t$regs", []>,
751 T1Misc<{1,1,0,?,?,?,?}> {
753 let Inst{8} = regs{15};
754 let Inst{7-0} = regs{7-0};
757 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
758 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
760 "push${p}\t$regs", []>,
761 T1Misc<{0,1,0,?,?,?,?}> {
763 let Inst{8} = regs{14};
764 let Inst{7-0} = regs{7-0};
767 //===----------------------------------------------------------------------===//
768 // Arithmetic Instructions.
771 // Helper classes for encoding T1pI patterns:
772 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
773 string opc, string asm, list<dag> pattern>
774 : T1pI<oops, iops, itin, opc, asm, pattern>,
775 T1DataProcessing<opA> {
781 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
782 string opc, string asm, list<dag> pattern>
783 : T1pI<oops, iops, itin, opc, asm, pattern>,
791 // Helper classes for encoding T1sI patterns:
792 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
793 string opc, string asm, list<dag> pattern>
794 : T1sI<oops, iops, itin, opc, asm, pattern>,
795 T1DataProcessing<opA> {
801 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
802 string opc, string asm, list<dag> pattern>
803 : T1sI<oops, iops, itin, opc, asm, pattern>,
812 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
813 string opc, string asm, list<dag> pattern>
814 : T1sI<oops, iops, itin, opc, asm, pattern>,
822 // Helper classes for encoding T1sIt patterns:
823 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
824 string opc, string asm, list<dag> pattern>
825 : T1sIt<oops, iops, itin, opc, asm, pattern>,
826 T1DataProcessing<opA> {
832 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
833 string opc, string asm, list<dag> pattern>
834 : T1sIt<oops, iops, itin, opc, asm, pattern>,
838 let Inst{10-8} = Rdn;
839 let Inst{7-0} = imm8;
842 // Add with carry register
843 let isCommutable = 1, Uses = [CPSR] in
845 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
846 "adc", "\t$Rdn, $Rm",
847 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
850 def tADDi3 : // A8.6.4 T1
851 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
853 "add", "\t$Rd, $Rm, $imm3",
854 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
856 let Inst{8-6} = imm3;
859 def tADDi8 : // A8.6.4 T2
860 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
862 "add", "\t$Rdn, $imm8",
863 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
866 let isCommutable = 1 in
867 def tADDrr : // A8.6.6 T1
868 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
870 "add", "\t$Rd, $Rn, $Rm",
871 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
873 let neverHasSideEffects = 1 in
874 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
875 "add", "\t$Rdn, $Rm", []>,
876 T1Special<{0,0,?,?}> {
880 let Inst{7} = Rdn{3};
882 let Inst{2-0} = Rdn{2-0};
886 let isCommutable = 1 in
887 def tAND : // A8.6.12
888 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
890 "and", "\t$Rdn, $Rm",
891 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
894 def tASRri : // A8.6.14
895 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
897 "asr", "\t$Rd, $Rm, $imm5",
898 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
900 let Inst{10-6} = imm5;
904 def tASRrr : // A8.6.15
905 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
907 "asr", "\t$Rdn, $Rm",
908 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
911 def tBIC : // A8.6.20
912 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
914 "bic", "\t$Rdn, $Rm",
915 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
918 let isCompare = 1, Defs = [CPSR] in {
919 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
920 // Compare-to-zero still works out, just not the relationals
921 //def tCMN : // A8.6.33
922 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
924 // "cmn", "\t$lhs, $rhs",
925 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
927 def tCMNz : // A8.6.33
928 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
931 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
933 } // isCompare = 1, Defs = [CPSR]
936 let isCompare = 1, Defs = [CPSR] in {
937 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
938 "cmp", "\t$Rn, $imm8",
939 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
940 T1General<{1,0,1,?,?}> {
945 let Inst{7-0} = imm8;
949 def tCMPr : // A8.6.36 T1
950 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
953 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
955 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
956 "cmp", "\t$Rn, $Rm", []>,
957 T1Special<{0,1,?,?}> {
963 let Inst{2-0} = Rn{2-0};
965 } // isCompare = 1, Defs = [CPSR]
969 let isCommutable = 1 in
970 def tEOR : // A8.6.45
971 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
973 "eor", "\t$Rdn, $Rm",
974 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
977 def tLSLri : // A8.6.88
978 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
980 "lsl", "\t$Rd, $Rm, $imm5",
981 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
983 let Inst{10-6} = imm5;
987 def tLSLrr : // A8.6.89
988 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
990 "lsl", "\t$Rdn, $Rm",
991 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
994 def tLSRri : // A8.6.90
995 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
997 "lsr", "\t$Rd, $Rm, $imm5",
998 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
1000 let Inst{10-6} = imm5;
1004 def tLSRrr : // A8.6.91
1005 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1007 "lsr", "\t$Rdn, $Rm",
1008 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1011 let isMoveImm = 1 in
1012 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1013 "mov", "\t$Rd, $imm8",
1014 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1015 T1General<{1,0,0,?,?}> {
1019 let Inst{10-8} = Rd;
1020 let Inst{7-0} = imm8;
1023 // A7-73: MOV(2) - mov setting flag.
1025 let neverHasSideEffects = 1 in {
1026 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1028 "mov", "\t$Rd, $Rm", "", []>,
1029 T1Special<{1,0,?,?}> {
1033 let Inst{7} = Rd{3};
1035 let Inst{2-0} = Rd{2-0};
1037 let Defs = [CPSR] in
1038 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1039 "movs\t$Rd, $Rm", []>, Encoding16 {
1043 let Inst{15-6} = 0b0000000000;
1047 } // neverHasSideEffects
1049 // Multiply register
1050 let isCommutable = 1 in
1051 def tMUL : // A8.6.105 T1
1052 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1054 "mul", "\t$Rdn, $Rm, $Rdn",
1055 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1057 // Move inverse register
1058 def tMVN : // A8.6.107
1059 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1060 "mvn", "\t$Rd, $Rn",
1061 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1063 // Bitwise or register
1064 let isCommutable = 1 in
1065 def tORR : // A8.6.114
1066 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1068 "orr", "\t$Rdn, $Rm",
1069 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1072 def tREV : // A8.6.134
1073 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1075 "rev", "\t$Rd, $Rm",
1076 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1077 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1079 def tREV16 : // A8.6.135
1080 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1082 "rev16", "\t$Rd, $Rm",
1083 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1084 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1086 def tREVSH : // A8.6.136
1087 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1089 "revsh", "\t$Rd, $Rm",
1090 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1091 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1093 // Rotate right register
1094 def tROR : // A8.6.139
1095 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1097 "ror", "\t$Rdn, $Rm",
1098 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1101 def tRSB : // A8.6.141
1102 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1104 "rsb", "\t$Rd, $Rn, #0",
1105 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1107 // Subtract with carry register
1108 let Uses = [CPSR] in
1109 def tSBC : // A8.6.151
1110 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1112 "sbc", "\t$Rdn, $Rm",
1113 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1115 // Subtract immediate
1116 def tSUBi3 : // A8.6.210 T1
1117 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1119 "sub", "\t$Rd, $Rm, $imm3",
1120 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1122 let Inst{8-6} = imm3;
1125 def tSUBi8 : // A8.6.210 T2
1126 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1128 "sub", "\t$Rdn, $imm8",
1129 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1131 // Subtract register
1132 def tSUBrr : // A8.6.212
1133 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1135 "sub", "\t$Rd, $Rn, $Rm",
1136 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1138 // TODO: A7-96: STMIA - store multiple.
1141 def tSXTB : // A8.6.222
1142 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1144 "sxtb", "\t$Rd, $Rm",
1145 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1146 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1148 // Sign-extend short
1149 def tSXTH : // A8.6.224
1150 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1152 "sxth", "\t$Rd, $Rm",
1153 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1154 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1157 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1158 def tTST : // A8.6.230
1159 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1160 "tst", "\t$Rn, $Rm",
1161 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1164 def tUXTB : // A8.6.262
1165 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1167 "uxtb", "\t$Rd, $Rm",
1168 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1169 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1171 // Zero-extend short
1172 def tUXTH : // A8.6.264
1173 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1175 "uxth", "\t$Rd, $Rm",
1176 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1177 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1179 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1180 // Expanded after instruction selection into a branch sequence.
1181 let usesCustomInserter = 1 in // Expanded after instruction selection.
1182 def tMOVCCr_pseudo :
1183 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1185 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1187 // tLEApcrel - Load a pc-relative address into a register without offending the
1190 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1191 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1192 T1Encoding<{1,0,1,0,0,?}> {
1195 let Inst{10-8} = Rd;
1196 let Inst{7-0} = addr;
1197 let DecoderMethod = "DecodeThumbAddSpecialReg";
1200 let neverHasSideEffects = 1, isReMaterializable = 1 in
1201 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1204 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1205 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1208 //===----------------------------------------------------------------------===//
1212 // __aeabi_read_tp preserves the registers r1-r3.
1213 // This is a pseudo inst so that we can get the encoding right,
1214 // complete with fixup for the aeabi_read_tp function.
1215 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1216 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1217 [(set R0, ARMthread_pointer)]>;
1219 //===----------------------------------------------------------------------===//
1220 // SJLJ Exception handling intrinsics
1223 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1224 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1225 // from some other function to get here, and we're using the stack frame for the
1226 // containing function to save/restore registers, we can't keep anything live in
1227 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1228 // tromped upon when we get here from a longjmp(). We force everything out of
1229 // registers except for our own input by listing the relevant registers in
1230 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1231 // preserve all of the callee-saved resgisters, which is exactly what we want.
1232 // $val is a scratch register for our use.
1233 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1234 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1235 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1236 AddrModeNone, 0, NoItinerary, "","",
1237 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1239 // FIXME: Non-Darwin version(s)
1240 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1241 Defs = [ R7, LR, SP ] in
1242 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1243 AddrModeNone, 0, IndexModeNone,
1244 Pseudo, NoItinerary, "", "",
1245 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1246 Requires<[IsThumb, IsDarwin]>;
1248 //===----------------------------------------------------------------------===//
1249 // Non-Instruction Patterns
1253 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1254 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1255 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1256 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1259 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1260 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1261 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1262 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1263 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1264 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1266 // Subtract with carry
1267 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1268 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1269 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1270 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1271 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1272 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1274 // ConstantPool, GlobalAddress
1275 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1276 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1279 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1280 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1283 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1284 Requires<[IsThumb, IsNotDarwin]>;
1285 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1286 Requires<[IsThumb, IsDarwin]>;
1288 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1289 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1290 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1291 Requires<[IsThumb, HasV5T, IsDarwin]>;
1293 // Indirect calls to ARM routines
1294 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1295 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1296 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1297 Requires<[IsThumb, HasV5T, IsDarwin]>;
1299 // zextload i1 -> zextload i8
1300 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1301 (tLDRBr t_addrmode_rrs1:$addr)>;
1302 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1303 (tLDRBi t_addrmode_is1:$addr)>;
1305 // extload -> zextload
1306 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1307 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1308 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1309 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1310 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1311 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1313 // If it's impossible to use [r,r] address mode for sextload, select to
1314 // ldr{b|h} + sxt{b|h} instead.
1315 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1316 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1317 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1318 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1319 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1320 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1321 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1322 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1323 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1324 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1325 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1326 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1328 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1329 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1330 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1331 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1332 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1333 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1334 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1335 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1337 // Large immediate handling.
1340 def : T1Pat<(i32 thumb_immshifted:$src),
1341 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1342 (thumb_immshifted_shamt imm:$src))>;
1344 def : T1Pat<(i32 imm0_255_comp:$src),
1345 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1347 // Pseudo instruction that combines ldr from constpool and add pc. This should
1348 // be expanded into two instructions late to allow if-conversion and
1350 let isReMaterializable = 1 in
1351 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1353 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1355 Requires<[IsThumb, IsThumb1Only]>;
1357 // Pseudo-instruction for merged POP and return.
1358 // FIXME: remove when we have a way to marking a MI with these properties.
1359 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1360 hasExtraDefRegAllocReq = 1 in
1361 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1363 (tPOP pred:$p, reglist:$regs)>;
1365 // Indirect branch using "mov pc, $Rm"
1366 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1367 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1368 2, IIC_Br, [(brind GPR:$Rm)],
1369 (tMOVr PC, GPR:$Rm, pred:$p)>;