1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_neg_XFORM : SDNodeXForm<imm, [{
23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
25 def imm_comp_XFORM : SDNodeXForm<imm, [{
26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 def imm0_7_neg : PatLeaf<(i32 imm), [{
30 return (uint32_t)-N->getZExtValue() < 8;
33 def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; }
34 def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
35 let ParserMatchClass = imm0_255_asmoperand;
37 def imm0_255_comp : PatLeaf<(i32 imm), [{
38 return ~((uint32_t)N->getZExtValue()) < 256;
41 def imm8_255 : ImmLeaf<i32, [{
42 return Imm >= 8 && Imm < 256;
44 def imm8_255_neg : PatLeaf<(i32 imm), [{
45 unsigned Val = -N->getZExtValue();
46 return Val >= 8 && Val < 256;
49 // Break imm's up into two pieces: an immediate + a left shift. This uses
50 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
51 // to get the val/shift pieces.
52 def thumb_immshifted : PatLeaf<(imm), [{
53 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
56 def thumb_immshifted_val : SDNodeXForm<imm, [{
57 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
58 return CurDAG->getTargetConstant(V, MVT::i32);
61 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
62 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
63 return CurDAG->getTargetConstant(V, MVT::i32);
66 // ADR instruction labels.
67 def t_adrlabel : Operand<i32> {
68 let EncoderMethod = "getThumbAdrLabelOpValue";
71 // Scaled 4 immediate.
72 def t_imm_s4 : Operand<i32> {
73 let PrintMethod = "printThumbS4ImmOperand";
74 let OperandType = "OPERAND_IMMEDIATE";
77 // Define Thumb specific addressing modes.
79 let OperandType = "OPERAND_PCREL" in {
80 def t_brtarget : Operand<OtherVT> {
81 let EncoderMethod = "getThumbBRTargetOpValue";
84 def t_bcctarget : Operand<i32> {
85 let EncoderMethod = "getThumbBCCTargetOpValue";
88 def t_cbtarget : Operand<i32> {
89 let EncoderMethod = "getThumbCBTargetOpValue";
92 def t_bltarget : Operand<i32> {
93 let EncoderMethod = "getThumbBLTargetOpValue";
96 def t_blxtarget : Operand<i32> {
97 let EncoderMethod = "getThumbBLXTargetOpValue";
101 def MemModeRegThumbAsmOperand : AsmOperandClass {
102 let Name = "MemModeRegThumb";
103 let SuperClasses = [];
106 def MemModeImmThumbAsmOperand : AsmOperandClass {
107 let Name = "MemModeImmThumb";
108 let SuperClasses = [];
111 // t_addrmode_rr := reg + reg
113 def t_addrmode_rr : Operand<i32>,
114 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
115 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
116 let PrintMethod = "printThumbAddrModeRROperand";
117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
120 // t_addrmode_rrs := reg + reg
122 def t_addrmode_rrs1 : Operand<i32>,
123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125 let PrintMethod = "printThumbAddrModeRROperand";
126 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127 let ParserMatchClass = MemModeRegThumbAsmOperand;
129 def t_addrmode_rrs2 : Operand<i32>,
130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132 let PrintMethod = "printThumbAddrModeRROperand";
133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
134 let ParserMatchClass = MemModeRegThumbAsmOperand;
136 def t_addrmode_rrs4 : Operand<i32>,
137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
138 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139 let PrintMethod = "printThumbAddrModeRROperand";
140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141 let ParserMatchClass = MemModeRegThumbAsmOperand;
144 // t_addrmode_is4 := reg + imm5 * 4
146 def t_addrmode_is4 : Operand<i32>,
147 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
148 let EncoderMethod = "getAddrModeISOpValue";
149 let PrintMethod = "printThumbAddrModeImm5S4Operand";
150 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
151 let ParserMatchClass = MemModeImmThumbAsmOperand;
154 // t_addrmode_is2 := reg + imm5 * 2
156 def t_addrmode_is2 : Operand<i32>,
157 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
158 let EncoderMethod = "getAddrModeISOpValue";
159 let PrintMethod = "printThumbAddrModeImm5S2Operand";
160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
161 let ParserMatchClass = MemModeImmThumbAsmOperand;
164 // t_addrmode_is1 := reg + imm5
166 def t_addrmode_is1 : Operand<i32>,
167 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
168 let EncoderMethod = "getAddrModeISOpValue";
169 let PrintMethod = "printThumbAddrModeImm5S1Operand";
170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171 let ParserMatchClass = MemModeImmThumbAsmOperand;
174 // t_addrmode_sp := sp + imm8 * 4
176 def t_addrmode_sp : Operand<i32>,
177 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
178 let EncoderMethod = "getAddrModeThumbSPOpValue";
179 let PrintMethod = "printThumbAddrModeSPOperand";
180 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
181 let ParserMatchClass = MemModeImmThumbAsmOperand;
184 // t_addrmode_pc := <label> => pc + imm8 * 4
186 def t_addrmode_pc : Operand<i32> {
187 let EncoderMethod = "getAddrModePCOpValue";
188 let ParserMatchClass = MemModeImmThumbAsmOperand;
191 //===----------------------------------------------------------------------===//
192 // Miscellaneous Instructions.
195 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
196 // from removing one half of the matched pairs. That breaks PEI, which assumes
197 // these will always be in pairs, and asserts if it finds otherwise. Better way?
198 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
199 def tADJCALLSTACKUP :
200 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
201 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
202 Requires<[IsThumb, IsThumb1Only]>;
204 def tADJCALLSTACKDOWN :
205 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
206 [(ARMcallseq_start imm:$amt)]>,
207 Requires<[IsThumb, IsThumb1Only]>;
210 // T1Disassembly - A simple class to make encoding some disassembly patterns
211 // easier and less verbose.
212 class T1Disassembly<bits<2> op1, bits<8> op2>
213 : T1Encoding<0b101111> {
218 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
219 [/* For disassembly only; pattern left blank */]>,
220 T1Disassembly<0b11, 0x00>; // A8.6.110
222 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
223 [/* For disassembly only; pattern left blank */]>,
224 T1Disassembly<0b11, 0x10>; // A8.6.410
226 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
227 [/* For disassembly only; pattern left blank */]>,
228 T1Disassembly<0b11, 0x20>; // A8.6.408
230 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
231 [/* For disassembly only; pattern left blank */]>,
232 T1Disassembly<0b11, 0x30>; // A8.6.409
234 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
235 [/* For disassembly only; pattern left blank */]>,
236 T1Disassembly<0b11, 0x40>; // A8.6.157
238 // The i32imm operand $val can be used by a debugger to store more information
239 // about the breakpoint.
240 def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
241 [/* For disassembly only; pattern left blank */]>,
242 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
248 def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
249 [/* For disassembly only; pattern left blank */]>,
250 T1Encoding<0b101101> {
252 let Inst{9-5} = 0b10010;
254 let Inst{3} = 1; // Big-Endian
255 let Inst{2-0} = 0b000;
258 def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
259 [/* For disassembly only; pattern left blank */]>,
260 T1Encoding<0b101101> {
262 let Inst{9-5} = 0b10010;
264 let Inst{3} = 0; // Little-Endian
265 let Inst{2-0} = 0b000;
268 // Change Processor State is a system instruction -- for disassembly only.
269 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
270 NoItinerary, "cps$imod $iflags",
271 [/* For disassembly only; pattern left blank */]>,
279 let Inst{2-0} = iflags;
282 // For both thumb1 and thumb2.
283 let isNotDuplicable = 1, isCodeGenOnly = 1 in
284 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
285 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
286 T1Special<{0,0,?,?}> {
289 let Inst{6-3} = 0b1111; // Rm = pc
293 // PC relative add (ADR).
294 def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
295 "add\t$dst, pc, $rhs", []>,
296 T1Encoding<{1,0,1,0,0,?}> {
300 let Inst{10-8} = dst;
304 // ADD <Rd>, sp, #<imm8>
305 // This is rematerializable, which is particularly useful for taking the
306 // address of locals.
307 let isReMaterializable = 1 in
308 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
309 "add\t$dst, $sp, $rhs", []>,
310 T1Encoding<{1,0,1,0,1,?}> {
314 let Inst{10-8} = dst;
318 // ADD sp, sp, #<imm7>
319 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
320 "add\t$dst, $rhs", []>,
321 T1Misc<{0,0,0,0,0,?,?}> {
327 // SUB sp, sp, #<imm7>
328 // FIXME: The encoding and the ASM string don't match up.
329 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
330 "sub\t$dst, $rhs", []>,
331 T1Misc<{0,0,0,0,1,?,?}> {
338 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
339 "add\t$dst, $rhs", []>,
340 T1Special<{0,0,?,?}> {
341 // A8.6.9 Encoding T1
343 let Inst{7} = dst{3};
344 let Inst{6-3} = 0b1101;
345 let Inst{2-0} = dst{2-0};
349 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
350 "add\t$dst, $rhs", []>,
351 T1Special<{0,0,?,?}> {
352 // A8.6.9 Encoding T2
356 let Inst{2-0} = 0b101;
359 //===----------------------------------------------------------------------===//
360 // Control Flow Instructions.
364 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
365 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
366 T1Special<{1,1,0,?}> {
370 let Inst{2-0} = 0b000;
374 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
375 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
376 [(ARMretflag)], (tBX LR, pred:$p)>;
378 // Alternative return instruction used by vararg functions.
379 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
381 (tBX GPR:$Rm, pred:$p)>;
384 // All calls clobber the non-callee saved registers. SP is marked as a use to
385 // prevent stack-pointer assignments that appear immediately before calls from
386 // potentially appearing dead.
388 // On non-Darwin platforms R9 is callee-saved.
389 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
391 // Also used for Thumb2
392 def tBL : TIx2<0b11110, 0b11, 1,
393 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
395 [(ARMtcall tglobaladdr:$func)]>,
396 Requires<[IsThumb, IsNotDarwin]> {
398 let Inst{25-16} = func{20-11};
401 let Inst{10-0} = func{10-0};
404 // ARMv5T and above, also used for Thumb2
405 def tBLXi : TIx2<0b11110, 0b11, 0,
406 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
408 [(ARMcall tglobaladdr:$func)]>,
409 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
411 let Inst{25-16} = func{20-11};
414 let Inst{10-1} = func{10-1};
415 let Inst{0} = 0; // func{0} is assumed zero
418 // Also used for Thumb2
419 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
421 [(ARMtcall GPR:$func)]>,
422 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
423 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
425 let Inst{6-3} = func;
426 let Inst{2-0} = 0b000;
430 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
432 [(ARMcall_nolink tGPR:$func)]>,
433 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
437 // On Darwin R9 is call-clobbered.
438 // R7 is marked as a use to prevent frame-pointer assignments from being
439 // moved above / below calls.
440 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
442 // Also used for Thumb2
443 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
444 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
445 (tBL pred:$p, t_bltarget:$func)>,
446 Requires<[IsThumb, IsDarwin]>;
448 // ARMv5T and above, also used for Thumb2
449 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
450 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
451 (tBLXi pred:$p, t_blxtarget:$func)>,
452 Requires<[IsThumb, HasV5T, IsDarwin]>;
454 // Also used for Thumb2
455 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
456 2, IIC_Br, [(ARMtcall GPR:$func)],
457 (tBLXr pred:$p, GPR:$func)>,
458 Requires<[IsThumb, HasV5T, IsDarwin]>;
461 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
463 [(ARMcall_nolink tGPR:$func)]>,
464 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
467 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
468 let isPredicable = 1 in
469 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
470 "b\t$target", [(br bb:$target)]>,
471 T1Encoding<{1,1,1,0,0,?}> {
473 let Inst{10-0} = target;
477 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
478 // the clobber of LR.
480 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
481 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
483 def tBR_JTr : tPseudoInst<(outs),
484 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
486 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
487 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
491 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
492 // a two-value operand where a dag node expects two operands. :(
493 let isBranch = 1, isTerminator = 1 in
494 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
496 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
497 T1BranchCond<{1,1,0,1}> {
501 let Inst{7-0} = target;
504 // Compare and branch on zero / non-zero
505 let isBranch = 1, isTerminator = 1 in {
506 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
507 "cbz\t$Rn, $target", []>,
508 T1Misc<{0,0,?,1,?,?,?}> {
512 let Inst{9} = target{5};
513 let Inst{7-3} = target{4-0};
517 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
518 "cbnz\t$cmp, $target", []>,
519 T1Misc<{1,0,?,1,?,?,?}> {
523 let Inst{9} = target{5};
524 let Inst{7-3} = target{4-0};
530 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
532 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
534 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
535 // on Darwin), so it's in ARMInstrThumb2.td.
536 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
538 (tBX GPR:$dst, (ops 14, zero_reg))>,
539 Requires<[IsThumb, IsDarwin]>;
541 // Non-Darwin versions (the difference is R9).
542 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
544 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
546 (tB t_brtarget:$dst)>,
547 Requires<[IsThumb, IsNotDarwin]>;
548 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
550 (tBX GPR:$dst, (ops 14, zero_reg))>,
551 Requires<[IsThumb, IsNotDarwin]>;
556 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
557 // A8.6.16 B: Encoding T1
558 // If Inst{11-8} == 0b1111 then SEE SVC
559 let isCall = 1, Uses = [SP] in
560 def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
561 "svc", "\t$imm", []>, Encoding16 {
563 let Inst{15-12} = 0b1101;
564 let Inst{11-8} = 0b1111;
568 // The assembler uses 0xDEFE for a trap instruction.
569 let isBarrier = 1, isTerminator = 1 in
570 def tTRAP : TI<(outs), (ins), IIC_Br,
571 "trap", [(trap)]>, Encoding16 {
575 //===----------------------------------------------------------------------===//
576 // Load Store Instructions.
579 // Loads: reg/reg and reg/imm5
580 let canFoldAsLoad = 1, isReMaterializable = 1 in
581 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
582 Operand AddrMode_r, Operand AddrMode_i,
583 AddrMode am, InstrItinClass itin_r,
584 InstrItinClass itin_i, string asm,
587 T1pILdStEncode<reg_opc,
588 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
589 am, itin_r, asm, "\t$Rt, $addr",
590 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
592 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
593 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
594 am, itin_i, asm, "\t$Rt, $addr",
595 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
597 // Stores: reg/reg and reg/imm5
598 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
599 Operand AddrMode_r, Operand AddrMode_i,
600 AddrMode am, InstrItinClass itin_r,
601 InstrItinClass itin_i, string asm,
604 T1pILdStEncode<reg_opc,
605 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
606 am, itin_r, asm, "\t$Rt, $addr",
607 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
609 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
610 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
611 am, itin_i, asm, "\t$Rt, $addr",
612 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
616 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
617 t_addrmode_is4, AddrModeT1_4,
618 IIC_iLoad_r, IIC_iLoad_i, "ldr",
619 UnOpFrag<(load node:$Src)>>;
622 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
623 t_addrmode_is1, AddrModeT1_1,
624 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
625 UnOpFrag<(zextloadi8 node:$Src)>>;
628 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
629 t_addrmode_is2, AddrModeT1_2,
630 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
631 UnOpFrag<(zextloadi16 node:$Src)>>;
633 let AddedComplexity = 10 in
634 def tLDRSB : // A8.6.80
635 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
636 AddrModeT1_1, IIC_iLoad_bh_r,
637 "ldrsb", "\t$dst, $addr",
638 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
640 let AddedComplexity = 10 in
641 def tLDRSH : // A8.6.84
642 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
643 AddrModeT1_2, IIC_iLoad_bh_r,
644 "ldrsh", "\t$dst, $addr",
645 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
647 let canFoldAsLoad = 1 in
648 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
649 "ldr", "\t$Rt, $addr",
650 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
655 let Inst{7-0} = addr;
659 // FIXME: Use ldr.n to work around a Darwin assembler bug.
660 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
661 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
662 "ldr", ".n\t$Rt, $addr",
663 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
664 T1Encoding<{0,1,0,0,1,?}> {
669 let Inst{7-0} = addr;
672 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
673 // For disassembly use only.
674 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
675 "ldr", "\t$Rt, $addr",
676 [/* disassembly only */]>,
677 T1Encoding<{0,1,0,0,1,?}> {
682 let Inst{7-0} = addr;
685 // A8.6.194 & A8.6.192
686 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
687 t_addrmode_is4, AddrModeT1_4,
688 IIC_iStore_r, IIC_iStore_i, "str",
689 BinOpFrag<(store node:$LHS, node:$RHS)>>;
691 // A8.6.197 & A8.6.195
692 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
693 t_addrmode_is1, AddrModeT1_1,
694 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
695 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
697 // A8.6.207 & A8.6.205
698 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
699 t_addrmode_is2, AddrModeT1_2,
700 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
701 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
704 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
705 "str", "\t$Rt, $addr",
706 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
711 let Inst{7-0} = addr;
714 //===----------------------------------------------------------------------===//
715 // Load / store multiple Instructions.
718 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
719 InstrItinClass itin_upd, bits<6> T1Enc,
722 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
723 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
728 let Inst{7-0} = regs;
731 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
732 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
737 let Inst{7-0} = regs;
741 // These require base address to be written back or one of the loaded regs.
742 let neverHasSideEffects = 1 in {
744 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
745 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
748 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
749 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
752 } // neverHasSideEffects
754 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
755 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
757 "pop${p}\t$regs", []>,
758 T1Misc<{1,1,0,?,?,?,?}> {
760 let Inst{8} = regs{15};
761 let Inst{7-0} = regs{7-0};
764 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
765 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
767 "push${p}\t$regs", []>,
768 T1Misc<{0,1,0,?,?,?,?}> {
770 let Inst{8} = regs{14};
771 let Inst{7-0} = regs{7-0};
774 //===----------------------------------------------------------------------===//
775 // Arithmetic Instructions.
778 // Helper classes for encoding T1pI patterns:
779 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
780 string opc, string asm, list<dag> pattern>
781 : T1pI<oops, iops, itin, opc, asm, pattern>,
782 T1DataProcessing<opA> {
788 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
789 string opc, string asm, list<dag> pattern>
790 : T1pI<oops, iops, itin, opc, asm, pattern>,
798 // Helper classes for encoding T1sI patterns:
799 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
800 string opc, string asm, list<dag> pattern>
801 : T1sI<oops, iops, itin, opc, asm, pattern>,
802 T1DataProcessing<opA> {
808 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
809 string opc, string asm, list<dag> pattern>
810 : T1sI<oops, iops, itin, opc, asm, pattern>,
819 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
820 string opc, string asm, list<dag> pattern>
821 : T1sI<oops, iops, itin, opc, asm, pattern>,
829 // Helper classes for encoding T1sIt patterns:
830 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
831 string opc, string asm, list<dag> pattern>
832 : T1sIt<oops, iops, itin, opc, asm, pattern>,
833 T1DataProcessing<opA> {
839 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
840 string opc, string asm, list<dag> pattern>
841 : T1sIt<oops, iops, itin, opc, asm, pattern>,
845 let Inst{10-8} = Rdn;
846 let Inst{7-0} = imm8;
849 // Add with carry register
850 let isCommutable = 1, Uses = [CPSR] in
852 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
853 "adc", "\t$Rdn, $Rm",
854 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
857 def tADDi3 : // A8.6.4 T1
858 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
860 "add", "\t$Rd, $Rm, $imm3",
861 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
863 let Inst{8-6} = imm3;
866 def tADDi8 : // A8.6.4 T2
867 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
869 "add", "\t$Rdn, $imm8",
870 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
873 let isCommutable = 1 in
874 def tADDrr : // A8.6.6 T1
875 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
877 "add", "\t$Rd, $Rn, $Rm",
878 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
880 let neverHasSideEffects = 1 in
881 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
882 "add", "\t$Rdn, $Rm", []>,
883 T1Special<{0,0,?,?}> {
887 let Inst{7} = Rdn{3};
889 let Inst{2-0} = Rdn{2-0};
893 let isCommutable = 1 in
894 def tAND : // A8.6.12
895 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
897 "and", "\t$Rdn, $Rm",
898 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
901 def tASRri : // A8.6.14
902 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
904 "asr", "\t$Rd, $Rm, $imm5",
905 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
907 let Inst{10-6} = imm5;
911 def tASRrr : // A8.6.15
912 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
914 "asr", "\t$Rdn, $Rm",
915 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
918 def tBIC : // A8.6.20
919 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
921 "bic", "\t$Rdn, $Rm",
922 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
925 let isCompare = 1, Defs = [CPSR] in {
926 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
927 // Compare-to-zero still works out, just not the relationals
928 //def tCMN : // A8.6.33
929 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
931 // "cmn", "\t$lhs, $rhs",
932 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
934 def tCMNz : // A8.6.33
935 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
938 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
940 } // isCompare = 1, Defs = [CPSR]
943 let isCompare = 1, Defs = [CPSR] in {
944 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
945 "cmp", "\t$Rn, $imm8",
946 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
947 T1General<{1,0,1,?,?}> {
952 let Inst{7-0} = imm8;
956 def tCMPr : // A8.6.36 T1
957 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
960 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
962 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
963 "cmp", "\t$Rn, $Rm", []>,
964 T1Special<{0,1,?,?}> {
970 let Inst{2-0} = Rn{2-0};
972 } // isCompare = 1, Defs = [CPSR]
976 let isCommutable = 1 in
977 def tEOR : // A8.6.45
978 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
980 "eor", "\t$Rdn, $Rm",
981 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
984 def tLSLri : // A8.6.88
985 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
987 "lsl", "\t$Rd, $Rm, $imm5",
988 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
990 let Inst{10-6} = imm5;
994 def tLSLrr : // A8.6.89
995 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
997 "lsl", "\t$Rdn, $Rm",
998 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1001 def tLSRri : // A8.6.90
1002 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1004 "lsr", "\t$Rd, $Rm, $imm5",
1005 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1007 let Inst{10-6} = imm5;
1011 def tLSRrr : // A8.6.91
1012 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1014 "lsr", "\t$Rdn, $Rm",
1015 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1018 let isMoveImm = 1 in
1019 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1020 "mov", "\t$Rd, $imm8",
1021 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1022 T1General<{1,0,0,?,?}> {
1026 let Inst{10-8} = Rd;
1027 let Inst{7-0} = imm8;
1030 // A7-73: MOV(2) - mov setting flag.
1032 let neverHasSideEffects = 1 in {
1033 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1035 "mov", "\t$Rd, $Rm", "", []>,
1036 T1Special<{1,0,?,?}> {
1040 let Inst{7} = Rd{3};
1042 let Inst{2-0} = Rd{2-0};
1044 let Defs = [CPSR] in
1045 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1046 "movs\t$Rd, $Rm", []>, Encoding16 {
1050 let Inst{15-6} = 0b0000000000;
1054 } // neverHasSideEffects
1056 // Multiply register
1057 let isCommutable = 1 in
1058 def tMUL : // A8.6.105 T1
1059 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1061 "mul", "\t$Rdn, $Rm, $Rdn",
1062 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1064 // Move inverse register
1065 def tMVN : // A8.6.107
1066 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1067 "mvn", "\t$Rd, $Rn",
1068 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1070 // Bitwise or register
1071 let isCommutable = 1 in
1072 def tORR : // A8.6.114
1073 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1075 "orr", "\t$Rdn, $Rm",
1076 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1079 def tREV : // A8.6.134
1080 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1082 "rev", "\t$Rd, $Rm",
1083 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1084 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1086 def tREV16 : // A8.6.135
1087 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1089 "rev16", "\t$Rd, $Rm",
1090 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1091 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1093 def tREVSH : // A8.6.136
1094 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1096 "revsh", "\t$Rd, $Rm",
1097 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1098 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1100 // Rotate right register
1101 def tROR : // A8.6.139
1102 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1104 "ror", "\t$Rdn, $Rm",
1105 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1108 def tRSB : // A8.6.141
1109 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1111 "rsb", "\t$Rd, $Rn, #0",
1112 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1114 // Subtract with carry register
1115 let Uses = [CPSR] in
1116 def tSBC : // A8.6.151
1117 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1119 "sbc", "\t$Rdn, $Rm",
1120 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1122 // Subtract immediate
1123 def tSUBi3 : // A8.6.210 T1
1124 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1126 "sub", "\t$Rd, $Rm, $imm3",
1127 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1129 let Inst{8-6} = imm3;
1132 def tSUBi8 : // A8.6.210 T2
1133 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1135 "sub", "\t$Rdn, $imm8",
1136 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1138 // Subtract register
1139 def tSUBrr : // A8.6.212
1140 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1142 "sub", "\t$Rd, $Rn, $Rm",
1143 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1145 // TODO: A7-96: STMIA - store multiple.
1148 def tSXTB : // A8.6.222
1149 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1151 "sxtb", "\t$Rd, $Rm",
1152 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1153 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1155 // Sign-extend short
1156 def tSXTH : // A8.6.224
1157 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1159 "sxth", "\t$Rd, $Rm",
1160 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1161 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1164 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1165 def tTST : // A8.6.230
1166 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1167 "tst", "\t$Rn, $Rm",
1168 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1171 def tUXTB : // A8.6.262
1172 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1174 "uxtb", "\t$Rd, $Rm",
1175 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1176 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1178 // Zero-extend short
1179 def tUXTH : // A8.6.264
1180 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1182 "uxth", "\t$Rd, $Rm",
1183 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1184 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1186 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1187 // Expanded after instruction selection into a branch sequence.
1188 let usesCustomInserter = 1 in // Expanded after instruction selection.
1189 def tMOVCCr_pseudo :
1190 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1192 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1194 // tLEApcrel - Load a pc-relative address into a register without offending the
1197 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1198 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1199 T1Encoding<{1,0,1,0,0,?}> {
1202 let Inst{10-8} = Rd;
1203 let Inst{7-0} = addr;
1206 let neverHasSideEffects = 1, isReMaterializable = 1 in
1207 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1210 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1211 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1214 //===----------------------------------------------------------------------===//
1218 // __aeabi_read_tp preserves the registers r1-r3.
1219 // This is a pseudo inst so that we can get the encoding right,
1220 // complete with fixup for the aeabi_read_tp function.
1221 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1222 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1223 [(set R0, ARMthread_pointer)]>;
1225 //===----------------------------------------------------------------------===//
1226 // SJLJ Exception handling intrinsics
1229 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1230 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1231 // from some other function to get here, and we're using the stack frame for the
1232 // containing function to save/restore registers, we can't keep anything live in
1233 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1234 // tromped upon when we get here from a longjmp(). We force everything out of
1235 // registers except for our own input by listing the relevant registers in
1236 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1237 // preserve all of the callee-saved resgisters, which is exactly what we want.
1238 // $val is a scratch register for our use.
1239 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1240 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1241 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1242 AddrModeNone, 0, NoItinerary, "","",
1243 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1245 // FIXME: Non-Darwin version(s)
1246 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1247 Defs = [ R7, LR, SP ] in
1248 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1249 AddrModeNone, 0, IndexModeNone,
1250 Pseudo, NoItinerary, "", "",
1251 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1252 Requires<[IsThumb, IsDarwin]>;
1254 //===----------------------------------------------------------------------===//
1255 // Non-Instruction Patterns
1259 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1260 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1261 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1262 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1265 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1266 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1267 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1268 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1269 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1270 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1272 // Subtract with carry
1273 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1274 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1275 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1276 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1277 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1278 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1280 // ConstantPool, GlobalAddress
1281 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1282 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1285 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1286 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1289 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1290 Requires<[IsThumb, IsNotDarwin]>;
1291 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1292 Requires<[IsThumb, IsDarwin]>;
1294 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1295 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1296 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1297 Requires<[IsThumb, HasV5T, IsDarwin]>;
1299 // Indirect calls to ARM routines
1300 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1301 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1302 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1303 Requires<[IsThumb, HasV5T, IsDarwin]>;
1305 // zextload i1 -> zextload i8
1306 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1307 (tLDRBr t_addrmode_rrs1:$addr)>;
1308 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1309 (tLDRBi t_addrmode_is1:$addr)>;
1311 // extload -> zextload
1312 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1313 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1314 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1315 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1316 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1317 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1319 // If it's impossible to use [r,r] address mode for sextload, select to
1320 // ldr{b|h} + sxt{b|h} instead.
1321 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1322 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1323 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1324 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1325 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1326 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1327 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1328 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1329 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1330 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1331 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1332 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1334 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1335 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1336 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1337 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1338 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1339 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1340 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1341 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1343 // Large immediate handling.
1346 def : T1Pat<(i32 thumb_immshifted:$src),
1347 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1348 (thumb_immshifted_shamt imm:$src))>;
1350 def : T1Pat<(i32 imm0_255_comp:$src),
1351 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1353 // Pseudo instruction that combines ldr from constpool and add pc. This should
1354 // be expanded into two instructions late to allow if-conversion and
1356 let isReMaterializable = 1 in
1357 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1359 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1361 Requires<[IsThumb, IsThumb1Only]>;
1363 // Pseudo-instruction for merged POP and return.
1364 // FIXME: remove when we have a way to marking a MI with these properties.
1365 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1366 hasExtraDefRegAllocReq = 1 in
1367 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1369 (tPOP pred:$p, reglist:$regs)>;
1371 // Indirect branch using "mov pc, $Rm"
1372 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1373 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1374 2, IIC_Br, [(brind GPR:$Rm)],
1375 (tMOVr PC, GPR:$Rm, pred:$p)>;