1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 // TI - Thumb instruction.
23 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
28 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
32 class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, cstr> {
37 let OperandList = ops;
39 let Pattern = pattern;
40 list<Predicate> Predicates = [IsThumb];
43 class TI<dag ops, string asm, list<dag> pattern>
44 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
45 class TI1<dag ops, string asm, list<dag> pattern>
46 : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
47 class TI2<dag ops, string asm, list<dag> pattern>
48 : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
49 class TI4<dag ops, string asm, list<dag> pattern>
50 : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
51 class TIs<dag ops, string asm, list<dag> pattern>
52 : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
54 // Two-address instructions
55 class TIt<dag ops, string asm, list<dag> pattern>
56 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
58 // BL, BLX(1) are translated by assembler into two instructions
59 class TIx2<dag ops, string asm, list<dag> pattern>
60 : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
63 class TJTI<dag ops, string asm, list<dag> pattern>
64 : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
66 def imm_neg_XFORM : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
69 def imm_comp_XFORM : SDNodeXForm<imm, [{
70 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
74 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
75 def imm0_7 : PatLeaf<(i32 imm), [{
76 return (uint32_t)N->getValue() < 8;
78 def imm0_7_neg : PatLeaf<(i32 imm), [{
79 return (uint32_t)-N->getValue() < 8;
82 def imm0_255 : PatLeaf<(i32 imm), [{
83 return (uint32_t)N->getValue() < 256;
85 def imm0_255_comp : PatLeaf<(i32 imm), [{
86 return ~((uint32_t)N->getValue()) < 256;
89 def imm8_255 : PatLeaf<(i32 imm), [{
90 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
92 def imm8_255_neg : PatLeaf<(i32 imm), [{
93 unsigned Val = -N->getValue();
94 return Val >= 8 && Val < 256;
97 // Break imm's up into two pieces: an immediate + a left shift.
98 // This uses thumb_immshifted to match and thumb_immshifted_val and
99 // thumb_immshifted_shamt to get the val/shift pieces.
100 def thumb_immshifted : PatLeaf<(imm), [{
101 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
104 def thumb_immshifted_val : SDNodeXForm<imm, [{
105 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
106 return CurDAG->getTargetConstant(V, MVT::i32);
109 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
110 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
111 return CurDAG->getTargetConstant(V, MVT::i32);
114 // Define Thumb specific addressing modes.
116 // t_addrmode_rr := reg + reg
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let PrintMethod = "printThumbAddrModeRROperand";
121 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
124 // t_addrmode_s4 := reg + reg
127 def t_addrmode_s4 : Operand<i32>,
128 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
129 let PrintMethod = "printThumbAddrModeS4Operand";
130 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
133 // t_addrmode_s2 := reg + reg
136 def t_addrmode_s2 : Operand<i32>,
137 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
138 let PrintMethod = "printThumbAddrModeS2Operand";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
142 // t_addrmode_s1 := reg + reg
145 def t_addrmode_s1 : Operand<i32>,
146 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
147 let PrintMethod = "printThumbAddrModeS1Operand";
148 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
151 // t_addrmode_sp := sp + imm8 * 4
153 def t_addrmode_sp : Operand<i32>,
154 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
155 let PrintMethod = "printThumbAddrModeSPOperand";
156 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
159 //===----------------------------------------------------------------------===//
160 // Miscellaneous Instructions.
163 def tADJCALLSTACKUP :
164 PseudoInst<(ops i32imm:$amt),
165 "@ tADJCALLSTACKUP $amt",
166 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
168 def tADJCALLSTACKDOWN :
169 PseudoInst<(ops i32imm:$amt),
170 "@ tADJCALLSTACKDOWN $amt",
171 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
173 let isNotDuplicable = 1 in
174 def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
175 "$cp:\n\tadd $dst, pc",
176 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
178 //===----------------------------------------------------------------------===//
179 // Control Flow Instructions.
182 let isReturn = 1, isTerminator = 1 in {
183 def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
184 // Alternative return instruction used by vararg functions.
185 def tBX_RET_vararg : TI<(ops GPR:$dst), "bx $dst", []>;
188 // FIXME: remove when we have a way to marking a MI with these properties.
189 let isLoad = 1, isReturn = 1, isTerminator = 1 in
190 def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
193 let isCall = 1, noResults = 1,
194 Defs = [R0, R1, R2, R3, LR,
195 D0, D1, D2, D3, D4, D5, D6, D7] in {
196 def tBL : TIx2<(ops i32imm:$func, variable_ops),
198 [(ARMtcall tglobaladdr:$func)]>;
200 def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
202 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
203 def tBLXr : TI<(ops GPR:$dst, variable_ops),
205 [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
207 def tBX : TIx2<(ops GPR:$dst, variable_ops),
208 "cpy lr, pc\n\tbx $dst",
209 [(ARMcall_nolink GPR:$dst)]>;
212 let isBranch = 1, isTerminator = 1, noResults = 1 in {
213 let isBarrier = 1 in {
214 let isPredicable = 1 in
215 def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
218 def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>;
220 def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
221 "cpy pc, $dst \n\t.align\t2\n$jt",
222 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
226 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
227 // a two-value operand where a dag node expects two operands. :(
228 let isBranch = 1, isTerminator = 1, noResults = 1 in
229 def tBcc : TI<(ops brtarget:$dst, pred:$cc), "b$cc $dst",
230 [/*(ARMbrcond bb:$dst, imm:$cc)*/]>;
232 //===----------------------------------------------------------------------===//
233 // Load Store Instructions.
237 def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
239 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
241 def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
243 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
245 def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
247 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
249 def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
251 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
253 def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
255 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
257 def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
259 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
261 // Special instruction for restore. It cannot clobber condition register
262 // when it's expanded by eliminateCallFramePseudoInstr().
263 def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
264 "ldr $dst, $addr", []>;
267 def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
269 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
271 // Special LDR for loads from non-pc-relative constpools.
272 let isReMaterializable = 1 in
273 def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr),
274 "ldr $dst, $addr", []>;
278 def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
280 [(store GPR:$src, t_addrmode_s4:$addr)]>;
282 def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
284 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
286 def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
288 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
290 def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
292 [(store GPR:$src, t_addrmode_sp:$addr)]>;
294 // Special instruction for spill. It cannot clobber condition register
295 // when it's expanded by eliminateCallFramePseudoInstr().
296 def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
297 "str $src, $addr", []>;
300 //===----------------------------------------------------------------------===//
301 // Load / store multiple Instructions.
304 // TODO: A7-44: LDMIA - load multiple
307 def tPOP : TI<(ops reglist:$dst1, variable_ops),
311 def tPUSH : TI<(ops reglist:$src1, variable_ops),
314 //===----------------------------------------------------------------------===//
315 // Arithmetic Instructions.
319 def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
321 [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
323 def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
324 "add $dst, $lhs, $rhs",
325 [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
328 def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
329 "add $dst, $lhs, $rhs",
330 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
332 def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
334 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
336 def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
337 "add $dst, $lhs, $rhs",
338 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
340 def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
341 "add $dst, $rhs", []>;
343 def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
344 "add $dst, pc, $rhs * 4", []>;
345 def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
346 "add $dst, $sp, $rhs * 4", []>;
347 def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
348 "add $dst, $rhs * 4", []>;
350 def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
352 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
354 def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
355 "asr $dst, $lhs, $rhs",
356 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
358 def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
360 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
362 def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
364 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
367 def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
369 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
371 def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
373 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
375 def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
377 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
379 def tTST : TI<(ops GPR:$lhs, GPR:$rhs),
381 [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
383 def tCMNNZ : TI<(ops GPR:$lhs, GPR:$rhs),
385 [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
387 def tCMPNZi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
389 [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
391 def tCMPNZr : TI<(ops GPR:$lhs, GPR:$rhs),
393 [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
395 // TODO: A7-37: CMP(3) - cmp hi regs
397 def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
399 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
401 def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
402 "lsl $dst, $lhs, $rhs",
403 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
405 def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
407 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
409 def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
410 "lsr $dst, $lhs, $rhs",
411 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
413 def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
415 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
417 // FIXME: This is not rematerializable because mov changes the condition code.
418 def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src),
420 [(set GPR:$dst, imm0_255:$src)]>;
422 // TODO: A7-73: MOV(2) - mov setting flag.
425 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
426 // which is MOV(3). This also supports high registers.
427 def tMOVr : TI<(ops GPR:$dst, GPR:$src),
428 "cpy $dst, $src", []>;
430 def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
432 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
434 def tMVN : TI<(ops GPR:$dst, GPR:$src),
436 [(set GPR:$dst, (not GPR:$src))]>;
438 def tNEG : TI<(ops GPR:$dst, GPR:$src),
440 [(set GPR:$dst, (ineg GPR:$src))]>;
442 def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
444 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
447 def tREV : TI<(ops GPR:$dst, GPR:$src),
449 [(set GPR:$dst, (bswap GPR:$src))]>,
450 Requires<[IsThumb, HasV6]>;
452 def tREV16 : TI<(ops GPR:$dst, GPR:$src),
455 (or (and (srl GPR:$src, 8), 0xFF),
456 (or (and (shl GPR:$src, 8), 0xFF00),
457 (or (and (srl GPR:$src, 8), 0xFF0000),
458 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
459 Requires<[IsThumb, HasV6]>;
461 def tREVSH : TI<(ops GPR:$dst, GPR:$src),
465 (or (srl (and GPR:$src, 0xFFFF), 8),
466 (shl GPR:$src, 8)), i16))]>,
467 Requires<[IsThumb, HasV6]>;
469 def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
471 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
474 // Subtract with carry
475 def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
477 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
479 def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
480 "sub $dst, $lhs, $rhs",
481 [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
484 // TODO: A7-96: STMIA - store multiple.
486 def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
487 "sub $dst, $lhs, $rhs",
488 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
490 def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
492 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
494 def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
495 "sub $dst, $lhs, $rhs",
496 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
498 def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
499 "sub $dst, $rhs * 4", []>;
501 def tSXTB : TI<(ops GPR:$dst, GPR:$src),
503 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
504 Requires<[IsThumb, HasV6]>;
505 def tSXTH : TI<(ops GPR:$dst, GPR:$src),
507 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
508 Requires<[IsThumb, HasV6]>;
511 def tUXTB : TI<(ops GPR:$dst, GPR:$src),
513 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
514 Requires<[IsThumb, HasV6]>;
515 def tUXTH : TI<(ops GPR:$dst, GPR:$src),
517 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
518 Requires<[IsThumb, HasV6]>;
521 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
522 // Expanded by the scheduler into a branch sequence.
523 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
525 PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, pred:$cc),
527 [/*(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))*/]>;
529 // tLEApcrel - Load a pc-relative address into a register without offending the
531 def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
532 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
533 "${:private}PCRELL${:uid}+4))\n"),
534 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
535 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
538 def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
539 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
540 "${:private}PCRELL${:uid}+4))\n"),
541 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
542 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
545 //===----------------------------------------------------------------------===//
549 // __aeabi_read_tp preserves the registers r1-r3.
552 def tTPsoft : TIx2<(ops),
553 "bl __aeabi_read_tp",
554 [(set R0, ARMthread_pointer)]>;
557 //===----------------------------------------------------------------------===//
558 // Non-Instruction Patterns
561 // ConstantPool, GlobalAddress
562 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
563 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
566 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
567 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
570 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
571 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
573 // Indirect calls to ARM routines
574 def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
576 // zextload i1 -> zextload i8
577 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
578 (tLDRB t_addrmode_s1:$addr)>;
580 // extload -> zextload
581 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
582 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
583 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
585 // truncstore i1 -> truncstore i8
586 def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
587 (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
589 // Large immediate handling.
592 def : ThumbPat<(i32 thumb_immshifted:$src),
593 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
594 (thumb_immshifted_shamt imm:$src))>;
596 def : ThumbPat<(i32 imm0_255_comp:$src),
597 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;