1 //===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm_s4 : Operand<i32> {
82 let PrintMethod = "printThumbS4ImmOperand";
83 let OperandType = "OPERAND_IMMEDIATE";
86 // Define Thumb specific addressing modes.
88 let OperandType = "OPERAND_PCREL" in {
89 def t_brtarget : Operand<OtherVT> {
90 let EncoderMethod = "getThumbBRTargetOpValue";
91 let DecoderMethod = "DecodeThumbBROperand";
94 def t_bcctarget : Operand<i32> {
95 let EncoderMethod = "getThumbBCCTargetOpValue";
96 let DecoderMethod = "DecodeThumbBCCTargetOperand";
99 def t_cbtarget : Operand<i32> {
100 let EncoderMethod = "getThumbCBTargetOpValue";
101 let DecoderMethod = "DecodeThumbCmpBROperand";
104 def t_bltarget : Operand<i32> {
105 let EncoderMethod = "getThumbBLTargetOpValue";
106 let DecoderMethod = "DecodeThumbBLTargetOperand";
109 def t_blxtarget : Operand<i32> {
110 let EncoderMethod = "getThumbBLXTargetOpValue";
111 let DecoderMethod = "DecodeThumbBLXOffset";
115 // t_addrmode_rr := reg + reg
117 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
121 let PrintMethod = "printThumbAddrModeRROperand";
122 let DecoderMethod = "DecodeThumbAddrModeRR";
123 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
126 // t_addrmode_rrs := reg + reg
128 // We use separate scaled versions because the Select* functions need
129 // to explicitly check for a matching constant and return false here so that
130 // the reg+imm forms will match instead. This is a horrible way to do that,
131 // as it forces tight coupling between the methods, but it's how selectiondag
133 def t_addrmode_rrs1 : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
135 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
136 let PrintMethod = "printThumbAddrModeRROperand";
137 let DecoderMethod = "DecodeThumbAddrModeRR";
138 let ParserMatchClass = t_addrmode_rr_asm_operand;
139 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141 def t_addrmode_rrs2 : Operand<i32>,
142 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
143 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
144 let DecoderMethod = "DecodeThumbAddrModeRR";
145 let PrintMethod = "printThumbAddrModeRROperand";
146 let ParserMatchClass = t_addrmode_rr_asm_operand;
147 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
149 def t_addrmode_rrs4 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
151 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
152 let DecoderMethod = "DecodeThumbAddrModeRR";
153 let PrintMethod = "printThumbAddrModeRROperand";
154 let ParserMatchClass = t_addrmode_rr_asm_operand;
155 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
158 // t_addrmode_is4 := reg + imm5 * 4
160 def t_addrmode_is4 : Operand<i32>,
161 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
162 let EncoderMethod = "getAddrModeISOpValue";
163 let DecoderMethod = "DecodeThumbAddrModeIS";
164 let PrintMethod = "printThumbAddrModeImm5S4Operand";
165 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
168 // t_addrmode_is2 := reg + imm5 * 2
170 def t_addrmode_is2 : Operand<i32>,
171 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
172 let EncoderMethod = "getAddrModeISOpValue";
173 let DecoderMethod = "DecodeThumbAddrModeIS";
174 let PrintMethod = "printThumbAddrModeImm5S2Operand";
175 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
178 // t_addrmode_is1 := reg + imm5
180 def t_addrmode_is1 : Operand<i32>,
181 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
182 let EncoderMethod = "getAddrModeISOpValue";
183 let DecoderMethod = "DecodeThumbAddrModeIS";
184 let PrintMethod = "printThumbAddrModeImm5S1Operand";
185 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
188 // t_addrmode_sp := sp + imm8 * 4
190 def t_addrmode_sp : Operand<i32>,
191 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
192 let EncoderMethod = "getAddrModeThumbSPOpValue";
193 let DecoderMethod = "DecodeThumbAddrModeSP";
194 let PrintMethod = "printThumbAddrModeSPOperand";
195 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
198 // t_addrmode_pc := <label> => pc + imm8 * 4
200 def t_addrmode_pc : Operand<i32> {
201 let EncoderMethod = "getAddrModePCOpValue";
202 let DecoderMethod = "DecodeThumbAddrModePC";
205 //===----------------------------------------------------------------------===//
206 // Miscellaneous Instructions.
209 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
210 // from removing one half of the matched pairs. That breaks PEI, which assumes
211 // these will always be in pairs, and asserts if it finds otherwise. Better way?
212 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
213 def tADJCALLSTACKUP :
214 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
215 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
216 Requires<[IsThumb, IsThumb1Only]>;
218 def tADJCALLSTACKDOWN :
219 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
220 [(ARMcallseq_start imm:$amt)]>,
221 Requires<[IsThumb, IsThumb1Only]>;
224 class T1SystemEncoding<bits<8> opc>
225 : T1Encoding<0b101111> {
226 let Inst{9-8} = 0b11;
230 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
231 T1SystemEncoding<0x00>; // A8.6.110
233 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
234 T1SystemEncoding<0x10>; // A8.6.410
236 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
237 T1SystemEncoding<0x20>; // A8.6.408
239 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
240 T1SystemEncoding<0x30>; // A8.6.409
242 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
243 T1SystemEncoding<0x40>; // A8.6.157
245 // The imm operand $val can be used by a debugger to store more information
246 // about the breakpoint.
247 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
249 T1Encoding<0b101111> {
250 let Inst{9-8} = 0b10;
256 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
257 []>, T1Encoding<0b101101> {
260 let Inst{9-5} = 0b10010;
263 let Inst{2-0} = 0b000;
266 // Change Processor State is a system instruction -- for disassembly only.
267 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
268 NoItinerary, "cps$imod $iflags",
269 [/* For disassembly only; pattern left blank */]>,
277 let Inst{2-0} = iflags;
278 let DecoderMethod = "DecodeThumbCPS";
281 // For both thumb1 and thumb2.
282 let isNotDuplicable = 1, isCodeGenOnly = 1 in
283 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
284 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
285 T1Special<{0,0,?,?}> {
288 let Inst{6-3} = 0b1111; // Rm = pc
292 // ADD <Rd>, sp, #<imm8>
293 // This is rematerializable, which is particularly useful for taking the
294 // address of locals.
295 let isReMaterializable = 1 in
296 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
297 "add\t$dst, $sp, $rhs", []>,
298 T1Encoding<{1,0,1,0,1,?}> {
302 let Inst{10-8} = dst;
304 let DecoderMethod = "DecodeThumbAddSpecialReg";
307 // ADD sp, sp, #<imm7>
308 def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
309 "add\t$dst, $rhs", []>,
310 T1Misc<{0,0,0,0,0,?,?}> {
314 let DecoderMethod = "DecodeThumbAddSPImm";
317 // SUB sp, sp, #<imm7>
318 // FIXME: The encoding and the ASM string don't match up.
319 def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
320 "sub\t$dst, $rhs", []>,
321 T1Misc<{0,0,0,0,1,?,?}> {
325 let DecoderMethod = "DecodeThumbAddSPImm";
329 def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
330 "add\t$dst, $rhs", []>,
331 T1Special<{0,0,?,?}> {
332 // A8.6.9 Encoding T1
334 let Inst{7} = dst{3};
335 let Inst{6-3} = 0b1101;
336 let Inst{2-0} = dst{2-0};
337 let DecoderMethod = "DecodeThumbAddSPReg";
341 def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
342 "add\t$dst, $rhs", []>,
343 T1Special<{0,0,?,?}> {
344 // A8.6.9 Encoding T2
348 let Inst{2-0} = 0b101;
349 let DecoderMethod = "DecodeThumbAddSPReg";
352 //===----------------------------------------------------------------------===//
353 // Control Flow Instructions.
357 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
358 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
359 T1Special<{1,1,0,?}> {
363 let Inst{2-0} = 0b000;
367 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
368 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
369 [(ARMretflag)], (tBX LR, pred:$p)>;
371 // Alternative return instruction used by vararg functions.
372 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
374 (tBX GPR:$Rm, pred:$p)>;
377 // All calls clobber the non-callee saved registers. SP is marked as a use to
378 // prevent stack-pointer assignments that appear immediately before calls from
379 // potentially appearing dead.
381 // On non-Darwin platforms R9 is callee-saved.
382 Defs = [R0, R1, R2, R3, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
384 // Also used for Thumb2
385 def tBL : TIx2<0b11110, 0b11, 1,
386 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
388 [(ARMtcall tglobaladdr:$func)]>,
389 Requires<[IsThumb, IsNotDarwin]> {
391 let Inst{26} = func{21};
392 let Inst{25-16} = func{20-11};
395 let Inst{10-0} = func{10-0};
398 // ARMv5T and above, also used for Thumb2
399 def tBLXi : TIx2<0b11110, 0b11, 0,
400 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
402 [(ARMcall tglobaladdr:$func)]>,
403 Requires<[IsThumb, HasV5T, IsNotDarwin]> {
405 let Inst{25-16} = func{20-11};
408 let Inst{10-1} = func{10-1};
409 let Inst{0} = 0; // func{0} is assumed zero
412 // Also used for Thumb2
413 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
415 [(ARMtcall GPR:$func)]>,
416 Requires<[IsThumb, HasV5T, IsNotDarwin]>,
417 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
419 let Inst{6-3} = func;
420 let Inst{2-0} = 0b000;
424 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
426 [(ARMcall_nolink tGPR:$func)]>,
427 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
431 // On Darwin R9 is call-clobbered.
432 // R7 is marked as a use to prevent frame-pointer assignments from being
433 // moved above / below calls.
434 Defs = [R0, R1, R2, R3, R9, R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
436 // Also used for Thumb2
437 def tBLr9 : tPseudoExpand<(outs), (ins pred:$p, t_bltarget:$func, variable_ops),
438 4, IIC_Br, [(ARMtcall tglobaladdr:$func)],
439 (tBL pred:$p, t_bltarget:$func)>,
440 Requires<[IsThumb, IsDarwin]>;
442 // ARMv5T and above, also used for Thumb2
443 def tBLXi_r9 : tPseudoExpand<(outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
444 4, IIC_Br, [(ARMcall tglobaladdr:$func)],
445 (tBLXi pred:$p, t_blxtarget:$func)>,
446 Requires<[IsThumb, HasV5T, IsDarwin]>;
448 // Also used for Thumb2
449 def tBLXr_r9 : tPseudoExpand<(outs), (ins pred:$p, GPR:$func, variable_ops),
450 2, IIC_Br, [(ARMtcall GPR:$func)],
451 (tBLXr pred:$p, GPR:$func)>,
452 Requires<[IsThumb, HasV5T, IsDarwin]>;
455 def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
457 [(ARMcall_nolink tGPR:$func)]>,
458 Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
461 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
462 let isPredicable = 1 in
463 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
464 "b\t$target", [(br bb:$target)]>,
465 T1Encoding<{1,1,1,0,0,?}> {
467 let Inst{10-0} = target;
471 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
472 // the clobber of LR.
474 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
475 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
477 def tBR_JTr : tPseudoInst<(outs),
478 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
480 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
481 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
485 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
486 // a two-value operand where a dag node expects two operands. :(
487 let isBranch = 1, isTerminator = 1 in
488 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
490 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
491 T1BranchCond<{1,1,0,1}> {
495 let Inst{7-0} = target;
499 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
501 let Defs = [R0, R1, R2, R3, R9, R12, QQQQ0, QQQQ2, QQQQ3, PC],
503 // tTAILJMPd: Darwin version uses a Thumb2 branch (no Thumb1 tail calls
504 // on Darwin), so it's in ARMInstrThumb2.td.
505 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
507 (tBX GPR:$dst, (ops 14, zero_reg))>,
508 Requires<[IsThumb, IsDarwin]>;
510 // Non-Darwin versions (the difference is R9).
511 let Defs = [R0, R1, R2, R3, R12, QQQQ0, QQQQ2, QQQQ3, PC],
513 def tTAILJMPdND : tPseudoExpand<(outs), (ins t_brtarget:$dst, variable_ops),
515 (tB t_brtarget:$dst)>,
516 Requires<[IsThumb, IsNotDarwin]>;
517 def tTAILJMPrND : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
519 (tBX GPR:$dst, (ops 14, zero_reg))>,
520 Requires<[IsThumb, IsNotDarwin]>;
525 // A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
526 // A8.6.16 B: Encoding T1
527 // If Inst{11-8} == 0b1111 then SEE SVC
528 let isCall = 1, Uses = [SP] in
529 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
530 "svc", "\t$imm", []>, Encoding16 {
532 let Inst{15-12} = 0b1101;
533 let Inst{11-8} = 0b1111;
537 // The assembler uses 0xDEFE for a trap instruction.
538 let isBarrier = 1, isTerminator = 1 in
539 def tTRAP : TI<(outs), (ins), IIC_Br,
540 "trap", [(trap)]>, Encoding16 {
544 //===----------------------------------------------------------------------===//
545 // Load Store Instructions.
548 // Loads: reg/reg and reg/imm5
549 let canFoldAsLoad = 1, isReMaterializable = 1 in
550 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
551 Operand AddrMode_r, Operand AddrMode_i,
552 AddrMode am, InstrItinClass itin_r,
553 InstrItinClass itin_i, string asm,
556 T1pILdStEncode<reg_opc,
557 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
558 am, itin_r, asm, "\t$Rt, $addr",
559 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
561 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
562 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
563 am, itin_i, asm, "\t$Rt, $addr",
564 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
566 // Stores: reg/reg and reg/imm5
567 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
568 Operand AddrMode_r, Operand AddrMode_i,
569 AddrMode am, InstrItinClass itin_r,
570 InstrItinClass itin_i, string asm,
573 T1pILdStEncode<reg_opc,
574 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
575 am, itin_r, asm, "\t$Rt, $addr",
576 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
578 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
579 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
580 am, itin_i, asm, "\t$Rt, $addr",
581 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
585 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
586 t_addrmode_is4, AddrModeT1_4,
587 IIC_iLoad_r, IIC_iLoad_i, "ldr",
588 UnOpFrag<(load node:$Src)>>;
591 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
592 t_addrmode_is1, AddrModeT1_1,
593 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
594 UnOpFrag<(zextloadi8 node:$Src)>>;
597 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
598 t_addrmode_is2, AddrModeT1_2,
599 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
600 UnOpFrag<(zextloadi16 node:$Src)>>;
602 let AddedComplexity = 10 in
603 def tLDRSB : // A8.6.80
604 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
605 AddrModeT1_1, IIC_iLoad_bh_r,
606 "ldrsb", "\t$Rt, $addr",
607 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
609 let AddedComplexity = 10 in
610 def tLDRSH : // A8.6.84
611 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
612 AddrModeT1_2, IIC_iLoad_bh_r,
613 "ldrsh", "\t$Rt, $addr",
614 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
616 let canFoldAsLoad = 1 in
617 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
618 "ldr", "\t$Rt, $addr",
619 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
624 let Inst{7-0} = addr;
628 // FIXME: Use ldr.n to work around a Darwin assembler bug.
629 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
630 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
631 "ldr", ".n\t$Rt, $addr",
632 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
633 T1Encoding<{0,1,0,0,1,?}> {
638 let Inst{7-0} = addr;
641 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
642 // For disassembly use only.
643 def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
644 "ldr", "\t$Rt, $addr",
645 [/* disassembly only */]>,
646 T1Encoding<{0,1,0,0,1,?}> {
651 let Inst{7-0} = addr;
654 // A8.6.194 & A8.6.192
655 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
656 t_addrmode_is4, AddrModeT1_4,
657 IIC_iStore_r, IIC_iStore_i, "str",
658 BinOpFrag<(store node:$LHS, node:$RHS)>>;
660 // A8.6.197 & A8.6.195
661 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
662 t_addrmode_is1, AddrModeT1_1,
663 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
664 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
666 // A8.6.207 & A8.6.205
667 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
668 t_addrmode_is2, AddrModeT1_2,
669 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
670 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
673 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
674 "str", "\t$Rt, $addr",
675 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
680 let Inst{7-0} = addr;
683 //===----------------------------------------------------------------------===//
684 // Load / store multiple Instructions.
687 multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
688 InstrItinClass itin_upd, bits<6> T1Enc,
689 bit L_bit, string baseOpc> {
691 T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
692 itin, !strconcat(asm, "${p}\t$Rn, $regs"), []>,
697 let Inst{7-0} = regs;
701 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
702 "$Rn = $wb", itin_upd>,
703 PseudoInstExpansion<(!cast<Instruction>(!strconcat(baseOpc, "IA"))
704 tGPR:$Rn, pred:$p, reglist:$regs)> {
706 let OutOperandList = (outs GPR:$wb);
707 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
709 let isCodeGenOnly = 1;
711 list<Predicate> Predicates = [IsThumb];
715 // These require base address to be written back or one of the loaded regs.
716 let neverHasSideEffects = 1 in {
718 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
719 defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
720 {1,1,0,0,1,?}, 1, "tLDM">;
722 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
723 defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
724 {1,1,0,0,0,?}, 0, "tSTM">;
726 } // neverHasSideEffects
728 def : InstAlias<"ldm${p} $Rn!, $regs",
729 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
730 Requires<[IsThumb, IsThumb1Only]>;
733 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
734 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
736 "pop${p}\t$regs", []>,
737 T1Misc<{1,1,0,?,?,?,?}> {
739 let Inst{8} = regs{15};
740 let Inst{7-0} = regs{7-0};
743 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
744 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
746 "push${p}\t$regs", []>,
747 T1Misc<{0,1,0,?,?,?,?}> {
749 let Inst{8} = regs{14};
750 let Inst{7-0} = regs{7-0};
753 //===----------------------------------------------------------------------===//
754 // Arithmetic Instructions.
757 // Helper classes for encoding T1pI patterns:
758 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
759 string opc, string asm, list<dag> pattern>
760 : T1pI<oops, iops, itin, opc, asm, pattern>,
761 T1DataProcessing<opA> {
767 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
768 string opc, string asm, list<dag> pattern>
769 : T1pI<oops, iops, itin, opc, asm, pattern>,
777 // Helper classes for encoding T1sI patterns:
778 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
779 string opc, string asm, list<dag> pattern>
780 : T1sI<oops, iops, itin, opc, asm, pattern>,
781 T1DataProcessing<opA> {
787 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
788 string opc, string asm, list<dag> pattern>
789 : T1sI<oops, iops, itin, opc, asm, pattern>,
798 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
799 string opc, string asm, list<dag> pattern>
800 : T1sI<oops, iops, itin, opc, asm, pattern>,
808 // Helper classes for encoding T1sIt patterns:
809 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
810 string opc, string asm, list<dag> pattern>
811 : T1sIt<oops, iops, itin, opc, asm, pattern>,
812 T1DataProcessing<opA> {
818 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
819 string opc, string asm, list<dag> pattern>
820 : T1sIt<oops, iops, itin, opc, asm, pattern>,
824 let Inst{10-8} = Rdn;
825 let Inst{7-0} = imm8;
828 // Add with carry register
829 let isCommutable = 1, Uses = [CPSR] in
831 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
832 "adc", "\t$Rdn, $Rm",
833 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
836 def tADDi3 : // A8.6.4 T1
837 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
839 "add", "\t$Rd, $Rm, $imm3",
840 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
842 let Inst{8-6} = imm3;
845 def tADDi8 : // A8.6.4 T2
846 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
847 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
848 "add", "\t$Rdn, $imm8",
849 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
852 let isCommutable = 1 in
853 def tADDrr : // A8.6.6 T1
854 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
856 "add", "\t$Rd, $Rn, $Rm",
857 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
859 let neverHasSideEffects = 1 in
860 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
861 "add", "\t$Rdn, $Rm", []>,
862 T1Special<{0,0,?,?}> {
866 let Inst{7} = Rdn{3};
868 let Inst{2-0} = Rdn{2-0};
872 let isCommutable = 1 in
873 def tAND : // A8.6.12
874 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
876 "and", "\t$Rdn, $Rm",
877 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
880 def tASRri : // A8.6.14
881 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
883 "asr", "\t$Rd, $Rm, $imm5",
884 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
886 let Inst{10-6} = imm5;
890 def tASRrr : // A8.6.15
891 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
893 "asr", "\t$Rdn, $Rm",
894 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
897 def tBIC : // A8.6.20
898 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
900 "bic", "\t$Rdn, $Rm",
901 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
904 let isCompare = 1, Defs = [CPSR] in {
905 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
906 // Compare-to-zero still works out, just not the relationals
907 //def tCMN : // A8.6.33
908 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
910 // "cmn", "\t$lhs, $rhs",
911 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
913 def tCMNz : // A8.6.33
914 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
917 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
919 } // isCompare = 1, Defs = [CPSR]
922 let isCompare = 1, Defs = [CPSR] in {
923 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
924 "cmp", "\t$Rn, $imm8",
925 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
926 T1General<{1,0,1,?,?}> {
931 let Inst{7-0} = imm8;
935 def tCMPr : // A8.6.36 T1
936 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
939 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
941 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
942 "cmp", "\t$Rn, $Rm", []>,
943 T1Special<{0,1,?,?}> {
949 let Inst{2-0} = Rn{2-0};
951 } // isCompare = 1, Defs = [CPSR]
955 let isCommutable = 1 in
956 def tEOR : // A8.6.45
957 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
959 "eor", "\t$Rdn, $Rm",
960 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
963 def tLSLri : // A8.6.88
964 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
966 "lsl", "\t$Rd, $Rm, $imm5",
967 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
969 let Inst{10-6} = imm5;
973 def tLSLrr : // A8.6.89
974 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
976 "lsl", "\t$Rdn, $Rm",
977 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
980 def tLSRri : // A8.6.90
981 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
983 "lsr", "\t$Rd, $Rm, $imm5",
984 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
986 let Inst{10-6} = imm5;
990 def tLSRrr : // A8.6.91
991 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
993 "lsr", "\t$Rdn, $Rm",
994 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
998 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
999 "mov", "\t$Rd, $imm8",
1000 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1001 T1General<{1,0,0,?,?}> {
1005 let Inst{10-8} = Rd;
1006 let Inst{7-0} = imm8;
1009 // A7-73: MOV(2) - mov setting flag.
1011 let neverHasSideEffects = 1 in {
1012 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1014 "mov", "\t$Rd, $Rm", "", []>,
1015 T1Special<{1,0,?,?}> {
1019 let Inst{7} = Rd{3};
1021 let Inst{2-0} = Rd{2-0};
1023 let Defs = [CPSR] in
1024 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1025 "movs\t$Rd, $Rm", []>, Encoding16 {
1029 let Inst{15-6} = 0b0000000000;
1033 } // neverHasSideEffects
1035 // Multiply register
1036 let isCommutable = 1 in
1037 def tMUL : // A8.6.105 T1
1038 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1040 "mul", "\t$Rdn, $Rm, $Rdn",
1041 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1043 // Move inverse register
1044 def tMVN : // A8.6.107
1045 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1046 "mvn", "\t$Rd, $Rn",
1047 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1049 // Bitwise or register
1050 let isCommutable = 1 in
1051 def tORR : // A8.6.114
1052 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1054 "orr", "\t$Rdn, $Rm",
1055 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1058 def tREV : // A8.6.134
1059 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1061 "rev", "\t$Rd, $Rm",
1062 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1063 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1065 def tREV16 : // A8.6.135
1066 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1068 "rev16", "\t$Rd, $Rm",
1069 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1070 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1072 def tREVSH : // A8.6.136
1073 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1075 "revsh", "\t$Rd, $Rm",
1076 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1077 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1079 // Rotate right register
1080 def tROR : // A8.6.139
1081 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1083 "ror", "\t$Rdn, $Rm",
1084 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1087 def tRSB : // A8.6.141
1088 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1090 "rsb", "\t$Rd, $Rn, #0",
1091 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1093 // Subtract with carry register
1094 let Uses = [CPSR] in
1095 def tSBC : // A8.6.151
1096 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1098 "sbc", "\t$Rdn, $Rm",
1099 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1101 // Subtract immediate
1102 def tSUBi3 : // A8.6.210 T1
1103 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1105 "sub", "\t$Rd, $Rm, $imm3",
1106 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1108 let Inst{8-6} = imm3;
1111 def tSUBi8 : // A8.6.210 T2
1112 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1114 "sub", "\t$Rdn, $imm8",
1115 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1117 // Subtract register
1118 def tSUBrr : // A8.6.212
1119 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1121 "sub", "\t$Rd, $Rn, $Rm",
1122 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1124 // TODO: A7-96: STMIA - store multiple.
1127 def tSXTB : // A8.6.222
1128 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1130 "sxtb", "\t$Rd, $Rm",
1131 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1132 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1134 // Sign-extend short
1135 def tSXTH : // A8.6.224
1136 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1138 "sxth", "\t$Rd, $Rm",
1139 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1140 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1143 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1144 def tTST : // A8.6.230
1145 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1146 "tst", "\t$Rn, $Rm",
1147 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1150 def tUXTB : // A8.6.262
1151 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1153 "uxtb", "\t$Rd, $Rm",
1154 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1155 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1157 // Zero-extend short
1158 def tUXTH : // A8.6.264
1159 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1161 "uxth", "\t$Rd, $Rm",
1162 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1163 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1165 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1166 // Expanded after instruction selection into a branch sequence.
1167 let usesCustomInserter = 1 in // Expanded after instruction selection.
1168 def tMOVCCr_pseudo :
1169 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1171 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1173 // tLEApcrel - Load a pc-relative address into a register without offending the
1176 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1177 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1178 T1Encoding<{1,0,1,0,0,?}> {
1181 let Inst{10-8} = Rd;
1182 let Inst{7-0} = addr;
1183 let DecoderMethod = "DecodeThumbAddSpecialReg";
1186 let neverHasSideEffects = 1, isReMaterializable = 1 in
1187 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1190 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1191 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1194 //===----------------------------------------------------------------------===//
1198 // __aeabi_read_tp preserves the registers r1-r3.
1199 // This is a pseudo inst so that we can get the encoding right,
1200 // complete with fixup for the aeabi_read_tp function.
1201 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1202 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1203 [(set R0, ARMthread_pointer)]>;
1205 //===----------------------------------------------------------------------===//
1206 // SJLJ Exception handling intrinsics
1209 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1210 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1211 // from some other function to get here, and we're using the stack frame for the
1212 // containing function to save/restore registers, we can't keep anything live in
1213 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1214 // tromped upon when we get here from a longjmp(). We force everything out of
1215 // registers except for our own input by listing the relevant registers in
1216 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1217 // preserve all of the callee-saved resgisters, which is exactly what we want.
1218 // $val is a scratch register for our use.
1219 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1220 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1221 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1222 AddrModeNone, 0, NoItinerary, "","",
1223 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1225 // FIXME: Non-Darwin version(s)
1226 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1227 Defs = [ R7, LR, SP ] in
1228 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1229 AddrModeNone, 0, IndexModeNone,
1230 Pseudo, NoItinerary, "", "",
1231 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1232 Requires<[IsThumb, IsDarwin]>;
1234 //===----------------------------------------------------------------------===//
1235 // Non-Instruction Patterns
1239 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1240 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1241 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1242 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1245 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1246 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1247 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1248 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1249 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1250 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1252 // Subtract with carry
1253 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1254 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1255 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1256 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1257 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1258 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1260 // ConstantPool, GlobalAddress
1261 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1262 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1265 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1266 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1269 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1270 Requires<[IsThumb, IsNotDarwin]>;
1271 def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1272 Requires<[IsThumb, IsDarwin]>;
1274 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1275 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1276 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1277 Requires<[IsThumb, HasV5T, IsDarwin]>;
1279 // Indirect calls to ARM routines
1280 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1281 Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1282 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1283 Requires<[IsThumb, HasV5T, IsDarwin]>;
1285 // zextload i1 -> zextload i8
1286 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1287 (tLDRBr t_addrmode_rrs1:$addr)>;
1288 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1289 (tLDRBi t_addrmode_is1:$addr)>;
1291 // extload -> zextload
1292 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1293 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1294 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1295 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1296 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1297 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1299 // If it's impossible to use [r,r] address mode for sextload, select to
1300 // ldr{b|h} + sxt{b|h} instead.
1301 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1302 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1303 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1304 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1305 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1306 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1307 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1308 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1309 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1310 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1311 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1312 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1314 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1315 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1316 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1317 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1318 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1319 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1320 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1321 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1323 // Large immediate handling.
1326 def : T1Pat<(i32 thumb_immshifted:$src),
1327 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1328 (thumb_immshifted_shamt imm:$src))>;
1330 def : T1Pat<(i32 imm0_255_comp:$src),
1331 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1333 // Pseudo instruction that combines ldr from constpool and add pc. This should
1334 // be expanded into two instructions late to allow if-conversion and
1336 let isReMaterializable = 1 in
1337 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1339 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1341 Requires<[IsThumb, IsThumb1Only]>;
1343 // Pseudo-instruction for merged POP and return.
1344 // FIXME: remove when we have a way to marking a MI with these properties.
1345 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1346 hasExtraDefRegAllocReq = 1 in
1347 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1349 (tPOP pred:$p, reglist:$regs)>;
1351 // Indirect branch using "mov pc, $Rm"
1352 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1353 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1354 2, IIC_Br, [(brind GPR:$Rm)],
1355 (tMOVr PC, GPR:$Rm, pred:$p)>;