1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
136 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
137 "add $dst, pc, $rhs * 4", []>;
140 // FIXME: hard code sp?
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
142 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
145 // FIXME: hard code sp?
146 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
147 "add $dst, $rhs * 4", []>;
149 // FIXME: Make use of the following?
153 //===----------------------------------------------------------------------===//
154 // Control Flow Instructions.
157 let isReturn = 1, isTerminator = 1 in {
158 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
159 // Alternative return instruction used by vararg functions.
160 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
163 // FIXME: remove when we have a way to marking a MI with these properties.
164 let isReturn = 1, isTerminator = 1 in
165 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
169 Defs = [R0, R1, R2, R3, R12, LR,
170 D0, D1, D2, D3, D4, D5, D6, D7,
171 D16, D17, D18, D19, D20, D21, D22, D23,
172 D24, D25, D26, D27, D28, D29, D31, D31, CPSR] in {
173 def tBL : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
175 [(ARMtcall tglobaladdr:$func)]>;
177 def tBLXi : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
179 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
180 def tBLXr : T1I<(outs), (ins tGPR:$func, variable_ops),
182 [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
184 def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
185 "mov lr, pc\n\tbx $func",
186 [(ARMcall_nolink tGPR:$func)]>;
189 let isBranch = 1, isTerminator = 1 in {
190 let isBarrier = 1 in {
191 let isPredicable = 1 in
192 def tB : T1I<(outs), (ins brtarget:$target), "b $target",
196 def tBfar : T1Ix2<(outs), (ins brtarget:$target),
197 "bl $target\t@ far jump",[]>;
199 def tBR_JTr : T1JTI<(outs),
200 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
201 "mov pc, $target \n\t.align\t2\n$jt",
202 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
206 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
207 // a two-value operand where a dag node expects two operands. :(
208 let isBranch = 1, isTerminator = 1 in
209 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
210 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
212 //===----------------------------------------------------------------------===//
213 // Load Store Instructions.
216 let canFoldAsLoad = 1 in
217 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
218 "ldr", " $dst, $addr",
219 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
221 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
222 "ldrb", " $dst, $addr",
223 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
225 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
226 "ldrh", " $dst, $addr",
227 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
229 let AddedComplexity = 10 in
230 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
231 "ldrsb", " $dst, $addr",
232 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
234 let AddedComplexity = 10 in
235 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
236 "ldrsh", " $dst, $addr",
237 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
239 let canFoldAsLoad = 1 in
240 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
241 "ldr", " $dst, $addr",
242 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
244 // Special instruction for restore. It cannot clobber condition register
245 // when it's expanded by eliminateCallFramePseudoInstr().
246 let canFoldAsLoad = 1, mayLoad = 1 in
247 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
248 "ldr", " $dst, $addr", []>;
251 let canFoldAsLoad = 1 in
252 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
253 "ldr", " $dst, $addr",
254 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
256 // Special LDR for loads from non-pc-relative constpools.
257 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
258 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
259 "ldr", " $dst, $addr", []>;
261 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
262 "str", " $src, $addr",
263 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
265 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
266 "strb", " $src, $addr",
267 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
269 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
270 "strh", " $src, $addr",
271 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
273 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
274 "str", " $src, $addr",
275 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
277 let mayStore = 1 in {
278 // Special instruction for spill. It cannot clobber condition register
279 // when it's expanded by eliminateCallFramePseudoInstr().
280 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
281 "str", " $src, $addr", []>;
284 //===----------------------------------------------------------------------===//
285 // Load / store multiple Instructions.
288 // TODO: A7-44: LDMIA - load multiple
289 // TODO: Allow these to be predicated
292 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
296 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
299 //===----------------------------------------------------------------------===//
300 // Arithmetic Instructions.
303 // Add with carry register
304 let isCommutable = 1, Uses = [CPSR] in
305 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
306 "adc", " $dst, $rhs",
307 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
310 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
311 "add", " $dst, $lhs, $rhs",
312 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
314 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
315 "add", " $dst, $rhs",
316 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
319 let isCommutable = 1 in
320 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
321 "add", " $dst, $lhs, $rhs",
322 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
324 let neverHasSideEffects = 1 in
325 def tADDhirr : T1pIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
326 "add", " $dst, $rhs @ addhirr", []>;
329 let isCommutable = 1 in
330 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
331 "and", " $dst, $rhs",
332 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
335 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
336 "asr", " $dst, $lhs, $rhs",
337 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
340 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
341 "asr", " $dst, $rhs",
342 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
345 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
346 "bic", " $dst, $rhs",
347 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
350 let Defs = [CPSR] in {
351 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
352 "cmn", " $lhs, $rhs",
353 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
354 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
355 "cmn", " $lhs, $rhs",
356 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
360 let Defs = [CPSR] in {
361 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
362 "cmp", " $lhs, $rhs",
363 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
364 def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
365 "cmp", " $lhs, $rhs",
366 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
371 let Defs = [CPSR] in {
372 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
373 "cmp", " $lhs, $rhs",
374 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
375 def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
376 "cmp", " $lhs, $rhs",
377 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
379 // TODO: Make use of the followings cmp hi regs
380 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
381 "cmp", " $lhs, $rhs", []>;
382 def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
383 "cmp", " $lhs, $rhs", []>;
388 let isCommutable = 1 in
389 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
390 "eor", " $dst, $rhs",
391 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
394 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
395 "lsl", " $dst, $lhs, $rhs",
396 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
399 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
400 "lsl", " $dst, $rhs",
401 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
404 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
405 "lsr", " $dst, $lhs, $rhs",
406 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
409 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
410 "lsr", " $dst, $rhs",
411 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
414 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src),
415 "mov", " $dst, $src",
416 [(set tGPR:$dst, imm0_255:$src)]>;
418 // TODO: A7-73: MOV(2) - mov setting flag.
421 let neverHasSideEffects = 1 in {
422 // FIXME: Make this predicable.
423 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
424 "mov $dst, $src", []>;
426 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
427 "movs $dst, $src", []>;
429 // FIXME: Make these predicable.
430 def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src),
431 "mov $dst, $src\t@ hir2lor", []>;
432 def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src),
433 "mov $dst, $src\t@ lor2hir", []>;
434 def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src),
435 "mov $dst, $src\t@ hir2hir", []>;
436 } // neverHasSideEffects
439 let isCommutable = 1 in
440 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
441 "mul", " $dst, $rhs",
442 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
444 // move inverse register
445 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
446 "mvn", " $dst, $src",
447 [(set tGPR:$dst, (not tGPR:$src))]>;
449 // bitwise or register
450 let isCommutable = 1 in
451 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
452 "orr", " $dst, $rhs",
453 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
456 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
457 "rev", " $dst, $src",
458 [(set tGPR:$dst, (bswap tGPR:$src))]>,
459 Requires<[IsThumb1Only, HasV6]>;
461 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
462 "rev16", " $dst, $src",
464 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
465 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
466 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
467 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
468 Requires<[IsThumb1Only, HasV6]>;
470 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
471 "revsh", " $dst, $src",
474 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
475 (shl tGPR:$src, (i32 8))), i16))]>,
476 Requires<[IsThumb1Only, HasV6]>;
478 // rotate right register
479 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
480 "ror", " $dst, $rhs",
481 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
484 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
485 "rsb", " $dst, $src, #0",
486 [(set tGPR:$dst, (ineg tGPR:$src))]>;
488 // Subtract with carry register
490 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
491 "sbc", " $dst, $rhs",
492 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
494 // Subtract immediate
495 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
496 "sub", " $dst, $lhs, $rhs",
497 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
499 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
500 "sub", " $dst, $rhs",
501 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
504 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
505 "sub", " $dst, $lhs, $rhs",
506 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
508 // TODO: A7-96: STMIA - store multiple.
510 def tSUBspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
511 "sub $dst, $rhs * 4", []>;
514 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
515 "sxtb", " $dst, $src",
516 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
517 Requires<[IsThumb1Only, HasV6]>;
520 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
521 "sxth", " $dst, $src",
522 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
523 Requires<[IsThumb1Only, HasV6]>;
526 let isCommutable = 1, Defs = [CPSR] in
527 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
528 "tst", " $lhs, $rhs",
529 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
532 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
533 "uxtb", " $dst, $src",
534 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
535 Requires<[IsThumb1Only, HasV6]>;
538 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
539 "uxth", " $dst, $src",
540 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
541 Requires<[IsThumb1Only, HasV6]>;
544 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
545 // Expanded by the scheduler into a branch sequence.
546 // FIXME: Add actual movcc in IT blocks for Thumb2.
547 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
549 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
551 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
553 // tLEApcrel - Load a pc-relative address into a register without offending the
555 def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label),
556 "adr $dst, #$label", []>;
558 def tLEApcrelJT : T1I<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
559 "adr $dst, #${label}_${id:no_hash}", []>;
561 //===----------------------------------------------------------------------===//
565 // __aeabi_read_tp preserves the registers r1-r3.
568 def tTPsoft : T1Ix2<(outs), (ins),
569 "bl __aeabi_read_tp",
570 [(set R0, ARMthread_pointer)]>;
573 //===----------------------------------------------------------------------===//
574 // Non-Instruction Patterns
578 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
579 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
580 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
581 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
582 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
583 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
585 // Subtract with carry
586 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
587 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
588 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
589 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
590 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
591 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
593 // ConstantPool, GlobalAddress
594 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
595 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
598 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
599 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
602 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
603 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
605 // Indirect calls to ARM routines
606 def : Tv5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
608 // zextload i1 -> zextload i8
609 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
610 (tLDRB t_addrmode_s1:$addr)>;
612 // extload -> zextload
613 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
614 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
615 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
617 // If it's possible to use [r,r] address mode for sextload, select to
618 // ldr{b|h} + sxt{b|h} instead.
619 def : T1Pat<(sextloadi8 t_addrmode_s1:$addr),
620 (tSXTB (tLDRB t_addrmode_s1:$addr))>;
621 def : T1Pat<(sextloadi16 t_addrmode_s2:$addr),
622 (tSXTH (tLDRH t_addrmode_s2:$addr))>;
625 // Large immediate handling.
628 def : T1Pat<(i32 thumb_immshifted:$src),
629 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
630 (thumb_immshifted_shamt imm:$src))>;
632 def : T1Pat<(i32 imm0_255_comp:$src),
633 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;