1 //===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
22 def imm_sr_XFORM: SDNodeXForm<imm, [{
23 unsigned Imm = N->getZExtValue();
24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32);
26 def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; }
27 def imm_sr : Operand<i32>, PatLeaf<(imm), [{
28 uint64_t Imm = N->getZExtValue();
29 return Imm > 0 && Imm <= 32;
31 let PrintMethod = "printThumbSRImm";
32 let ParserMatchClass = ThumbSRImmAsmOperand;
35 def imm_neg_XFORM : SDNodeXForm<imm, [{
36 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
38 def imm_comp_XFORM : SDNodeXForm<imm, [{
39 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
42 def imm0_7_neg : PatLeaf<(i32 imm), [{
43 return (uint32_t)-N->getZExtValue() < 8;
46 def imm0_255_comp : PatLeaf<(i32 imm), [{
47 return ~((uint32_t)N->getZExtValue()) < 256;
50 def imm8_255 : ImmLeaf<i32, [{
51 return Imm >= 8 && Imm < 256;
53 def imm8_255_neg : PatLeaf<(i32 imm), [{
54 unsigned Val = -N->getZExtValue();
55 return Val >= 8 && Val < 256;
58 // Break imm's up into two pieces: an immediate + a left shift. This uses
59 // thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
60 // to get the val/shift pieces.
61 def thumb_immshifted : PatLeaf<(imm), [{
62 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
65 def thumb_immshifted_val : SDNodeXForm<imm, [{
66 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
67 return CurDAG->getTargetConstant(V, MVT::i32);
70 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
71 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
72 return CurDAG->getTargetConstant(V, MVT::i32);
75 // ADR instruction labels.
76 def t_adrlabel : Operand<i32> {
77 let EncoderMethod = "getThumbAdrLabelOpValue";
80 // Scaled 4 immediate.
81 def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; }
82 def t_imm0_1020s4 : Operand<i32> {
83 let PrintMethod = "printThumbS4ImmOperand";
84 let ParserMatchClass = t_imm0_1020s4_asmoperand;
85 let OperandType = "OPERAND_IMMEDIATE";
88 def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; }
89 def t_imm0_508s4 : Operand<i32> {
90 let PrintMethod = "printThumbS4ImmOperand";
91 let ParserMatchClass = t_imm0_508s4_asmoperand;
92 let OperandType = "OPERAND_IMMEDIATE";
94 // Alias use only, so no printer is necessary.
95 def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; }
96 def t_imm0_508s4_neg : Operand<i32> {
97 let ParserMatchClass = t_imm0_508s4_neg_asmoperand;
98 let OperandType = "OPERAND_IMMEDIATE";
101 // Define Thumb specific addressing modes.
103 let OperandType = "OPERAND_PCREL" in {
104 def t_brtarget : Operand<OtherVT> {
105 let EncoderMethod = "getThumbBRTargetOpValue";
106 let DecoderMethod = "DecodeThumbBROperand";
109 def t_bcctarget : Operand<i32> {
110 let EncoderMethod = "getThumbBCCTargetOpValue";
111 let DecoderMethod = "DecodeThumbBCCTargetOperand";
114 def t_cbtarget : Operand<i32> {
115 let EncoderMethod = "getThumbCBTargetOpValue";
116 let DecoderMethod = "DecodeThumbCmpBROperand";
119 def t_bltarget : Operand<i32> {
120 let EncoderMethod = "getThumbBLTargetOpValue";
121 let DecoderMethod = "DecodeThumbBLTargetOperand";
124 def t_blxtarget : Operand<i32> {
125 let EncoderMethod = "getThumbBLXTargetOpValue";
126 let DecoderMethod = "DecodeThumbBLXOffset";
130 // t_addrmode_rr := reg + reg
132 def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; }
133 def t_addrmode_rr : Operand<i32>,
134 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
135 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
136 let PrintMethod = "printThumbAddrModeRROperand";
137 let DecoderMethod = "DecodeThumbAddrModeRR";
138 let ParserMatchClass = t_addrmode_rr_asm_operand;
139 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
142 // t_addrmode_rrs := reg + reg
144 // We use separate scaled versions because the Select* functions need
145 // to explicitly check for a matching constant and return false here so that
146 // the reg+imm forms will match instead. This is a horrible way to do that,
147 // as it forces tight coupling between the methods, but it's how selectiondag
149 def t_addrmode_rrs1 : Operand<i32>,
150 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
151 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
152 let PrintMethod = "printThumbAddrModeRROperand";
153 let DecoderMethod = "DecodeThumbAddrModeRR";
154 let ParserMatchClass = t_addrmode_rr_asm_operand;
155 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
157 def t_addrmode_rrs2 : Operand<i32>,
158 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
159 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
160 let DecoderMethod = "DecodeThumbAddrModeRR";
161 let PrintMethod = "printThumbAddrModeRROperand";
162 let ParserMatchClass = t_addrmode_rr_asm_operand;
163 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
165 def t_addrmode_rrs4 : Operand<i32>,
166 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
167 let EncoderMethod = "getThumbAddrModeRegRegOpValue";
168 let DecoderMethod = "DecodeThumbAddrModeRR";
169 let PrintMethod = "printThumbAddrModeRROperand";
170 let ParserMatchClass = t_addrmode_rr_asm_operand;
171 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
174 // t_addrmode_is4 := reg + imm5 * 4
176 def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; }
177 def t_addrmode_is4 : Operand<i32>,
178 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
179 let EncoderMethod = "getAddrModeISOpValue";
180 let DecoderMethod = "DecodeThumbAddrModeIS";
181 let PrintMethod = "printThumbAddrModeImm5S4Operand";
182 let ParserMatchClass = t_addrmode_is4_asm_operand;
183 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
186 // t_addrmode_is2 := reg + imm5 * 2
188 def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; }
189 def t_addrmode_is2 : Operand<i32>,
190 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
191 let EncoderMethod = "getAddrModeISOpValue";
192 let DecoderMethod = "DecodeThumbAddrModeIS";
193 let PrintMethod = "printThumbAddrModeImm5S2Operand";
194 let ParserMatchClass = t_addrmode_is2_asm_operand;
195 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
198 // t_addrmode_is1 := reg + imm5
200 def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; }
201 def t_addrmode_is1 : Operand<i32>,
202 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
203 let EncoderMethod = "getAddrModeISOpValue";
204 let DecoderMethod = "DecodeThumbAddrModeIS";
205 let PrintMethod = "printThumbAddrModeImm5S1Operand";
206 let ParserMatchClass = t_addrmode_is1_asm_operand;
207 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
210 // t_addrmode_sp := sp + imm8 * 4
212 // FIXME: This really shouldn't have an explicit SP operand at all. It should
213 // be implicit, just like in the instruction encoding itself.
214 def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; }
215 def t_addrmode_sp : Operand<i32>,
216 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
217 let EncoderMethod = "getAddrModeThumbSPOpValue";
218 let DecoderMethod = "DecodeThumbAddrModeSP";
219 let PrintMethod = "printThumbAddrModeSPOperand";
220 let ParserMatchClass = t_addrmode_sp_asm_operand;
221 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
224 // t_addrmode_pc := <label> => pc + imm8 * 4
226 def t_addrmode_pc : Operand<i32> {
227 let EncoderMethod = "getAddrModePCOpValue";
228 let DecoderMethod = "DecodeThumbAddrModePC";
231 //===----------------------------------------------------------------------===//
232 // Miscellaneous Instructions.
235 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
236 // from removing one half of the matched pairs. That breaks PEI, which assumes
237 // these will always be in pairs, and asserts if it finds otherwise. Better way?
238 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
239 def tADJCALLSTACKUP :
240 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
241 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
242 Requires<[IsThumb, IsThumb1Only]>;
244 def tADJCALLSTACKDOWN :
245 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
246 [(ARMcallseq_start imm:$amt)]>,
247 Requires<[IsThumb, IsThumb1Only]>;
250 class T1SystemEncoding<bits<8> opc>
251 : T1Encoding<0b101111> {
252 let Inst{9-8} = 0b11;
256 def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>,
257 T1SystemEncoding<0x00>, // A8.6.110
258 Requires<[IsThumb2]>;
260 def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>,
261 T1SystemEncoding<0x10>, // A8.6.410
262 Requires<[IsThumb2]>;
264 def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>,
265 T1SystemEncoding<0x20>, // A8.6.408
266 Requires<[IsThumb2]>;
268 def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>,
269 T1SystemEncoding<0x30>, // A8.6.409
270 Requires<[IsThumb2]>;
272 def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>,
273 T1SystemEncoding<0x40>, // A8.6.157
274 Requires<[IsThumb2]>;
276 // The imm operand $val can be used by a debugger to store more information
277 // about the breakpoint.
278 def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val",
280 T1Encoding<0b101111> {
281 let Inst{9-8} = 0b10;
287 def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end",
288 []>, T1Encoding<0b101101> {
291 let Inst{9-5} = 0b10010;
294 let Inst{2-0} = 0b000;
297 // Change Processor State is a system instruction -- for disassembly only.
298 def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
299 NoItinerary, "cps$imod $iflags", []>,
307 let Inst{2-0} = iflags;
308 let DecoderMethod = "DecodeThumbCPS";
311 // For both thumb1 and thumb2.
312 let isNotDuplicable = 1, isCodeGenOnly = 1 in
313 def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
314 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
315 T1Special<{0,0,?,?}> {
318 let Inst{6-3} = 0b1111; // Rm = pc
322 // ADD <Rd>, sp, #<imm8>
323 // FIXME: This should not be marked as having side effects, and it should be
324 // rematerializable. Clearing the side effect bit causes miscompilations,
325 // probably because the instruction can be moved around.
326 def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm),
327 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>,
328 T1Encoding<{1,0,1,0,1,?}> {
332 let Inst{10-8} = dst;
334 let DecoderMethod = "DecodeThumbAddSpecialReg";
337 // ADD sp, sp, #<imm7>
338 def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
339 IIC_iALUi, "add", "\t$Rdn, $imm", []>,
340 T1Misc<{0,0,0,0,0,?,?}> {
344 let DecoderMethod = "DecodeThumbAddSPImm";
347 // SUB sp, sp, #<imm7>
348 // FIXME: The encoding and the ASM string don't match up.
349 def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm),
350 IIC_iALUi, "sub", "\t$Rdn, $imm", []>,
351 T1Misc<{0,0,0,0,1,?,?}> {
355 let DecoderMethod = "DecodeThumbAddSPImm";
358 def : tInstAlias<"add${p} sp, $imm",
359 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
360 def : tInstAlias<"add${p} sp, sp, $imm",
361 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>;
363 // Can optionally specify SP as a three operand instruction.
364 def : tInstAlias<"add${p} sp, sp, $imm",
365 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>;
366 def : tInstAlias<"sub${p} sp, sp, $imm",
367 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>;
370 def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr,
371 "add", "\t$Rdn, $sp, $Rn", []>,
372 T1Special<{0,0,?,?}> {
373 // A8.6.9 Encoding T1
375 let Inst{7} = Rdn{3};
376 let Inst{6-3} = 0b1101;
377 let Inst{2-0} = Rdn{2-0};
378 let DecoderMethod = "DecodeThumbAddSPReg";
382 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
383 "add", "\t$Rdn, $Rm", []>,
384 T1Special<{0,0,?,?}> {
385 // A8.6.9 Encoding T2
389 let Inst{2-0} = 0b101;
390 let DecoderMethod = "DecodeThumbAddSPReg";
393 //===----------------------------------------------------------------------===//
394 // Control Flow Instructions.
398 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
399 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
400 T1Special<{1,1,0,?}> {
404 let Inst{2-0} = 0b000;
405 let Unpredictable{2-0} = 0b111;
409 let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
410 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br,
411 [(ARMretflag)], (tBX LR, pred:$p)>;
413 // Alternative return instruction used by vararg functions.
414 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p),
416 (tBX GPR:$Rm, pred:$p)>;
419 // All calls clobber the non-callee saved registers. SP is marked as a use to
420 // prevent stack-pointer assignments that appear immediately before calls from
421 // potentially appearing dead.
423 Defs = [LR], Uses = [SP] in {
424 // Also used for Thumb2
425 def tBL : TIx2<0b11110, 0b11, 1,
426 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), IIC_Br,
428 [(ARMtcall tglobaladdr:$func)]>,
429 Requires<[IsThumb]> {
431 let Inst{26} = func{23};
432 let Inst{25-16} = func{20-11};
433 let Inst{13} = func{22};
434 let Inst{11} = func{21};
435 let Inst{10-0} = func{10-0};
438 // ARMv5T and above, also used for Thumb2
439 def tBLXi : TIx2<0b11110, 0b11, 0,
440 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), IIC_Br,
442 [(ARMcall tglobaladdr:$func)]>,
443 Requires<[IsThumb, HasV5T]> {
445 let Inst{26} = func{23};
446 let Inst{25-16} = func{20-11};
447 let Inst{13} = func{22};
448 let Inst{11} = func{21};
449 let Inst{10-1} = func{10-1};
450 let Inst{0} = 0; // func{0} is assumed zero
453 // Also used for Thumb2
454 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
456 [(ARMtcall GPR:$func)]>,
457 Requires<[IsThumb, HasV5T]>,
458 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
460 let Inst{6-3} = func;
461 let Inst{2-0} = 0b000;
465 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
467 [(ARMcall_nolink tGPR:$func)]>,
468 Requires<[IsThumb, IsThumb1Only]>;
471 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
472 let isPredicable = 1 in
473 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br,
474 "b", "\t$target", [(br bb:$target)]>,
475 T1Encoding<{1,1,1,0,0,?}> {
477 let Inst{10-0} = target;
481 // Just a pseudo for a tBL instruction. Needed to let regalloc know about
482 // the clobber of LR.
484 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p),
485 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>;
487 def tBR_JTr : tPseudoInst<(outs),
488 (ins tGPR:$target, i32imm:$jt, i32imm:$id),
490 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
491 list<Predicate> Predicates = [IsThumb, IsThumb1Only];
495 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
496 // a two-value operand where a dag node expects two operands. :(
497 let isBranch = 1, isTerminator = 1 in
498 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
500 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
501 T1BranchCond<{1,1,0,1}> {
505 let Inst{7-0} = target;
509 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
512 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst, variable_ops),
514 (tBX GPR:$dst, (ops 14, zero_reg))>,
517 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls
518 // on IOS), so it's in ARMInstrThumb2.td.
521 def tTAILJMPdND : tPseudoExpand<(outs),
522 (ins t_brtarget:$dst, pred:$p, variable_ops),
524 (tB t_brtarget:$dst, pred:$p)>,
525 Requires<[IsThumb, IsNotIOS]>;
530 // A8.6.218 Supervisor Call (Software Interrupt)
531 // A8.6.16 B: Encoding T1
532 // If Inst{11-8} == 0b1111 then SEE SVC
533 let isCall = 1, Uses = [SP] in
534 def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br,
535 "svc", "\t$imm", []>, Encoding16 {
537 let Inst{15-12} = 0b1101;
538 let Inst{11-8} = 0b1111;
542 // The assembler uses 0xDEFE for a trap instruction.
543 let isBarrier = 1, isTerminator = 1 in
544 def tTRAP : TI<(outs), (ins), IIC_Br,
545 "trap", [(trap)]>, Encoding16 {
549 //===----------------------------------------------------------------------===//
550 // Load Store Instructions.
553 // Loads: reg/reg and reg/imm5
554 let canFoldAsLoad = 1, isReMaterializable = 1 in
555 multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
556 Operand AddrMode_r, Operand AddrMode_i,
557 AddrMode am, InstrItinClass itin_r,
558 InstrItinClass itin_i, string asm,
561 T1pILdStEncode<reg_opc,
562 (outs tGPR:$Rt), (ins AddrMode_r:$addr),
563 am, itin_r, asm, "\t$Rt, $addr",
564 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
566 T1pILdStEncodeImm<imm_opc, 1 /* Load */,
567 (outs tGPR:$Rt), (ins AddrMode_i:$addr),
568 am, itin_i, asm, "\t$Rt, $addr",
569 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
571 // Stores: reg/reg and reg/imm5
572 multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
573 Operand AddrMode_r, Operand AddrMode_i,
574 AddrMode am, InstrItinClass itin_r,
575 InstrItinClass itin_i, string asm,
578 T1pILdStEncode<reg_opc,
579 (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
580 am, itin_r, asm, "\t$Rt, $addr",
581 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
583 T1pILdStEncodeImm<imm_opc, 0 /* Store */,
584 (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
585 am, itin_i, asm, "\t$Rt, $addr",
586 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
590 defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
591 t_addrmode_is4, AddrModeT1_4,
592 IIC_iLoad_r, IIC_iLoad_i, "ldr",
593 UnOpFrag<(load node:$Src)>>;
596 defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
597 t_addrmode_is1, AddrModeT1_1,
598 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
599 UnOpFrag<(zextloadi8 node:$Src)>>;
602 defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
603 t_addrmode_is2, AddrModeT1_2,
604 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
605 UnOpFrag<(zextloadi16 node:$Src)>>;
607 let AddedComplexity = 10 in
608 def tLDRSB : // A8.6.80
609 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
610 AddrModeT1_1, IIC_iLoad_bh_r,
611 "ldrsb", "\t$Rt, $addr",
612 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>;
614 let AddedComplexity = 10 in
615 def tLDRSH : // A8.6.84
616 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr),
617 AddrModeT1_2, IIC_iLoad_bh_r,
618 "ldrsh", "\t$Rt, $addr",
619 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>;
621 let canFoldAsLoad = 1 in
622 def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
623 "ldr", "\t$Rt, $addr",
624 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
629 let Inst{7-0} = addr;
633 // FIXME: Use ldr.n to work around a darwin assembler bug.
634 let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in
635 def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
636 "ldr", ".n\t$Rt, $addr",
637 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
638 T1Encoding<{0,1,0,0,1,?}> {
643 let Inst{7-0} = addr;
646 // FIXME: Remove this entry when the above ldr.n workaround is fixed.
647 // For assembly/disassembly use only.
648 def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
649 "ldr", "\t$Rt, $addr", []>,
650 T1Encoding<{0,1,0,0,1,?}> {
655 let Inst{7-0} = addr;
658 // A8.6.194 & A8.6.192
659 defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
660 t_addrmode_is4, AddrModeT1_4,
661 IIC_iStore_r, IIC_iStore_i, "str",
662 BinOpFrag<(store node:$LHS, node:$RHS)>>;
664 // A8.6.197 & A8.6.195
665 defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
666 t_addrmode_is1, AddrModeT1_1,
667 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
668 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
670 // A8.6.207 & A8.6.205
671 defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
672 t_addrmode_is2, AddrModeT1_2,
673 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
674 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
677 def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
678 "str", "\t$Rt, $addr",
679 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
684 let Inst{7-0} = addr;
687 //===----------------------------------------------------------------------===//
688 // Load / store multiple Instructions.
691 // These require base address to be written back or one of the loaded regs.
692 let neverHasSideEffects = 1 in {
694 let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
695 def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
696 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> {
700 let Inst{7-0} = regs;
703 // Writeback version is just a pseudo, as there's no encoding difference.
704 // Writeback happens iff the base register is not in the destination register
707 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain,
708 "$Rn = $wb", IIC_iLoad_mu>,
709 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> {
711 let OutOperandList = (outs GPR:$wb);
712 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops);
714 let isCodeGenOnly = 1;
716 list<Predicate> Predicates = [IsThumb];
719 // There is no non-writeback version of STM for Thumb.
720 let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
721 def tSTMIA_UPD : Thumb1I<(outs GPR:$wb),
722 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops),
723 AddrModeNone, 2, IIC_iStore_mu,
724 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>,
725 T1Encoding<{1,1,0,0,0,?}> {
729 let Inst{7-0} = regs;
732 } // neverHasSideEffects
734 def : InstAlias<"ldm${p} $Rn!, $regs",
735 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>,
736 Requires<[IsThumb, IsThumb1Only]>;
738 let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
739 def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
741 "pop${p}\t$regs", []>,
742 T1Misc<{1,1,0,?,?,?,?}> {
744 let Inst{8} = regs{15};
745 let Inst{7-0} = regs{7-0};
748 let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
749 def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
751 "push${p}\t$regs", []>,
752 T1Misc<{0,1,0,?,?,?,?}> {
754 let Inst{8} = regs{14};
755 let Inst{7-0} = regs{7-0};
758 //===----------------------------------------------------------------------===//
759 // Arithmetic Instructions.
762 // Helper classes for encoding T1pI patterns:
763 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
764 string opc, string asm, list<dag> pattern>
765 : T1pI<oops, iops, itin, opc, asm, pattern>,
766 T1DataProcessing<opA> {
772 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
773 string opc, string asm, list<dag> pattern>
774 : T1pI<oops, iops, itin, opc, asm, pattern>,
782 // Helper classes for encoding T1sI patterns:
783 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
784 string opc, string asm, list<dag> pattern>
785 : T1sI<oops, iops, itin, opc, asm, pattern>,
786 T1DataProcessing<opA> {
792 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
793 string opc, string asm, list<dag> pattern>
794 : T1sI<oops, iops, itin, opc, asm, pattern>,
803 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
804 string opc, string asm, list<dag> pattern>
805 : T1sI<oops, iops, itin, opc, asm, pattern>,
813 // Helper classes for encoding T1sIt patterns:
814 class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
815 string opc, string asm, list<dag> pattern>
816 : T1sIt<oops, iops, itin, opc, asm, pattern>,
817 T1DataProcessing<opA> {
823 class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
824 string opc, string asm, list<dag> pattern>
825 : T1sIt<oops, iops, itin, opc, asm, pattern>,
829 let Inst{10-8} = Rdn;
830 let Inst{7-0} = imm8;
833 // Add with carry register
834 let isCommutable = 1, Uses = [CPSR] in
836 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
837 "adc", "\t$Rdn, $Rm",
838 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
841 def tADDi3 : // A8.6.4 T1
842 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
844 "add", "\t$Rd, $Rm, $imm3",
845 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
847 let Inst{8-6} = imm3;
850 def tADDi8 : // A8.6.4 T2
851 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn),
852 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
853 "add", "\t$Rdn, $imm8",
854 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
857 let isCommutable = 1 in
858 def tADDrr : // A8.6.6 T1
859 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
861 "add", "\t$Rd, $Rn, $Rm",
862 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
864 let neverHasSideEffects = 1 in
865 def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
866 "add", "\t$Rdn, $Rm", []>,
867 T1Special<{0,0,?,?}> {
871 let Inst{7} = Rdn{3};
873 let Inst{2-0} = Rdn{2-0};
877 let isCommutable = 1 in
878 def tAND : // A8.6.12
879 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
881 "and", "\t$Rdn, $Rm",
882 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
885 def tASRri : // A8.6.14
886 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
888 "asr", "\t$Rd, $Rm, $imm5",
889 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
891 let Inst{10-6} = imm5;
895 def tASRrr : // A8.6.15
896 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
898 "asr", "\t$Rdn, $Rm",
899 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
902 def tBIC : // A8.6.20
903 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
905 "bic", "\t$Rdn, $Rm",
906 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
909 let isCompare = 1, Defs = [CPSR] in {
910 //FIXME: Disable CMN, as CCodes are backwards from compare expectations
911 // Compare-to-zero still works out, just not the relationals
912 //def tCMN : // A8.6.33
913 // T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
915 // "cmn", "\t$lhs, $rhs",
916 // [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
918 def tCMNz : // A8.6.33
919 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
922 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
924 } // isCompare = 1, Defs = [CPSR]
927 let isCompare = 1, Defs = [CPSR] in {
928 def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi,
929 "cmp", "\t$Rn, $imm8",
930 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
931 T1General<{1,0,1,?,?}> {
936 let Inst{7-0} = imm8;
940 def tCMPr : // A8.6.36 T1
941 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
944 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
946 def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
947 "cmp", "\t$Rn, $Rm", []>,
948 T1Special<{0,1,?,?}> {
954 let Inst{2-0} = Rn{2-0};
956 } // isCompare = 1, Defs = [CPSR]
960 let isCommutable = 1 in
961 def tEOR : // A8.6.45
962 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
964 "eor", "\t$Rdn, $Rm",
965 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
968 def tLSLri : // A8.6.88
969 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5),
971 "lsl", "\t$Rd, $Rm, $imm5",
972 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
974 let Inst{10-6} = imm5;
978 def tLSLrr : // A8.6.89
979 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
981 "lsl", "\t$Rdn, $Rm",
982 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
985 def tLSRri : // A8.6.90
986 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5),
988 "lsr", "\t$Rd, $Rm, $imm5",
989 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> {
991 let Inst{10-6} = imm5;
995 def tLSRrr : // A8.6.91
996 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
998 "lsr", "\t$Rdn, $Rm",
999 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1002 let isMoveImm = 1 in
1003 def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi,
1004 "mov", "\t$Rd, $imm8",
1005 [(set tGPR:$Rd, imm0_255:$imm8)]>,
1006 T1General<{1,0,0,?,?}> {
1010 let Inst{10-8} = Rd;
1011 let Inst{7-0} = imm8;
1013 // Because we have an explicit tMOVSr below, we need an alias to handle
1014 // the immediate "movs" form here. Blech.
1015 def : tInstAlias <"movs $Rdn, $imm",
1016 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>;
1018 // A7-73: MOV(2) - mov setting flag.
1020 let neverHasSideEffects = 1 in {
1021 def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone,
1023 "mov", "\t$Rd, $Rm", "", []>,
1024 T1Special<{1,0,?,?}> {
1028 let Inst{7} = Rd{3};
1030 let Inst{2-0} = Rd{2-0};
1032 let Defs = [CPSR] in
1033 def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1034 "movs\t$Rd, $Rm", []>, Encoding16 {
1038 let Inst{15-6} = 0b0000000000;
1042 } // neverHasSideEffects
1044 // Multiply register
1045 let isCommutable = 1 in
1046 def tMUL : // A8.6.105 T1
1047 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2,
1048 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd",
1049 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>,
1050 T1DataProcessing<0b1101> {
1055 let AsmMatchConverter = "cvtThumbMultiply";
1058 def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn,
1061 // Move inverse register
1062 def tMVN : // A8.6.107
1063 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1064 "mvn", "\t$Rd, $Rn",
1065 [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1067 // Bitwise or register
1068 let isCommutable = 1 in
1069 def tORR : // A8.6.114
1070 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1072 "orr", "\t$Rdn, $Rm",
1073 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1076 def tREV : // A8.6.134
1077 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1079 "rev", "\t$Rd, $Rm",
1080 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1081 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1083 def tREV16 : // A8.6.135
1084 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1086 "rev16", "\t$Rd, $Rm",
1087 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>,
1088 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1090 def tREVSH : // A8.6.136
1091 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1093 "revsh", "\t$Rd, $Rm",
1094 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>,
1095 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1097 // Rotate right register
1098 def tROR : // A8.6.139
1099 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1101 "ror", "\t$Rdn, $Rm",
1102 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1105 def tRSB : // A8.6.141
1106 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1108 "rsb", "\t$Rd, $Rn, #0",
1109 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1111 // Subtract with carry register
1112 let Uses = [CPSR] in
1113 def tSBC : // A8.6.151
1114 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1116 "sbc", "\t$Rdn, $Rm",
1117 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1119 // Subtract immediate
1120 def tSUBi3 : // A8.6.210 T1
1121 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3),
1123 "sub", "\t$Rd, $Rm, $imm3",
1124 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1126 let Inst{8-6} = imm3;
1129 def tSUBi8 : // A8.6.210 T2
1130 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn),
1131 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi,
1132 "sub", "\t$Rdn, $imm8",
1133 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1135 // Subtract register
1136 def tSUBrr : // A8.6.212
1137 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1139 "sub", "\t$Rd, $Rn, $Rm",
1140 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1143 def tSXTB : // A8.6.222
1144 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1146 "sxtb", "\t$Rd, $Rm",
1147 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1148 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1150 // Sign-extend short
1151 def tSXTH : // A8.6.224
1152 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1154 "sxth", "\t$Rd, $Rm",
1155 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1156 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1159 let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1160 def tTST : // A8.6.230
1161 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1162 "tst", "\t$Rn, $Rm",
1163 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1166 def tUXTB : // A8.6.262
1167 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1169 "uxtb", "\t$Rd, $Rm",
1170 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1171 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1173 // Zero-extend short
1174 def tUXTH : // A8.6.264
1175 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1177 "uxth", "\t$Rd, $Rm",
1178 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1179 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1181 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1182 // Expanded after instruction selection into a branch sequence.
1183 let usesCustomInserter = 1 in // Expanded after instruction selection.
1184 def tMOVCCr_pseudo :
1185 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1187 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1189 // tLEApcrel - Load a pc-relative address into a register without offending the
1192 def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1193 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>,
1194 T1Encoding<{1,0,1,0,0,?}> {
1197 let Inst{10-8} = Rd;
1198 let Inst{7-0} = addr;
1199 let DecoderMethod = "DecodeThumbAddSpecialReg";
1202 let neverHasSideEffects = 1, isReMaterializable = 1 in
1203 def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1206 def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1207 (ins i32imm:$label, nohash_imm:$id, pred:$p),
1210 //===----------------------------------------------------------------------===//
1214 // __aeabi_read_tp preserves the registers r1-r3.
1215 // This is a pseudo inst so that we can get the encoding right,
1216 // complete with fixup for the aeabi_read_tp function.
1217 let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in
1218 def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br,
1219 [(set R0, ARMthread_pointer)]>;
1221 //===----------------------------------------------------------------------===//
1222 // SJLJ Exception handling intrinsics
1225 // eh_sjlj_setjmp() is an instruction sequence to store the return address and
1226 // save #0 in R0 for the non-longjmp case. Since by its nature we may be coming
1227 // from some other function to get here, and we're using the stack frame for the
1228 // containing function to save/restore registers, we can't keep anything live in
1229 // regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1230 // tromped upon when we get here from a longjmp(). We force everything out of
1231 // registers except for our own input by listing the relevant registers in
1232 // Defs. By doing so, we also cause the prologue/epilogue code to actively
1233 // preserve all of the callee-saved resgisters, which is exactly what we want.
1234 // $val is a scratch register for our use.
1235 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1236 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
1237 usesCustomInserter = 1 in
1238 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1239 AddrModeNone, 0, NoItinerary, "","",
1240 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1242 // FIXME: Non-IOS version(s)
1243 let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1244 Defs = [ R7, LR, SP ] in
1245 def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1246 AddrModeNone, 0, IndexModeNone,
1247 Pseudo, NoItinerary, "", "",
1248 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1249 Requires<[IsThumb, IsIOS]>;
1251 let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ],
1253 def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>;
1255 //===----------------------------------------------------------------------===//
1256 // Non-Instruction Patterns
1260 def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1261 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>;
1262 def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1263 (tCMPr tGPR:$Rn, tGPR:$Rm)>;
1266 def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs),
1267 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1268 def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs),
1269 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1270 def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs),
1271 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1273 // Subtract with carry
1274 def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
1275 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1276 def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
1277 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1278 def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs),
1279 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1281 // ConstantPool, GlobalAddress
1282 def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1283 def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
1286 def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1287 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1290 def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1291 Requires<[IsThumb]>;
1293 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1294 Requires<[IsThumb, HasV5T]>;
1296 // Indirect calls to ARM routines
1297 def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1298 Requires<[IsThumb, HasV5T]>;
1300 // zextload i1 -> zextload i8
1301 def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1302 (tLDRBr t_addrmode_rrs1:$addr)>;
1303 def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1304 (tLDRBi t_addrmode_is1:$addr)>;
1306 // extload -> zextload
1307 def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1308 def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1309 def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1310 def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>;
1311 def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1312 def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>;
1314 // If it's impossible to use [r,r] address mode for sextload, select to
1315 // ldr{b|h} + sxt{b|h} instead.
1316 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1317 (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1318 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1319 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1320 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1321 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1322 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1323 (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1324 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1325 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1326 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1327 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1329 def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1330 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1331 def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1332 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1333 def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1334 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1335 def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1336 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1338 def : T1Pat<(atomic_load_8 t_addrmode_is1:$src),
1339 (tLDRBi t_addrmode_is1:$src)>;
1340 def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src),
1341 (tLDRBr t_addrmode_rrs1:$src)>;
1342 def : T1Pat<(atomic_load_16 t_addrmode_is2:$src),
1343 (tLDRHi t_addrmode_is2:$src)>;
1344 def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src),
1345 (tLDRHr t_addrmode_rrs2:$src)>;
1346 def : T1Pat<(atomic_load_32 t_addrmode_is4:$src),
1347 (tLDRi t_addrmode_is4:$src)>;
1348 def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src),
1349 (tLDRr t_addrmode_rrs4:$src)>;
1350 def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val),
1351 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>;
1352 def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val),
1353 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>;
1354 def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val),
1355 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>;
1356 def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val),
1357 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>;
1358 def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val),
1359 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>;
1360 def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val),
1361 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>;
1363 // Large immediate handling.
1366 def : T1Pat<(i32 thumb_immshifted:$src),
1367 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1368 (thumb_immshifted_shamt imm:$src))>;
1370 def : T1Pat<(i32 imm0_255_comp:$src),
1371 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1373 // Pseudo instruction that combines ldr from constpool and add pc. This should
1374 // be expanded into two instructions late to allow if-conversion and
1376 let isReMaterializable = 1 in
1377 def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1379 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1381 Requires<[IsThumb, IsThumb1Only]>;
1383 // Pseudo-instruction for merged POP and return.
1384 // FIXME: remove when we have a way to marking a MI with these properties.
1385 let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
1386 hasExtraDefRegAllocReq = 1 in
1387 def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops),
1389 (tPOP pred:$p, reglist:$regs)>;
1391 // Indirect branch using "mov pc, $Rm"
1392 let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
1393 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p),
1394 2, IIC_Br, [(brind GPR:$Rm)],
1395 (tMOVr PC, GPR:$Rm, pred:$p)>;
1399 // In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00
1400 // encoding is available on ARMv6K, but we don't differentiate that finely.
1401 def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>;
1404 // For round-trip assembly/disassembly, we have to handle a CPS instruction
1405 // without any iflags. That's not, strictly speaking, valid syntax, but it's
1406 // a useful extension and assembles to defined behaviour (the insn does
1408 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1409 def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>;
1411 // "neg" is and alias for "rsb rd, rn, #0"
1412 def : tInstAlias<"neg${s}${p} $Rd, $Rm",
1413 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>;
1416 // Implied destination operand forms for shifts.
1417 def : tInstAlias<"lsl${s}${p} $Rdm, $imm",
1418 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>;
1419 def : tInstAlias<"lsr${s}${p} $Rdm, $imm",
1420 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;
1421 def : tInstAlias<"asr${s}${p} $Rdm, $imm",
1422 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>;