1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 def imm_neg_XFORM : SDNodeXForm<imm, [{
22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24 def imm_comp_XFORM : SDNodeXForm<imm, [{
25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
29 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30 def imm0_7 : PatLeaf<(i32 imm), [{
31 return (uint32_t)N->getZExtValue() < 8;
33 def imm0_7_neg : PatLeaf<(i32 imm), [{
34 return (uint32_t)-N->getZExtValue() < 8;
37 def imm0_255 : PatLeaf<(i32 imm), [{
38 return (uint32_t)N->getZExtValue() < 256;
40 def imm0_255_comp : PatLeaf<(i32 imm), [{
41 return ~((uint32_t)N->getZExtValue()) < 256;
44 def imm8_255 : PatLeaf<(i32 imm), [{
45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256;
47 def imm8_255_neg : PatLeaf<(i32 imm), [{
48 unsigned Val = -N->getZExtValue();
49 return Val >= 8 && Val < 256;
52 // Break imm's up into two pieces: an immediate + a left shift.
53 // This uses thumb_immshifted to match and thumb_immshifted_val and
54 // thumb_immshifted_shamt to get the val/shift pieces.
55 def thumb_immshifted : PatLeaf<(imm), [{
56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
59 def thumb_immshifted_val : SDNodeXForm<imm, [{
60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61 return CurDAG->getTargetConstant(V, MVT::i32);
64 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66 return CurDAG->getTargetConstant(V, MVT::i32);
69 // Define Thumb specific addressing modes.
71 // t_addrmode_rr := reg + reg
73 def t_addrmode_rr : Operand<i32>,
74 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
75 let PrintMethod = "printThumbAddrModeRROperand";
76 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
79 // t_addrmode_s4 := reg + reg
82 def t_addrmode_s4 : Operand<i32>,
83 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
84 let PrintMethod = "printThumbAddrModeS4Operand";
85 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
88 // t_addrmode_s2 := reg + reg
91 def t_addrmode_s2 : Operand<i32>,
92 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
93 let PrintMethod = "printThumbAddrModeS2Operand";
94 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
97 // t_addrmode_s1 := reg + reg
100 def t_addrmode_s1 : Operand<i32>,
101 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
102 let PrintMethod = "printThumbAddrModeS1Operand";
103 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg);
106 // t_addrmode_sp := sp + imm8 * 4
108 def t_addrmode_sp : Operand<i32>,
109 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
110 let PrintMethod = "printThumbAddrModeSPOperand";
111 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
114 //===----------------------------------------------------------------------===//
115 // Miscellaneous Instructions.
118 let Defs = [SP], Uses = [SP] in {
119 def tADJCALLSTACKUP :
120 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2),
121 "@ tADJCALLSTACKUP $amt1",
122 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>;
124 def tADJCALLSTACKDOWN :
125 PseudoInst<(outs), (ins i32imm:$amt),
126 "@ tADJCALLSTACKDOWN $amt",
127 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>;
130 let isNotDuplicable = 1 in
131 def tPICADD : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, pclabel:$cp),
132 "$cp:\n\tadd $dst, pc",
133 [(set tGPR:$dst, (ARMpic_add tGPR:$lhs, imm:$cp))]>;
136 def tADDrPCi : T1I<(outs tGPR:$dst), (ins i32imm:$rhs),
137 "add $dst, pc, $rhs * 4", []>;
140 // FIXME: hard code sp?
141 def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, i32imm:$rhs),
142 "add $dst, $sp, $rhs * 4 @ addrspi", []>;
145 // FIXME: hard code sp?
146 def tADDspi : T1It<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
147 "add $dst, $rhs * 4", []>;
149 // FIXME: Make use of the following?
153 //===----------------------------------------------------------------------===//
154 // Control Flow Instructions.
157 let isReturn = 1, isTerminator = 1 in {
158 def tBX_RET : TI<(outs), (ins), "bx lr", [(ARMretflag)]>;
159 // Alternative return instruction used by vararg functions.
160 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), "bx $target", []>;
163 // FIXME: remove when we have a way to marking a MI with these properties.
164 let isReturn = 1, isTerminator = 1 in
165 def tPOP_RET : T1I<(outs reglist:$dst1, variable_ops), (ins),
169 Defs = [R0, R1, R2, R3, LR,
170 D0, D1, D2, D3, D4, D5, D6, D7] in {
171 def tBL : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
173 [(ARMtcall tglobaladdr:$func)]>;
175 def tBLXi : T1Ix2<(outs), (ins i32imm:$func, variable_ops),
177 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
178 def tBLXr : T1I<(outs), (ins tGPR:$func, variable_ops),
180 [(ARMtcall tGPR:$func)]>, Requires<[HasV5T]>;
182 def tBX : T1Ix2<(outs), (ins tGPR:$func, variable_ops),
183 "mov lr, pc\n\tbx $func",
184 [(ARMcall_nolink tGPR:$func)]>;
187 let isBranch = 1, isTerminator = 1 in {
188 let isBarrier = 1 in {
189 let isPredicable = 1 in
190 def tB : T1I<(outs), (ins brtarget:$target), "b $target",
194 def tBfar : T1Ix2<(outs), (ins brtarget:$target),
195 "bl $target\t@ far jump",[]>;
197 def tBR_JTr : T1JTI<(outs),
198 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id),
199 "mov pc, $target \n\t.align\t2\n$jt",
200 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>;
204 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
205 // a two-value operand where a dag node expects two operands. :(
206 let isBranch = 1, isTerminator = 1 in
207 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
208 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
210 //===----------------------------------------------------------------------===//
211 // Load Store Instructions.
214 let canFoldAsLoad = 1 in
215 def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr),
216 "ldr", " $dst, $addr",
217 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>;
219 def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr),
220 "ldrb", " $dst, $addr",
221 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
223 def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr),
224 "ldrh", " $dst, $addr",
225 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
227 let AddedComplexity = 10 in
228 def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
229 "ldrsb", " $dst, $addr",
230 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
232 let AddedComplexity = 10 in
233 def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr),
234 "ldrsh", " $dst, $addr",
235 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
237 let canFoldAsLoad = 1 in
238 def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
239 "ldr", " $dst, $addr",
240 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>;
242 // Special instruction for restore. It cannot clobber condition register
243 // when it's expanded by eliminateCallFramePseudoInstr().
244 let canFoldAsLoad = 1, mayLoad = 1 in
245 def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr),
246 "ldr", " $dst, $addr", []>;
249 let canFoldAsLoad = 1 in
250 def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
251 "ldr", " $dst, $addr",
252 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
254 // Special LDR for loads from non-pc-relative constpools.
255 let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in
256 def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr),
257 "ldr", " $dst, $addr", []>;
259 def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr),
260 "str", " $src, $addr",
261 [(store tGPR:$src, t_addrmode_s4:$addr)]>;
263 def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr),
264 "strb", " $src, $addr",
265 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>;
267 def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr),
268 "strh", " $src, $addr",
269 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>;
271 def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
272 "str", " $src, $addr",
273 [(store tGPR:$src, t_addrmode_sp:$addr)]>;
275 let mayStore = 1 in {
276 // Special instruction for spill. It cannot clobber condition register
277 // when it's expanded by eliminateCallFramePseudoInstr().
278 def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr),
279 "str", " $src, $addr", []>;
282 //===----------------------------------------------------------------------===//
283 // Load / store multiple Instructions.
286 // TODO: A7-44: LDMIA - load multiple
287 // TODO: Allow these to be predicated
290 def tPOP : T1I<(outs reglist:$dst1, variable_ops), (ins),
294 def tPUSH : T1I<(outs), (ins reglist:$src1, variable_ops),
297 //===----------------------------------------------------------------------===//
298 // Arithmetic Instructions.
301 // Add with carry register
302 let isCommutable = 1, Uses = [CPSR] in
303 def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
304 "adc", " $dst, $rhs",
305 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>;
308 def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
309 "add", " $dst, $lhs, $rhs",
310 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>;
312 def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
313 "add", " $dst, $rhs",
314 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>;
317 let isCommutable = 1 in
318 def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
319 "add", " $dst, $lhs, $rhs",
320 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>;
322 let neverHasSideEffects = 1 in
323 def tADDhirr : T1pIt<(outs tGPR:$dst), (ins GPR:$lhs, GPR:$rhs),
324 "add", " $dst, $rhs @ addhirr", []>;
327 let isCommutable = 1 in
328 def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
329 "and", " $dst, $rhs",
330 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>;
333 def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
334 "asr", " $dst, $lhs, $rhs",
335 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>;
338 def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
339 "asr", " $dst, $rhs",
340 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>;
343 def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
344 "bic", " $dst, $rhs",
345 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>;
348 let Defs = [CPSR] in {
349 def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
350 "cmn", " $lhs, $rhs",
351 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
352 def tCMNZ : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
353 "cmn", " $lhs, $rhs",
354 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>;
358 let Defs = [CPSR] in {
359 def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
360 "cmp", " $lhs, $rhs",
361 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>;
362 def tCMPZi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs),
363 "cmp", " $lhs, $rhs",
364 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>;
369 let Defs = [CPSR] in {
370 def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
371 "cmp", " $lhs, $rhs",
372 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>;
373 def tCMPZr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
374 "cmp", " $lhs, $rhs",
375 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>;
377 // TODO: Make use of the followings cmp hi regs
378 def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
379 "cmp", " $lhs, $rhs", []>;
380 def tCMPZhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs),
381 "cmp", " $lhs, $rhs", []>;
386 let isCommutable = 1 in
387 def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
388 "eor", " $dst, $rhs",
389 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>;
392 def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
393 "lsl", " $dst, $lhs, $rhs",
394 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>;
397 def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
398 "lsl", " $dst, $rhs",
399 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>;
402 def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
403 "lsr", " $dst, $lhs, $rhs",
404 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>;
407 def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
408 "lsr", " $dst, $rhs",
409 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>;
412 def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src),
413 "mov", " $dst, $src",
414 [(set tGPR:$dst, imm0_255:$src)]>;
416 // TODO: A7-73: MOV(2) - mov setting flag.
419 let neverHasSideEffects = 1 in {
420 // FIXME: Make this predicable.
421 def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
422 "mov $dst, $src", []>;
424 def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src),
425 "movs $dst, $src", []>;
427 // FIXME: Make these predicable.
428 def tMOVhir2lor : T1I<(outs tGPR:$dst), (ins GPR:$src),
429 "mov $dst, $src\t@ hir2lor", []>;
430 def tMOVlor2hir : T1I<(outs GPR:$dst), (ins tGPR:$src),
431 "mov $dst, $src\t@ lor2hir", []>;
432 def tMOVhir2hir : T1I<(outs GPR:$dst), (ins GPR:$src),
433 "mov $dst, $src\t@ hir2hir", []>;
434 } // neverHasSideEffects
437 let isCommutable = 1 in
438 def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
439 "mul", " $dst, $rhs",
440 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>;
442 // move inverse register
443 def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
444 "mvn", " $dst, $src",
445 [(set tGPR:$dst, (not tGPR:$src))]>;
447 // bitwise or register
448 let isCommutable = 1 in
449 def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
450 "orr", " $dst, $rhs",
451 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>;
454 def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
455 "rev", " $dst, $src",
456 [(set tGPR:$dst, (bswap tGPR:$src))]>,
457 Requires<[IsThumb1Only, HasV6]>;
459 def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
460 "rev16", " $dst, $src",
462 (or (and (srl tGPR:$src, (i32 8)), 0xFF),
463 (or (and (shl tGPR:$src, (i32 8)), 0xFF00),
464 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000),
465 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>,
466 Requires<[IsThumb1Only, HasV6]>;
468 def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
469 "revsh", " $dst, $src",
472 (or (srl (and tGPR:$src, 0xFFFF), (i32 8)),
473 (shl tGPR:$src, (i32 8))), i16))]>,
474 Requires<[IsThumb1Only, HasV6]>;
476 // rotate right register
477 def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
478 "ror", " $dst, $rhs",
479 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>;
482 def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src),
483 "rsb", " $dst, $src, #0",
484 [(set tGPR:$dst, (ineg tGPR:$src))]>;
486 // Subtract with carry register
488 def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
489 "sbc", " $dst, $rhs",
490 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>;
492 // Subtract immediate
493 def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
494 "sub", " $dst, $lhs, $rhs",
495 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>;
497 def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
498 "sub", " $dst, $rhs",
499 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>;
502 def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs),
503 "sub", " $dst, $lhs, $rhs",
504 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>;
506 // TODO: A7-96: STMIA - store multiple.
508 def tSUBspi : T1It<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs),
509 "sub $dst, $rhs * 4", []>;
512 def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
513 "sxtb", " $dst, $src",
514 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>,
515 Requires<[IsThumb1Only, HasV6]>;
518 def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
519 "sxth", " $dst, $src",
520 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>,
521 Requires<[IsThumb1Only, HasV6]>;
524 let isCommutable = 1, Defs = [CPSR] in
525 def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs),
526 "tst", " $lhs, $rhs",
527 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>;
530 def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
531 "uxtb", " $dst, $src",
532 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>,
533 Requires<[IsThumb1Only, HasV6]>;
536 def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src),
537 "uxth", " $dst, $src",
538 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>,
539 Requires<[IsThumb1Only, HasV6]>;
542 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
543 // Expanded by the scheduler into a branch sequence.
544 // FIXME: Add actual movcc in IT blocks for Thumb2.
545 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
547 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
549 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
551 // tLEApcrel - Load a pc-relative address into a register without offending the
553 let Defs = [CPSR] in {
554 def tLEApcrel : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label),
555 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
556 "${:private}PCRELL${:uid}+4))\n"),
557 !strconcat("\tmovs $dst, #PCRELV${:uid}\n",
558 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
561 def tLEApcrelJT : T1Ix2<(outs tGPR:$dst), (ins i32imm:$label, i32imm:$id),
562 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
563 "${:private}PCRELL${:uid}+4))\n"),
564 !strconcat("\tmovs $dst, #PCRELV${:uid}\n",
565 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
569 //===----------------------------------------------------------------------===//
573 // __aeabi_read_tp preserves the registers r1-r3.
576 def tTPsoft : T1Ix2<(outs), (ins),
577 "bl __aeabi_read_tp",
578 [(set R0, ARMthread_pointer)]>;
581 //===----------------------------------------------------------------------===//
582 // Non-Instruction Patterns
586 def : TPat<(addc tGPR:$lhs, imm0_7:$rhs),
587 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
588 def : TPat<(addc tGPR:$lhs, imm8_255:$rhs),
589 (tADDi3 tGPR:$lhs, imm8_255:$rhs)>;
590 def : TPat<(addc tGPR:$lhs, tGPR:$rhs),
591 (tADDrr tGPR:$lhs, tGPR:$rhs)>;
593 // Subtract with carry
594 def : TPat<(addc tGPR:$lhs, imm0_7_neg:$rhs),
595 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
596 def : TPat<(addc tGPR:$lhs, imm8_255_neg:$rhs),
597 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
598 def : TPat<(subc tGPR:$lhs, tGPR:$rhs),
599 (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
601 // ConstantPool, GlobalAddress
602 def : TPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
603 def : TPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
606 def : TPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
607 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
610 def : TPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
611 def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
613 // Indirect calls to ARM routines
614 def : Tv5Pat<(ARMcall tGPR:$dst), (tBLXr tGPR:$dst)>;
616 // zextload i1 -> zextload i8
617 def : T1Pat<(zextloadi1 t_addrmode_s1:$addr),
618 (tLDRB t_addrmode_s1:$addr)>;
620 // extload -> zextload
621 def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
622 def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
623 def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
625 // If it's possible to use [r,r] address mode for sextload, select to
626 // ldr{b|h} + sxt{b|h} instead.
627 def : TPat<(sextloadi8 t_addrmode_s1:$addr),
628 (tSXTB (tLDRB t_addrmode_s1:$addr))>;
629 def : TPat<(sextloadi16 t_addrmode_s2:$addr),
630 (tSXTH (tLDRH t_addrmode_s2:$addr))>;
633 // Large immediate handling.
636 def : T1Pat<(i32 thumb_immshifted:$src),
637 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
638 (thumb_immshifted_shamt imm:$src))>;
640 def : T1Pat<(i32 imm0_255_comp:$src),
641 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;