1 //===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Chris Lattner and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb instruction set.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Thumb specific DAG Nodes.
18 def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
21 // TI - Thumb instruction.
23 // ThumbPat - Same as Pat<>, but requires that the compiler be in Thumb mode.
24 class ThumbPat<dag pattern, dag result> : Pat<pattern, result> {
25 list<Predicate> Predicates = [IsThumb];
28 class ThumbV5Pat<dag pattern, dag result> : Pat<pattern, result> {
29 list<Predicate> Predicates = [IsThumb, HasV5T];
32 class ThumbI<dag ops, AddrMode am, SizeFlagVal sz,
33 string asm, string cstr, list<dag> pattern>
34 // FIXME: Set all opcodes to 0 for now.
35 : InstARM<0, am, sz, IndexModeNone, cstr> {
37 let OperandList = ops;
39 let Pattern = pattern;
40 list<Predicate> Predicates = [IsThumb];
43 class TI<dag ops, string asm, list<dag> pattern>
44 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "", pattern>;
45 class TI1<dag ops, string asm, list<dag> pattern>
46 : ThumbI<ops, AddrModeT1, Size2Bytes, asm, "", pattern>;
47 class TI2<dag ops, string asm, list<dag> pattern>
48 : ThumbI<ops, AddrModeT2, Size2Bytes, asm, "", pattern>;
49 class TI4<dag ops, string asm, list<dag> pattern>
50 : ThumbI<ops, AddrModeT4, Size2Bytes, asm, "", pattern>;
51 class TIs<dag ops, string asm, list<dag> pattern>
52 : ThumbI<ops, AddrModeTs, Size2Bytes, asm, "", pattern>;
54 // Two-address instructions
55 class TIt<dag ops, string asm, list<dag> pattern>
56 : ThumbI<ops, AddrModeNone, Size2Bytes, asm, "$lhs = $dst", pattern>;
58 // BL, BLX(1) are translated by assembler into two instructions
59 class TIx2<dag ops, string asm, list<dag> pattern>
60 : ThumbI<ops, AddrModeNone, Size4Bytes, asm, "", pattern>;
63 class TJTI<dag ops, string asm, list<dag> pattern>
64 : ThumbI<ops, AddrModeNone, SizeSpecial, asm, "", pattern>;
66 def imm_neg_XFORM : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant(-(int)N->getValue(), MVT::i32);
69 def imm_comp_XFORM : SDNodeXForm<imm, [{
70 return CurDAG->getTargetConstant(~((uint32_t)N->getValue()), MVT::i32);
74 /// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
75 def imm0_7 : PatLeaf<(i32 imm), [{
76 return (uint32_t)N->getValue() < 8;
78 def imm0_7_neg : PatLeaf<(i32 imm), [{
79 return (uint32_t)-N->getValue() < 8;
82 def imm0_255 : PatLeaf<(i32 imm), [{
83 return (uint32_t)N->getValue() < 256;
85 def imm0_255_comp : PatLeaf<(i32 imm), [{
86 return ~((uint32_t)N->getValue()) < 256;
89 def imm8_255 : PatLeaf<(i32 imm), [{
90 return (uint32_t)N->getValue() >= 8 && (uint32_t)N->getValue() < 256;
92 def imm8_255_neg : PatLeaf<(i32 imm), [{
93 unsigned Val = -N->getValue();
94 return Val >= 8 && Val < 256;
97 // Break imm's up into two pieces: an immediate + a left shift.
98 // This uses thumb_immshifted to match and thumb_immshifted_val and
99 // thumb_immshifted_shamt to get the val/shift pieces.
100 def thumb_immshifted : PatLeaf<(imm), [{
101 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getValue());
104 def thumb_immshifted_val : SDNodeXForm<imm, [{
105 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getValue());
106 return CurDAG->getTargetConstant(V, MVT::i32);
109 def thumb_immshifted_shamt : SDNodeXForm<imm, [{
110 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getValue());
111 return CurDAG->getTargetConstant(V, MVT::i32);
114 // Define Thumb specific addressing modes.
116 // t_addrmode_rr := reg + reg
118 def t_addrmode_rr : Operand<i32>,
119 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
120 let PrintMethod = "printThumbAddrModeRROperand";
121 let MIOperandInfo = (ops GPR:$base, GPR:$offsreg);
124 // t_addrmode_s4 := reg + reg
127 def t_addrmode_s4 : Operand<i32>,
128 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> {
129 let PrintMethod = "printThumbAddrModeS4Operand";
130 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
133 // t_addrmode_s2 := reg + reg
136 def t_addrmode_s2 : Operand<i32>,
137 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> {
138 let PrintMethod = "printThumbAddrModeS2Operand";
139 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
142 // t_addrmode_s1 := reg + reg
145 def t_addrmode_s1 : Operand<i32>,
146 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> {
147 let PrintMethod = "printThumbAddrModeS1Operand";
148 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm, GPR:$offsreg);
151 // t_addrmode_sp := sp + imm8 * 4
153 def t_addrmode_sp : Operand<i32>,
154 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
155 let PrintMethod = "printThumbAddrModeSPOperand";
156 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
159 //===----------------------------------------------------------------------===//
160 // Miscellaneous Instructions.
163 def tADJCALLSTACKUP :
164 PseudoInst<(ops i32imm:$amt),
165 "@ tADJCALLSTACKUP $amt",
166 [(ARMcallseq_end imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
168 def tADJCALLSTACKDOWN :
169 PseudoInst<(ops i32imm:$amt),
170 "@ tADJCALLSTACKDOWN $amt",
171 [(ARMcallseq_start imm:$amt)]>, Imp<[SP],[SP]>, Requires<[IsThumb]>;
173 def tPICADD : TIt<(ops GPR:$dst, GPR:$lhs, pclabel:$cp),
174 "$cp:\n\tadd $dst, pc",
175 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>;
177 //===----------------------------------------------------------------------===//
178 // Control Flow Instructions.
181 let isReturn = 1, isTerminator = 1 in {
182 def tBX_RET : TI<(ops), "bx lr", [(ARMretflag)]>;
183 // Alternative return instruction used by vararg functions.
184 def tBX_RET_vararg : TI<(ops GPR:$dst), "bx $dst", []>;
187 // FIXME: remove when we have a way to marking a MI with these properties.
188 let isLoad = 1, isReturn = 1, isTerminator = 1 in
189 def tPOP_RET : TI<(ops reglist:$dst1, variable_ops),
192 let isCall = 1, noResults = 1,
193 Defs = [R0, R1, R2, R3, LR,
194 D0, D1, D2, D3, D4, D5, D6, D7] in {
195 def tBL : TIx2<(ops i32imm:$func, variable_ops),
197 [(ARMtcall tglobaladdr:$func)]>;
199 def tBLXi : TIx2<(ops i32imm:$func, variable_ops),
201 [(ARMcall tglobaladdr:$func)]>, Requires<[HasV5T]>;
202 def tBLXr : TI<(ops GPR:$dst, variable_ops),
204 [(ARMtcall GPR:$dst)]>, Requires<[HasV5T]>;
206 def tBX : TIx2<(ops GPR:$dst, variable_ops),
207 "cpy lr, pc\n\tbx $dst",
208 [(ARMcall_nolink GPR:$dst)]>;
211 let isBranch = 1, isTerminator = 1, noResults = 1 in {
212 let isBarrier = 1 in {
213 let isPredicable = 1 in
214 def tB : TI<(ops brtarget:$dst), "b $dst", [(br bb:$dst)]>;
217 def tBfar : TIx2<(ops brtarget:$dst), "bl $dst\t@ far jump", []>;
219 def tBR_JTr : TJTI<(ops GPR:$dst, jtblock_operand:$jt, i32imm:$id),
220 "cpy pc, $dst \n\t.align\t2\n$jt",
221 [(ARMbrjt GPR:$dst, tjumptable:$jt, imm:$id)]>;
225 let isBranch = 1, isTerminator = 1, noResults = 1 in
226 def tBcc : TI<(ops brtarget:$dst, ccop:$cc), "b$cc $dst",
227 [(ARMbrcond bb:$dst, imm:$cc)]>;
229 //===----------------------------------------------------------------------===//
230 // Load Store Instructions.
234 def tLDR : TI4<(ops GPR:$dst, t_addrmode_s4:$addr),
236 [(set GPR:$dst, (load t_addrmode_s4:$addr))]>;
238 def tLDRB : TI1<(ops GPR:$dst, t_addrmode_s1:$addr),
240 [(set GPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>;
242 def tLDRH : TI2<(ops GPR:$dst, t_addrmode_s2:$addr),
244 [(set GPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>;
246 def tLDRSB : TI1<(ops GPR:$dst, t_addrmode_rr:$addr),
248 [(set GPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
250 def tLDRSH : TI2<(ops GPR:$dst, t_addrmode_rr:$addr),
252 [(set GPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
254 def tLDRspi : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
256 [(set GPR:$dst, (load t_addrmode_sp:$addr))]>;
258 // Special instruction for restore. It cannot clobber condition register
259 // when it's expanded by eliminateCallFramePseudoInstr().
260 def tRestore : TIs<(ops GPR:$dst, t_addrmode_sp:$addr),
261 "ldr $dst, $addr", []>;
264 def tLDRpci : TIs<(ops GPR:$dst, i32imm:$addr),
266 [(set GPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>;
268 // Special LDR for loads from non-pc-relative constpools.
269 let isReMaterializable = 1 in
270 def tLDRcp : TIs<(ops GPR:$dst, i32imm:$addr),
271 "ldr $dst, $addr", []>;
275 def tSTR : TI4<(ops GPR:$src, t_addrmode_s4:$addr),
277 [(store GPR:$src, t_addrmode_s4:$addr)]>;
279 def tSTRB : TI1<(ops GPR:$src, t_addrmode_s1:$addr),
281 [(truncstorei8 GPR:$src, t_addrmode_s1:$addr)]>;
283 def tSTRH : TI2<(ops GPR:$src, t_addrmode_s2:$addr),
285 [(truncstorei16 GPR:$src, t_addrmode_s2:$addr)]>;
287 def tSTRspi : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
289 [(store GPR:$src, t_addrmode_sp:$addr)]>;
291 // Special instruction for spill. It cannot clobber condition register
292 // when it's expanded by eliminateCallFramePseudoInstr().
293 def tSpill : TIs<(ops GPR:$src, t_addrmode_sp:$addr),
294 "str $src, $addr", []>;
297 //===----------------------------------------------------------------------===//
298 // Load / store multiple Instructions.
301 // TODO: A7-44: LDMIA - load multiple
304 def tPOP : TI<(ops reglist:$dst1, variable_ops),
308 def tPUSH : TI<(ops reglist:$src1, variable_ops),
311 //===----------------------------------------------------------------------===//
312 // Arithmetic Instructions.
316 def tADC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
318 [(set GPR:$dst, (adde GPR:$lhs, GPR:$rhs))]>;
320 def tADDS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
321 "add $dst, $lhs, $rhs",
322 [(set GPR:$dst, (addc GPR:$lhs, GPR:$rhs))]>;
325 def tADDi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
326 "add $dst, $lhs, $rhs",
327 [(set GPR:$dst, (add GPR:$lhs, imm0_7:$rhs))]>;
329 def tADDi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
331 [(set GPR:$dst, (add GPR:$lhs, imm8_255:$rhs))]>;
333 def tADDrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
334 "add $dst, $lhs, $rhs",
335 [(set GPR:$dst, (add GPR:$lhs, GPR:$rhs))]>;
337 def tADDhirr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
338 "add $dst, $rhs", []>;
340 def tADDrPCi : TI<(ops GPR:$dst, i32imm:$rhs),
341 "add $dst, pc, $rhs * 4", []>;
342 def tADDrSPi : TI<(ops GPR:$dst, GPR:$sp, i32imm:$rhs),
343 "add $dst, $sp, $rhs * 4", []>;
344 def tADDspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
345 "add $dst, $rhs * 4", []>;
347 def tAND : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
349 [(set GPR:$dst, (and GPR:$lhs, GPR:$rhs))]>;
351 def tASRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
352 "asr $dst, $lhs, $rhs",
353 [(set GPR:$dst, (sra GPR:$lhs, imm:$rhs))]>;
355 def tASRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
357 [(set GPR:$dst, (sra GPR:$lhs, GPR:$rhs))]>;
359 def tBIC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
361 [(set GPR:$dst, (and GPR:$lhs, (not GPR:$rhs)))]>;
364 def tCMN : TI<(ops GPR:$lhs, GPR:$rhs),
366 [(ARMcmp GPR:$lhs, (ineg GPR:$rhs))]>;
368 def tCMPi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
370 [(ARMcmp GPR:$lhs, imm0_255:$rhs)]>;
372 def tCMPr : TI<(ops GPR:$lhs, GPR:$rhs),
374 [(ARMcmp GPR:$lhs, GPR:$rhs)]>;
376 def tTST : TI<(ops GPR:$lhs, GPR:$rhs),
378 [(ARMcmpNZ (and GPR:$lhs, GPR:$rhs), 0)]>;
380 def tCMNNZ : TI<(ops GPR:$lhs, GPR:$rhs),
382 [(ARMcmpNZ GPR:$lhs, (ineg GPR:$rhs))]>;
384 def tCMPNZi8 : TI<(ops GPR:$lhs, i32imm:$rhs),
386 [(ARMcmpNZ GPR:$lhs, imm0_255:$rhs)]>;
388 def tCMPNZr : TI<(ops GPR:$lhs, GPR:$rhs),
390 [(ARMcmpNZ GPR:$lhs, GPR:$rhs)]>;
392 // TODO: A7-37: CMP(3) - cmp hi regs
394 def tEOR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
396 [(set GPR:$dst, (xor GPR:$lhs, GPR:$rhs))]>;
398 def tLSLri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
399 "lsl $dst, $lhs, $rhs",
400 [(set GPR:$dst, (shl GPR:$lhs, imm:$rhs))]>;
402 def tLSLrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
404 [(set GPR:$dst, (shl GPR:$lhs, GPR:$rhs))]>;
406 def tLSRri : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
407 "lsr $dst, $lhs, $rhs",
408 [(set GPR:$dst, (srl GPR:$lhs, imm:$rhs))]>;
410 def tLSRrr : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
412 [(set GPR:$dst, (srl GPR:$lhs, GPR:$rhs))]>;
414 // FIXME: This is not rematerializable because mov changes the condition code.
415 def tMOVi8 : TI<(ops GPR:$dst, i32imm:$src),
417 [(set GPR:$dst, imm0_255:$src)]>;
419 // TODO: A7-73: MOV(2) - mov setting flag.
422 // Note: MOV(2) of two low regs updates the flags, so we emit this as 'cpy',
423 // which is MOV(3). This also supports high registers.
424 def tMOVr : TI<(ops GPR:$dst, GPR:$src),
425 "cpy $dst, $src", []>;
427 def tMUL : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
429 [(set GPR:$dst, (mul GPR:$lhs, GPR:$rhs))]>;
431 def tMVN : TI<(ops GPR:$dst, GPR:$src),
433 [(set GPR:$dst, (not GPR:$src))]>;
435 def tNEG : TI<(ops GPR:$dst, GPR:$src),
437 [(set GPR:$dst, (ineg GPR:$src))]>;
439 def tORR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
441 [(set GPR:$dst, (or GPR:$lhs, GPR:$rhs))]>;
444 def tREV : TI<(ops GPR:$dst, GPR:$src),
446 [(set GPR:$dst, (bswap GPR:$src))]>,
447 Requires<[IsThumb, HasV6]>;
449 def tREV16 : TI<(ops GPR:$dst, GPR:$src),
452 (or (and (srl GPR:$src, 8), 0xFF),
453 (or (and (shl GPR:$src, 8), 0xFF00),
454 (or (and (srl GPR:$src, 8), 0xFF0000),
455 (and (shl GPR:$src, 8), 0xFF000000)))))]>,
456 Requires<[IsThumb, HasV6]>;
458 def tREVSH : TI<(ops GPR:$dst, GPR:$src),
462 (or (srl (and GPR:$src, 0xFFFF), 8),
463 (shl GPR:$src, 8)), i16))]>,
464 Requires<[IsThumb, HasV6]>;
466 def tROR : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
468 [(set GPR:$dst, (rotr GPR:$lhs, GPR:$rhs))]>;
471 // Subtract with carry
472 def tSBC : TIt<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
474 [(set GPR:$dst, (sube GPR:$lhs, GPR:$rhs))]>;
476 def tSUBS : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
477 "sub $dst, $lhs, $rhs",
478 [(set GPR:$dst, (subc GPR:$lhs, GPR:$rhs))]>;
481 // TODO: A7-96: STMIA - store multiple.
483 def tSUBi3 : TI<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
484 "sub $dst, $lhs, $rhs",
485 [(set GPR:$dst, (add GPR:$lhs, imm0_7_neg:$rhs))]>;
487 def tSUBi8 : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
489 [(set GPR:$dst, (add GPR:$lhs, imm8_255_neg:$rhs))]>;
491 def tSUBrr : TI<(ops GPR:$dst, GPR:$lhs, GPR:$rhs),
492 "sub $dst, $lhs, $rhs",
493 [(set GPR:$dst, (sub GPR:$lhs, GPR:$rhs))]>;
495 def tSUBspi : TIt<(ops GPR:$dst, GPR:$lhs, i32imm:$rhs),
496 "sub $dst, $rhs * 4", []>;
498 def tSXTB : TI<(ops GPR:$dst, GPR:$src),
500 [(set GPR:$dst, (sext_inreg GPR:$src, i8))]>,
501 Requires<[IsThumb, HasV6]>;
502 def tSXTH : TI<(ops GPR:$dst, GPR:$src),
504 [(set GPR:$dst, (sext_inreg GPR:$src, i16))]>,
505 Requires<[IsThumb, HasV6]>;
508 def tUXTB : TI<(ops GPR:$dst, GPR:$src),
510 [(set GPR:$dst, (and GPR:$src, 0xFF))]>,
511 Requires<[IsThumb, HasV6]>;
512 def tUXTH : TI<(ops GPR:$dst, GPR:$src),
514 [(set GPR:$dst, (and GPR:$src, 0xFFFF))]>,
515 Requires<[IsThumb, HasV6]>;
518 // Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation.
519 // Expanded by the scheduler into a branch sequence.
520 let usesCustomDAGSchedInserter = 1 in // Expanded by the scheduler.
522 PseudoInst<(ops GPR:$dst, GPR:$false, GPR:$true, ccop:$cc),
524 [(set GPR:$dst, (ARMcmov GPR:$false, GPR:$true, imm:$cc))]>;
526 // tLEApcrel - Load a pc-relative address into a register without offending the
528 def tLEApcrel : TIx2<(ops GPR:$dst, i32imm:$label),
529 !strconcat(!strconcat(".set PCRELV${:uid}, ($label-(",
530 "${:private}PCRELL${:uid}+4))\n"),
531 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
532 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
535 def tLEApcrelJT : TIx2<(ops GPR:$dst, i32imm:$label, i32imm:$id),
536 !strconcat(!strconcat(".set PCRELV${:uid}, (${label}_${id:no_hash}-(",
537 "${:private}PCRELL${:uid}+4))\n"),
538 !strconcat("\tmov $dst, #PCRELV${:uid}\n",
539 "${:private}PCRELL${:uid}:\n\tadd $dst, pc")),
542 //===----------------------------------------------------------------------===//
546 // __aeabi_read_tp preserves the registers r1-r3.
549 def tTPsoft : TIx2<(ops),
550 "bl __aeabi_read_tp",
551 [(set R0, ARMthread_pointer)]>;
554 //===----------------------------------------------------------------------===//
555 // Non-Instruction Patterns
558 // ConstantPool, GlobalAddress
559 def : ThumbPat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
560 def : ThumbPat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>;
563 def : ThumbPat<(ARMWrapperJT tjumptable:$dst, imm:$id),
564 (tLEApcrelJT tjumptable:$dst, imm:$id)>;
567 def : ThumbPat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>;
568 def : ThumbV5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>;
570 // Indirect calls to ARM routines
571 def : ThumbV5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>;
573 // zextload i1 -> zextload i8
574 def : ThumbPat<(zextloadi1 t_addrmode_s1:$addr),
575 (tLDRB t_addrmode_s1:$addr)>;
577 // extload -> zextload
578 def : ThumbPat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
579 def : ThumbPat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>;
580 def : ThumbPat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>;
582 // truncstore i1 -> truncstore i8
583 def : ThumbPat<(truncstorei1 GPR:$src, t_addrmode_s1:$dst),
584 (tSTRB GPR:$src, t_addrmode_s1:$dst)>;
586 // Large immediate handling.
589 def : ThumbPat<(i32 thumb_immshifted:$src),
590 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
591 (thumb_immshifted_shamt imm:$src))>;
593 def : ThumbPat<(i32 imm0_255_comp:$src),
594 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;