1 //===- ARMInstrThumb2.td - Thumb2 support for ARM -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Thumb2 instruction set.
12 //===----------------------------------------------------------------------===//
14 // Shifted operands. No register controlled shifts for Thumb2.
15 // Note: We do not support rrx shifted operands yet.
16 def t2_so_reg : Operand<i32>, // reg imm
17 ComplexPattern<i32, 2, "SelectShifterOperand",
19 let PrintMethod = "printSOOperand";
20 let MIOperandInfo = (ops GPR, i32imm);
23 def LO16 : SDNodeXForm<imm, [{
24 // Transformation function: shift the immediate value down into the low bits.
25 return getI32Imm((unsigned short)N->getZExtValue());
28 def HI16 : SDNodeXForm<imm, [{
29 // Transformation function: shift the immediate value down into the low bits.
30 return getI32Imm((unsigned)N->getZExtValue() >> 16);
33 def imm16high : PatLeaf<(i32 imm), [{
34 // Returns true if all bits out of the [31..16] range are 0.
35 return ((N->getZExtValue() & 0xFFFF0000ULL) == N->getZExtValue());
38 def imm16high0xffff : PatLeaf<(i32 imm), [{
39 // Returns true if lo 16 bits are set and this is a 32-bit value.
40 return ((N->getZExtValue() & 0x0000FFFFULL) == 0xFFFFULL);
43 def imm0_4095 : PatLeaf<(i32 imm), [{
44 return (uint32_t)N->getZExtValue() < 4096;
47 def imm0_4095_neg : PatLeaf<(i32 imm), [{
48 return (uint32_t)-N->getZExtValue() < 4096;
51 def imm0_65535 : PatLeaf<(i32 imm), [{
52 return N->getZExtValue() < 65536;
55 // A6.3.2 Modified immediate constants in Thumb instructions (#<const>)
56 // FIXME: Move it the the addrmode matcher code.
57 def t2_so_imm : PatLeaf<(i32 imm), [{
58 uint64_t v = N->getZExtValue();
59 if (v == 0 || v > 0xffffffffUL) return false;
60 // variant1 - 0b0000x - 8-bit which could be zero (not supported for now)
62 // variant2 - 0b00nnx - 8-bit repeated inside the 32-bit room
63 unsigned hi16 = (unsigned)(v >> 16);
64 unsigned lo16 = (unsigned)(v & 0xffffUL);
65 bool valid = (hi16 == lo16) && (
66 (v & 0x00ff00ffUL) == 0 || // type 0001x
67 (v & 0xff00ff00UL) == 0 || // type 0010x
68 ((lo16 >> 8) == (lo16 & 0xff))); // type 0011x
69 if (valid) return true;
71 // variant3 - 0b01000..0b11111 - 8-bit shifted inside the 32-bit room
72 unsigned shift = CountLeadingZeros_32(v);
73 uint64_t mask = (0xff000000ULL >> shift);
74 // If valid, it is type 01000 + shift
75 return ((shift < 24) && (v & mask) > 0) && ((v & (~mask)) == 0);
79 //===----------------------------------------------------------------------===//
80 // Thumb-2 to cover the functionality of the ARM instruction set.
83 /// T2I_bin_irs - Defines a set of (op reg, {so_imm|reg|so_reg}) patterns for a
84 // binary operation that produces a value.
85 multiclass T2I_bin_irs<string opc, PatFrag opnode> {
87 def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
88 !strconcat(opc, " $dst, $lhs, $rhs"),
89 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
90 Requires<[HasThumb2]>;
92 def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
93 !strconcat(opc, " $dst, $lhs, $rhs"),
94 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
95 Requires<[HasThumb2]>;
97 def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
98 !strconcat(opc, " $dst, $lhs, $rhs"),
99 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
100 Requires<[HasThumb2]>;
103 /// T2I_bin_s_irs - Similar to T2I_bin_irs except it sets the 's' bit so the
104 /// instruction modifies the CPSR register.
105 let Defs = [CPSR] in {
106 multiclass T2I_bin_s_irs<string opc, PatFrag opnode> {
108 def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
109 !strconcat(opc, "s $dst, $lhs, $rhs"),
110 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
111 Requires<[HasThumb2]>;
114 def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs),
115 !strconcat(opc, "s $dst, $lhs, $rhs"),
116 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
117 Requires<[HasThumb2]>;
120 def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs),
121 !strconcat(opc, "s $dst, $lhs, $rhs"),
122 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
123 Requires<[HasThumb2]>;
127 /// T2I_bin_c_irs - Similar to T2I_bin_irs except it uses the 's' bit. Also the
128 /// instruction can optionally set the CPSR register.
129 let Uses = [CPSR] in {
130 multiclass T2I_bin_c_irs<string opc, PatFrag opnode> {
132 def ri : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs, cc_out:$s),
133 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
134 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_imm:$rhs))]>,
135 Requires<[HasThumb2]>;
138 def rr : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs, cc_out:$s),
139 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
140 [(set GPR:$dst, (opnode GPR:$lhs, GPR:$rhs))]>,
141 Requires<[HasThumb2]>;
144 def rs : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t2_so_reg:$rhs, cc_out:$s),
145 !strconcat(opc, "${s} $dst, $lhs, $rhs"),
146 [(set GPR:$dst, (opnode GPR:$lhs, t2_so_reg:$rhs))]>,
147 Requires<[HasThumb2]>;
151 //===----------------------------------------------------------------------===//
152 // Arithmetic Instructions.
155 //===----------------------------------------------------------------------===//
156 // Move Instructions.
158 def tMOVi16 : PseudoInst<(outs GPR:$dst), (ins i32imm:$src),
160 [(set GPR:$dst, imm0_65535:$src)]>,
161 Requires<[HasThumb2]>;
163 let Constraints = "$src = $dst" in
164 def tMOVTi16 : PseudoInst<(outs GPR:$dst), (ins GPR:$src, i32imm:$imm),
166 [(set GPR:$dst, (or (and GPR:$src, 0xffff),
168 Requires<[HasThumb2]>;
170 def : Pat<(and (or GPR:$src, imm16high:$imm1), imm16high0xffff:$imm2),
171 (tMOVTi16 GPR:$src, (HI16 imm16high:$imm1))>,
172 Requires<[HasThumb2]>;
174 def : Pat<(i32 imm:$imm),
175 (tMOVTi16 (tMOVi16 (LO16 imm:$imm)),(HI16 imm:$imm))>,
176 Requires<[HasThumb2]>;
178 //===----------------------------------------------------------------------===//
179 // Arithmetic Instructions.
181 defm t2ADD : T2I_bin_irs <"add", BinOpFrag<(add node:$LHS, node:$RHS)>>;
182 defm t2SUB : T2I_bin_irs <"sub", BinOpFrag<(sub node:$LHS, node:$RHS)>>;
184 def tADDri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
185 "add $dst, $lhs, $rhs",
186 [(set GPR:$dst, (add GPR:$lhs, imm0_4095:$rhs))]>,
187 Requires<[HasThumb2]>;
188 def tSUBri12 : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs),
189 "sub $dst, $lhs, $rhs",
190 [(set GPR:$dst, (add GPR:$lhs, imm0_4095_neg:$rhs))]>,
191 Requires<[HasThumb2]>;
193 defm t2ADDS : T2I_bin_s_irs<"add", BinOpFrag<(addc node:$LHS, node:$RHS)>>;
194 defm t2SUBS : T2I_bin_s_irs<"sub", BinOpFrag<(subc node:$LHS, node:$RHS)>>;
196 defm t2ADC : T2I_bin_c_irs<"adc", BinOpFrag<(adde node:$LHS, node:$RHS)>>;
197 defm t2SBC : T2I_bin_c_irs<"sbc", BinOpFrag<(sube node:$LHS, node:$RHS)>>;
200 def tMLS : PseudoInst<(outs GPR:$dst), (ins GPR:$a, GPR:$b, GPR:$c),
201 "mls $dst, $a, $b, $c",
202 [(set GPR:$dst, (sub GPR:$c, (mul GPR:$a, GPR:$b)))]>,
203 Requires<[HasThumb2]>;
205 def tORNrs : PseudoInst<(outs GPR:$dst), (ins GPR:$src1, t2_so_reg:$src2),
206 "orn $dst, $src1, $src2",
207 [(set GPR:$dst, (or GPR:$src1, (not t2_so_reg: $src2)))]>,
208 Requires<[HasThumb2]>;